JPS55114034A - Digital-to-analog converter - Google Patents

Digital-to-analog converter

Info

Publication number
JPS55114034A
JPS55114034A JP1974979A JP1974979A JPS55114034A JP S55114034 A JPS55114034 A JP S55114034A JP 1974979 A JP1974979 A JP 1974979A JP 1974979 A JP1974979 A JP 1974979A JP S55114034 A JPS55114034 A JP S55114034A
Authority
JP
Japan
Prior art keywords
circuit
memory
output
address
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1974979A
Other languages
Japanese (ja)
Inventor
Tatsuhiko Kawachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1974979A priority Critical patent/JPS55114034A/en
Publication of JPS55114034A publication Critical patent/JPS55114034A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make an input analog waveform and output analog waveform alike without increasing the capacity of a memory by correcting a difference in phase between the input and output waveforms.
CONSTITUTION: Memory 19 is stored with quantized analog signals. Subtracter circuit 22 calculates a difference in quantized data between address (m) and address m+1 of memory 19. Divider circuit 23 divides the above-mentioned subtraction result by (n). Synchronizing with the read timing of memory 19, 1st gate circuit 27 allows quantized data of address (m) in memory 19 to pass through. At every timing one (n)-th the read timing of memory 19, 2nd gate circuit 33 allows the output of divider circuit 23 to pass through. Adder circuit 34 adds the output of divider circuit 23 to that of the 2nd gate circuit. Then, D/A converter 36 receives the output of adder circuit 34. Smoothing circuit 37 smooths the output of D/A converter 36.
COPYRIGHT: (C)1980,JPO&Japio
JP1974979A 1979-02-23 1979-02-23 Digital-to-analog converter Pending JPS55114034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1974979A JPS55114034A (en) 1979-02-23 1979-02-23 Digital-to-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1974979A JPS55114034A (en) 1979-02-23 1979-02-23 Digital-to-analog converter

Publications (1)

Publication Number Publication Date
JPS55114034A true JPS55114034A (en) 1980-09-03

Family

ID=12007982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1974979A Pending JPS55114034A (en) 1979-02-23 1979-02-23 Digital-to-analog converter

Country Status (1)

Country Link
JP (1) JPS55114034A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6016087A (en) * 1983-06-24 1985-01-26 アールシーエー トムソン ライセンシング コーポレーシヨン Luminance and chrominance signal phase regulating method
JPH0360526A (en) * 1989-07-28 1991-03-15 Yokogawa Electric Corp D/a converting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6016087A (en) * 1983-06-24 1985-01-26 アールシーエー トムソン ライセンシング コーポレーシヨン Luminance and chrominance signal phase regulating method
JPH0360526A (en) * 1989-07-28 1991-03-15 Yokogawa Electric Corp D/a converting circuit

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