JPS5651180A - Video signal binary device - Google Patents

Video signal binary device

Info

Publication number
JPS5651180A
JPS5651180A JP12764979A JP12764979A JPS5651180A JP S5651180 A JPS5651180 A JP S5651180A JP 12764979 A JP12764979 A JP 12764979A JP 12764979 A JP12764979 A JP 12764979A JP S5651180 A JPS5651180 A JP S5651180A
Authority
JP
Japan
Prior art keywords
video signal
binary
register
output value
new output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12764979A
Other languages
Japanese (ja)
Inventor
Shinjiro Kawato
Yoji Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12764979A priority Critical patent/JPS5651180A/en
Publication of JPS5651180A publication Critical patent/JPS5651180A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To obtain a stable binary video signal, by deciding the binary on a basis of the relative relation between the level at a prescribed point, where the video signal should be decided as ''0'' and ''1'', and the signal level at points around the point above. CONSTITUTION:Video signal 9 is subjected to A/D conversion in 10; and when a new output value is obtained, shift registers 11 and 13 are shifted by one-picture element components, and a new output value is set. The first, the second, the (n+ 1)th and the (n+2)th values of register 11 and the second, the (n+1)th and the (n+2)th values of register 13 are input to binary deciding circuit 12, and circuit 12 decides ''0'' and ''1'' and outputs binary video signal 14, and the value of signal 14 is set to register 13. This operation is repeated each time a new output value is obtained from converter 10, thereby the binary video signal for the whole of the screen.
JP12764979A 1979-10-02 1979-10-02 Video signal binary device Pending JPS5651180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12764979A JPS5651180A (en) 1979-10-02 1979-10-02 Video signal binary device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12764979A JPS5651180A (en) 1979-10-02 1979-10-02 Video signal binary device

Publications (1)

Publication Number Publication Date
JPS5651180A true JPS5651180A (en) 1981-05-08

Family

ID=14965306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12764979A Pending JPS5651180A (en) 1979-10-02 1979-10-02 Video signal binary device

Country Status (1)

Country Link
JP (1) JPS5651180A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102583A (en) * 1986-10-20 1988-05-07 Fujitsu Ltd Video signal digitizing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102583A (en) * 1986-10-20 1988-05-07 Fujitsu Ltd Video signal digitizing circuit

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