JPS567553A - Digital type fm modulator - Google Patents
Digital type fm modulatorInfo
- Publication number
- JPS567553A JPS567553A JP8357879A JP8357879A JPS567553A JP S567553 A JPS567553 A JP S567553A JP 8357879 A JP8357879 A JP 8357879A JP 8357879 A JP8357879 A JP 8357879A JP S567553 A JPS567553 A JP S567553A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminal
- pulse
- signal
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/12—Modulator circuits; Transmitter circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To decrease the deterioration to nonlinear type amplification, by producing the frequency modulation signal in spectrum shape through almost continuous switching of the frequency and the phase at the switching circuit. CONSTITUTION:The signal of logic ''1'' is always given to the input of the first stage of the shift register 14 from the terminal 16. Shift operation is made for the delay circuit 13 with the output pulse of the shift pulse generator 17 in unit delay time tau. Each output signal of the registers 14, 151-156 corresponding to tauo+Ktau (where; tauo=mtau, K=1, 2...6) for the delay time from the circuit 13 is selected at the switching circuit 18 and fed to the output terminal 9. The signal at the terminal 9 is fed to the reset circuit 19 to form reset pulse and the circuit 13 is reset with the pulse. The circuit 18 is switched for control through the switching control circuit 21 in response to the modulator input from the input terminal 6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8357879A JPS5840387B2 (en) | 1979-06-29 | 1979-06-29 | Digital FM modulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8357879A JPS5840387B2 (en) | 1979-06-29 | 1979-06-29 | Digital FM modulator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS567553A true JPS567553A (en) | 1981-01-26 |
JPS5840387B2 JPS5840387B2 (en) | 1983-09-05 |
Family
ID=13806373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8357879A Expired JPS5840387B2 (en) | 1979-06-29 | 1979-06-29 | Digital FM modulator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5840387B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58120353A (en) * | 1982-01-13 | 1983-07-18 | Fujitsu Ltd | Msk modulating system |
JPS58135154U (en) * | 1982-03-05 | 1983-09-10 | 日立電子株式会社 | MSK modulation circuit |
JP2006339944A (en) * | 2005-06-01 | 2006-12-14 | Seiko Epson Corp | Modulation circuit and demodulation circuit |
-
1979
- 1979-06-29 JP JP8357879A patent/JPS5840387B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58120353A (en) * | 1982-01-13 | 1983-07-18 | Fujitsu Ltd | Msk modulating system |
JPS58135154U (en) * | 1982-03-05 | 1983-09-10 | 日立電子株式会社 | MSK modulation circuit |
JP2006339944A (en) * | 2005-06-01 | 2006-12-14 | Seiko Epson Corp | Modulation circuit and demodulation circuit |
JP4701841B2 (en) * | 2005-06-01 | 2011-06-15 | セイコーエプソン株式会社 | Modulation circuit and demodulation circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5840387B2 (en) | 1983-09-05 |
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