JPS5840387B2 - Digital FM modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency modulator constituted by a digital circuit, and is particularly directed to a frequency modulator to which spectrum shaping technology for effective frequency utilization can be applied, and which is also suitable for LSI integration. It is.

Mobile communication devices used in mobile communication systems, such as mobile phones, are required to be economical and able to be mass-produced, have low power consumption, and have a narrow modulation spectrum so that frequencies can be used effectively.

A modulator that satisfies these conditions is 1) composed of digital logic elements that are compatible with LSI integration, il) performs frequency modulation with little signal deterioration for a saturation type amplifier with high power efficiency, and 111 ) It is considered optimal to apply spectrum shaping technology that narrows the spectral bandwidth of this frequency modulated wave.

Phase continuous FSK (MSK) with a modulation index of 0.5 is a frequency modulation method with a relatively narrow frequency spectrum bandwidth.
;minimum 5hift keying).

As a conventional MSK modulator constructed of digital logic elements, the one shown in FIG. 1 is known.

The clock pulse from the oscillator 1 is divided into 1/N and (N+1) by frequency dividers 2 and 3, respectively, and the outputs of these equal frequency dividers 2 and 3 are sent to a modulation index converter by a switching circuit 4. 5.

The switching circuit 4 is controlled to be switched by the modulated signal from the input terminal 6 through the switching control circuit I.

The converter 5 divides the input phase continuous FSK signal with a modulation index of 1 into half to convert the modulation index to 0.5.

The modulation index-converted signal is processed by a phase-locked loop (PLL).
) is supplied to the output terminal 9 through the circuit 8.

In this modulator, the output center frequency 'b''-f.

, when the clock period is T, the frequency f of the oscillator 10 and the division ratio N of the frequency divider 2 are set as follows.

fl 1 D 2foT 0=-() [()2-1) (1) f22foTD 2fT N--()-1) D (2) At this time, the FSK signal obtained by switching in the switching circuit 4 is not switched. The phase changes continuously even at the moment of change.

Since this FSK signal has a continuous phase, it is characterized by a relatively narrow spectral bandwidth compared to an FSK signal whose phase is discontinuous.

PLL 8 was added to make this spectrum even narrower.

When the bandwidth of the low pass filter (LPF) of PLL f3 is narrowed, the modulation phase changes more smoothly and the spectrum becomes narrower.

However, in order to smoothly change the phase of the PLL 8, the analog operating characteristics of the PLL 8 must be adjusted using its low-pass filter.

Incidentally, as a modulator composed of digital logic elements, the one shown in FIG. 2 has also been considered.

The PSK modulation circuit 12 is controlled by the modulation signal from the oscillator terminal 6 through the control circuit 11, and from this -7F)B
PSK signal is generated and its output is MSK by PLL 8
converted into a signal.

In the case of this modulator, PLL is also used to perform spectrum shaping.
8 had the disadvantage that the design was complicated.

This invention uses a delay circuit, a switching circuit, and a switching control circuit as main components, and generates a spectrum-shaped frequency modulation signal by switching the frequency and phase almost continuously in the switching circuit, and its purpose is to adjust F is composed of unnecessary digital logic elements and is suitable for LSI integration.
The purpose is to obtain an M modulator.

FIG. 3 shows an embodiment of the wave modulator according to the present invention.

For example, m + n stages (n and m are natural numbers) of delay circuits 13 each formed of a shift register are provided.

In this delay circuit 13, the output of the first m-stage shift register 4 and each output of each of the shift registers 151 to 156 constituting the next n stages (n-6 in this example) can be respectively taken out. ing.

A logic n 1n signal is always applied to the first stage input of the shift register 4 from the terminal 16.

The delay circuit 13 is a shift pulse generator 1 with a unit delay time τ.
A shift operation is performed by the output pulse No. 7.

The delay time from the delay circuit 13 is τ.

The output signals of the registers 4 and 151 to 156 corresponding to +kr (where τ.-mT, =L2...6) are selected by the switching circuit 18 and supplied to the output terminal 9.

Further, the signal of this output terminal 9 is supplied to a reset circuit 19, and a reset pulse is generated by the reset circuit 19.
This resets the delay circuit 13.

Waveform shaping is not performed on the output of the switching circuit 18 (if the delay circuit 13 can be reset, the reset circuit 19 may be a simple conductive wire).

The switching circuit 18 is switched and controlled via a switching control circuit 21 in response to the modulator input from the input terminal 6.

FIG. 4 shows temporal changes in the outputs of the registers 14, 14□, . . ., 151°, 152, . . . .

Registers 141, 142, . . . are stages forming the register 14.

First, at time 1=00, all the shift registers are reset and their respective output signals are O''.

The "l" signal is always applied to the first register 141, and the register at the next stage is set to the ``1'' state every time τ.

The switching circuit 18 switches the (m+k)th register 15k (fourth
In the figure, when the output terminal (=1) is connected to the reset circuit 19, the (m+k)th register 15k is set to 1"
When the state reaches time t=m+1, this register 15
1 output f? 1? 1 signal is fed back to registers 14 and 15 via switching circuit 18 and reset circuit 19.

As a result, all registers 14 and 15 are reset and return to the initial reset state.

If the switching circuit 18 remains as it is, a pulse having a period of (τo + kr) is taken out at the output terminal 9.

If the switching control circuit 21 moves the contacts of the switching circuit 18 one contact at a time in response to the input from the input terminal 60 of the modulator, the delay time (τo + kr) changes little by little, so the output pulse at the output terminal 9 changes accordingly. The frequency changes almost continuously.

FIG. 5 shows the relationship between delay time and frequency.

Note that the change in phase when switching the frequency is continuous because the registers are connected in cascade.

The state in which the phase changes is shown by the solid line in FIG.

In FIG. 6, black circles indicate times when the switching contacts are controlled.

Since the frequency is switched, the phase becomes a polygonal line.

In addition, in the figure, the phase change in the case of MSK is shown by a dotted line.

The above example shows a case where the number of switches is 7, but generally an n-stage register 15 is provided after the m-stage shift register 14.
If 15n are connected, the number of switching can be made to (n+1), so if n is increased, the change in frequency and phase becomes more continuous.

Spectrum shaping can be performed by the switching control circuit 21 in a manner equivalent to base frequency band limitation without manipulating the modulated output signal.

An example of such a switching control circuit 21 is shown in FIG.

The binary input value number from input terminal 6 with a clock period of T is 3.
The signal is supplied to the shift register 23 and clock generation circuit 24 of the stage.

The clock generation circuit 24 generates a clock pulse having a cycle of - (reaction to the example shown in FIG. 6) in synchronization with the input signal, and the clock pulse is supplied to the quarter frequency divider circuit 25.

The shift register 23 is shift-controlled by the output of the frequency dividing circuit 25 having a period T.

Each output of the shift register 23 and the input of the input terminal 60, as well as the outputs of the clock pulse generation circuit 24 and the frequency divider circuit 25 whose period is - are supplied to the read-only memory 26 as an address.

The memory 26 is read out four times within T periods in response to one input signal and the state up to three bits before it.

The read output is decoded by the decoder 27 and the switching circuit 18
select one of the fixed contacts.

That is, gates are connected between the fixed contacts of the switching circuit 18 and the output terminal 9, and one of the gates is controlled to be opened by the output of the decoder 27.

The switching control circuit 21 can control the spectrum by selecting the contents of the memory 26 in advance so that the output frequency (phase) does not suddenly change based on the input signal at the terminal 6 and the state of the previous input signal. can be restricted.

As the switching control circuit 21, in addition to the one shown in FIG. 7, a feedback type shown in FIG. 8 can be considered.

The modulator output at terminal 9 is frequency detected by demodulation circuit 28, and the difference between the signal detected by this circuit 28 and the input signal at terminal 60 is determined by circuit 29.

The difference signal of this output is 1'''II depending on the magnitude of the input.
091 is output, and this is supplied to a circuit 31 consisting of a shift register, a clock generator, a frequency dividing circuit, a memory, etc. as shown in FIG. controlled.

In this case, the contents of the memory are selected so that the frequency and phase of the output do not change suddenly, and the output switching circuit 1 of the circuit 31 is
It outputs a control signal indicating whether 8 remains the same, advances by 1, or is delayed by 1.

In this way, the error between the input signal and the output frequency can be kept small.

Note that in the modulator described above, the output is pulsed and has a waveform with a relatively small duty ratio.

Therefore, it may be possible to perform waveform shaping by adding a monostable multivibrator or the like to the output circuit.

As another method for this purpose, a bistable digital logic element may be connected to the output side of the modulator, that is, to the output terminal 9, as shown in FIG.

That is, the output terminal 9 is connected to the clock terminal CK of the delay flip-flop 32, and its 0 output is supplied to its data input terminal to form a 1/2 frequency divider circuit to obtain a waveform-shaped output at the terminal 33.

However, when this circuit is used, the frequency and modulation index are halved, so it is necessary to take this into consideration when designing the modulator.

When the input signal is analog, the spectral bandwidth of the modulated output can be narrowed by band-limiting the input analog signal in advance using a low-pass f-wave filter.

As explained above, according to the modulator of the present invention, a frequency modulated signal with little deterioration due to nonlinear amplification can be transmitted to an LSI.
It can be obtained with a configuration using digital logic circuit elements suitable for.

In addition, narrowband modulation is possible because a spectrum shaping method based on base frequency band limitation can be applied.

Therefore, it is useful as a modulator for mobile communication equipment that requires effective use of frequency spectrum and cost reduction due to LSI.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams showing conventional digital FM modulators, respectively, and FIG. 3 is a digital FM modulator according to the present invention.
A configuration diagram showing an embodiment of the M modulator, FIG. 4 is an output waveform diagram of the delay circuit for explaining the operation, and FIG. 5 is a diagram showing the relationship between the selected delay time and output frequency of the delay circuit. 6th
Figure 7 shows an example of the relationship between the input signal and the output phase.
8 and 8 are diagrams each showing a configuration example of a switching control circuit, and FIG. 9 is a diagram showing an example of a waveform shaping circuit. 6: input terminal, 9: output terminal, 13: delay circuit, 17:
Shift pulse generator, 18: switching circuit, 19: reset circuit, 21: switching control circuit.

Claims (1)

[Claims] 1. An (m+n) stage (m and n are natural numbers) delay circuit consisting of a delay element whose input is a "1'' signal, a delay element cascade-connected to it, and a (m+k) stage (m+k) stage (however, (k is an integer greater than or equal to 0 and less than or equal to n); a switching circuit that selects the output signal of the delay element; and a reset upon detecting that the output signal selected by this switching circuit transitions from a 00" signal to a "1" signal. a reset circuit that generates a pulse and causes the outputs of all the delay elements of the (m+n) stage delay circuit to become nO'' signals, and the period of the reset pulse corresponds to the input signal of the modulator. 1. A digital FM modulator, comprising: a switching control circuit for controlling the switching circuit; and a signal selected by the switching circuit is used as an output signal of the modulator.