JP2580833B2 - Frequency conversion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit, and more particularly, to a frequency conversion circuit including only a logic circuit.

[Conventional technology]

As a conventional frequency conversion circuit, for example, the one shown in FIG. 6 has been proposed. This frequency conversion circuit has an input terminal
The signal input to 31 is +1 in buffer amplifier 33 and power amplifier 35
It is amplified to about 0 dBm. The signal input to the input terminal 32 is amplified by the buffer amplifier 34. Each amplified signal is a balanced flattener composed of a diode mixer.
At 36, the sum and difference frequency components of each signal are output. Thereafter, unnecessary frequency components are filtered through a filter 37, amplified by a buffer amplifier 38, and an output signal whose frequency is converted to an output terminal 39 is obtained.

FIG. 7 shows another conventional frequency conversion circuit. In this frequency conversion circuit, a part of the signal input to the input terminals 41 and 42 is phase-converted by the π / 2 phase shift circuits 43 and 44. Then, in the multiplication circuits 45 and 46, the other part of the signal is cross-wise multiplied by the phase-converted signal,
Further, by adding each output in the adding circuit 47, an output signal whose frequency has been converted to an output terminal 48 is obtained.

That is, assuming that the signal at the input terminal 41 is cos (ω ₁ t + α) and the signal at the input terminal 42 is cos (ω ₂ t + β), the output terminal 48 that calculates these signals has cos [(ω ₁ −ω ₂ ) t +
(Α−β)], only the frequency of the difference between the two input signals appears. However, realizing a wide-band π / 2 phase shift circuit requires complicated digital signal processing or a multi-pole network, and is difficult to manufacture.

[Problems to be solved by the invention]

In the frequency conversion circuit shown in FIG. 6, the balanced modulator 36 generates the sum and difference frequencies of the two signals, so that the filter 37 for selecting and extracting one of the sum and the difference is provided with an external device. There is a problem that it is necessary as a component and it is difficult to realize circuit integration.

Further, since one input of the balanced modulator 36 requires an input of about 10 dBm, a small power amplifier 35 is required. Furthermore, considering the application of the frequency conversion circuit to a synthesizer or the like, since the input and output are often logic circuits, an interface circuit between a 50Ω RF circuit and the logic circuit is required. This further complicates the circuit.

On the other hand, the frequency conversion circuit of FIG.
4 is required, but in order to realize a wide-band π / 2 transfer circuit, complicated digital signal processing and a multi-pole network must be used. It is extremely difficult to configure

An object of the present invention is to provide a frequency conversion circuit that has a simple configuration and enables integration by solving these problems.

[Means for solving the problem]

The frequency conversion circuit according to the present invention includes first and second 2-bit Johnson counters that divide the first and second input signals into two signals that are divided by 1/4 and shifted by π / 2 phase, First and second exclusive NOR gates that take the exclusive OR of signals corresponding to the respective phase shifts of the 2-bit Johnson counter, and logic that takes the logical product of the positive logic and the negative logic of the outputs of these exclusive NOR gates It comprises a circuit and a latch circuit which is set and reset by the output of the logic circuit and outputs a signal.

Here, the logic circuit is configured to set the latch circuit when each output of the first and second exclusive NOR gates is a positive logic output, and to reset the latch circuit when each output is a negative logic output. .

[Action]

According to the present invention, it is possible to divide the first and second input signals by そ れ ぞ れ and to obtain a frequency signal having a frequency difference between the two signals as an output signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the frequency conversion circuit of the present invention. First input terminal 1 and second input terminal 2
Are connected to a first 2-bit Johnson counter 3 and a second 2-bit Johnson counter 4, respectively.
As shown in FIG. 2, for example, these 2-bit Johnson counters are composed of two flip-flops 11 and 12, and have one input terminal A and two output terminals B and C. Then, as shown in FIG. 3, the signal input to the input terminal A is frequency-divided by 1/4 and the signals shifted in phase by π / 2 are output from the output terminals B and C.

The first and second 2-bit Johnson counters 3, 4
Are connected to the first exclusive NOR gate 5 and the second exclusive NOR gate 5 so as to replace the outputs from the output terminals B and C, respectively.
To the exclusive NOR gate 6. Furthermore, these first
And the outputs of the second exclusive NOR gates 5 and 6 are input to the NAND gate 7 and the OR gate 8, respectively.

Then, the output of the NAND gate 7 is input to the set terminal of the RS latch circuit 9, and the output of the OR gate 8 is input to the reset terminal of the RS latch circuit 9.
The output is taken from.

Next, the operation of the circuit of FIG. 1 will be described with reference to the timing chart of FIG. Now, it is assumed that a signal of frequency f ₁₁ is input to the first input terminal 1 and a signal of frequency f ₁₂ is input to the second input terminal 2.

The signal a input to the first input terminal 1 is frequency-divided by the first 2-bit Johnson counter 3 into 1/4, and becomes two signals b and c shifted in phase by π / 2. Similarly, the signal c input to the second input terminal 2 is divided by a second 2-bit Johnson counter 4 into 1/4 and shifted by π / 2 in phase.
Signals d and e.

Then, the signals b and e are input to the first exclusive NOR gate 5 to output the signal g, and similarly, the signals c and f are input to the second exclusive NOR gate 6 to output the signal h.
The signals g and h are input to the set terminal and the reset terminal of the RS latch circuit 9 by inputting the signals ip and in of the logical product of the positive logic and the negative logic obtained through the NAND gate 7 and the OR gate 8, respectively. Output. here,
When both the signals g and h are “H”, the RS latch circuit 9 is set by the signal ip from the non-gate 7, and when both the signals g and h are “L”, the RS latch circuit is set by the signal in from the OR gate 8. 9 is reset.

As a result, the frequency f ₀ of the output signal j is 1/1 of the signal a.
4 minutes and division, 1/4 the difference in circumference of the signal d, that is, the _{f 0 = f 11/4-} f 12/4.

FIG. 5 shows one example of the frequency conversion circuit shown in FIG.
This is an example in which an FSK modulator that obtains an output frequency of 0.7 MHz ± 4.5 KHz is configured.

In FIG. 5, reference numeral 10 denotes a frequency conversion circuit having the configuration shown in FIG. 1, in which two frequency conversion circuits 10 are used. That is, the output signal from the voltage controlled oscillator 21 and the signal from the reference frequency oscillator 22 are converted into one frequency conversion circuit.
The frequency is converted in 10, and the frequency-converted signal is frequency-divided by the variable frequency divider 23 and input to the phase comparator 24. This phase comparator 24 compares the phase of the output of the reference frequency oscillator 22 with the output of the fixed frequency divider 25, and feeds back the output to the voltage controlled oscillator 21 through a loop filter 26, thereby providing a PLL ( Phase-locked loop). Further, after the output of the voltage controlled oscillator 21 is divided by the fixed divider 27, the divided signal and the signal of the reference frequency oscillator 22 are frequency-converted by another frequency conversion circuit 10 to obtain an FSK output. ing.

In this FSK modulator, an FSK output can be obtained by switching the frequency division ratio of the variable frequency divider 23 with data input from the data input terminal 28.

Here, the oscillation frequency of the voltage controlled oscillator 21 is set to 80 ± 1.8M
Hz, and the oscillation fraction of the reference frequency oscillator 22 is 42 MHz.

When the FSK modulator is constituted by the frequency conversion circuit of FIG. 1 in this way, as shown in this example, the ordinary FSK modulator is formed into a PLL synthesizer, and before and after the frequency conversion circuit operate at a logic level. In many cases, such as the frequency conversion circuit shown in FIG. 1, in which the input / output interface is constituted by a logic circuit, the logic → RF system (50
Ω), there is an advantage that the number of level conversion circuits from RF to logic is reduced.

〔The invention's effect〕

As described above, the present invention includes two 2-bit Johnson counters, two exclusive NOR gates, a logic circuit, and a latch circuit, and divides the first and second input signals into quarters, respectively. In addition, since a frequency signal having a frequency difference between the two signals can be obtained as an output signal, the frequency conversion circuit is composed of only a logic circuit, and an external filter, a power amplifier, and the like are not required, thereby simplifying the operation. In addition to realizing integration, there is an effect that frequency conversion can be performed over a wide band without requiring fine adjustment.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a frequency conversion circuit of the present invention,
FIG. 2 is a circuit diagram of a 2-bit Johnson counter, FIG. 3 is a timing diagram of a 2-bit Johnson counter, FIG. 4 is a signal timing diagram of each part of a to j of the frequency conversion circuit of FIG. 1, and FIG. FIG. 6 and FIG. 7 are circuit diagrams showing different conventional frequency conversion circuits in which the frequency conversion circuit of the present invention is applied to an FSK modulator. 1 1st input terminal 2 2nd input terminal 3 1st 2-bit Johnson counter 4 2nd 2-bit Johnson counter 5 1st exclusive NOR gate 6 ... Second exclusive NOR gate, 7 NAND gate, 8 OR gate, 9 RS latch circuit, 10 frequency conversion circuit, 11, 12 flip-flop, 21 voltage controlled oscillator, 22 Reference frequency oscillator, 23… Variable frequency divider, 24… Phase comparator, 25 …… Fixed frequency divider, 26 …… Loop filter, 27 …… Fixed frequency divider, 28 …… Data input terminal, 31, 32 …… Input terminal, 33,34 …… Buffer amplifier, 35 ……
Power amplifier, 36 ... balanced modulator (diode mixer),
37 ... Filter, 38 ... Buffer amplifier, 39 ... Output terminal, 4
1,42 input terminal, 43,44 π / 2 phase shift circuit, 45,46
Multiplication circuit, 47 addition circuit, 48 output terminal.

Claims (1)

(57) [Claims] 1. A first 2-bit Johnson counter which divides a first input signal by 1/4 and converts them into two signals having a phase difference of π / 2, and a second input signal by 1/4. A second 2-bit Johnson counter which is divided into two signals having a phase difference of π / 2, and first and second signals which are exclusive-ORed between signals of corresponding phases of the respective 2-bit Johnson counters Two exclusive NOR gates, a logic circuit for performing a logical AND operation on the outputs of the exclusive NOR gates, and a latch circuit which is set by the positive logic output and reset by the negative logic output to output a signal A frequency conversion circuit comprising: