JP3019434B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer which is one of basic elements constituting a frequency division multiplexing system widely used in the field of communications.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional frequency synthesizer. In FIG. 3, 1 is a reference oscillator, 2 is a frequency divider, 3 is a phase comparator, 4 is a loop filter (LPF), and 5 is a voltage control oscillator (Voltage Control Osc).
VCO), 6 is a programmable frequency divider.

The frequency divider 2 sets the frequency f _R of the reference oscillator 1 to M
The frequency is divided to generate a step frequency Δf of the following equation.

Δf = f _R / M (1) On the other hand, the programmable frequency divider 6 divides the output frequency f _{O of the} VCO 5 by a frequency dividing ratio N specified from the outside. The part consisting of the circuits 3, 4, 5, 6 is a phase locked loop (Pha
(se Lock Loop; PLL), and the frequencies of both inputs of the phase comparator 3 completely match in the synchronized state. At this time, since Δf = f _O / N (2), f _O = N · Δf (3), and a frequency synthesis output in Δf steps is obtained.

[0005]

The conventional frequency synthesizer has the following difficulties.

That is, the operating speed of the phase comparator 3 is basically Δf, and a component having a frequency Δf and its harmonic components are generated at its output. When these components are added to the VCO 5, the frequency modulation is performed. Output as spurious noise.
In order to prevent this, low-pass filtering is performed in the loop filter 4 to sufficiently suppress the component whose frequency is equal to or more than Δf. That is,
The bandwidth of the PLL must be smaller than Δf.
However, in this case, the phase noise caused by the internal noise of the VCO 5 is output without being sufficiently suppressed.

Therefore, it is extremely difficult to realize a frequency synthesizer having a smaller step of Δf and a wide frequency range (N is large) in the prior art.

[0008] The present invention overcomes the disadvantages of the prior art described above,
An object of the present invention is to realize a frequency synthesizer having a large frequency range with a small Δf step and a small phase noise.

[0009]

Frequency synthesizer of the present invention SUMMARY OF] is (the M is a natural number) counting modulo M per cycle output of the reference oscillator output of the reference oscillator by outputting a count value m M divides to step frequency
And a first phase converter that receives the modulo M count value m from the frequency divider and generates a reference phase signal by an operation of K · (m / M) (K is a natural number) the controlled and the circuit, the output phase by the control voltage step
N (N is a natural number) specified externally to the signal of the loop frequency
A voltage controlled oscillator for generating a signal of a required frequency multiplied by the by outputting the modulo N count n in accordance with the value N specified from the count-up external to the receiving every one cycle output of the voltage controlled oscillator A programmable frequency divider that divides the output of the voltage controlled oscillator by N, and receives the modulo N count value n from the programmable frequency divider to obtain K · (n
/ N), and a second phase conversion circuit for generating an output phase signal by an operation of: (N) modulo the output phase signal from the second phase conversion circuit and the reference phase signal from the first phase conversion circuit. an adder for generating the K difference, the the D / a converter for converting the analog signal undergoing modulo K difference, flat smooth City said control voltage in response to the output of the D / a converter from the adder and a loop filter for outputting said voltage system to control the.

The second phase conversion circuit includes a read-only memory for generating a value K / N for the externally designated value N, and a value K / N from the read-only memory.
N and a multiplier that receives the modulo N count value n from the programmable frequency divider.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the frequency synthesizer according to the present invention. In FIG. 1, reference numeral 7 denotes a phase conversion circuit;
Is a binary adder, 9 is a phase conversion circuit, 10 is a D / A converter, and the other configuration is the same as that of FIG. example
For example, the output frequency f0 of the VCO 5 is
Numerical value N specified externally to the signal (same as frequency division ratio N described later)
Signal). FIG. 2 shows the program frequency divider 6 and the phase conversion circuit 9 in FIG. 9
1 is a read-only memory (ReadOnlyMem) that generates a numerical value of K / N with respect to a numerical value N given from outside.
(ory: ROM), 92 is a multiplier.

The program frequency divider 6 outputs the VCO 5 output 1
The count is incremented every cycle, and the modulo N count value n (n =
0, 1, 2, ..., N-1). Since the outputs of the programmable frequency divider 6 and the ROM 91 are input to the multiplier 92, the output of the multiplier 92 ( the output of the phase conversion circuit 9) has θ ₀ = K · (n / N) (n = 0, 1,2, ..., N
-1) is obtained. That is, the phase conversion circuit
9 converts the phase by modulo N into the phase of modulo K
ing. Similarly, in the phase conversion circuit 7, θ _R =
A conversion phase of K · (m / M) (m = 0, 1, 2,..., M−1) is obtained. These phase conversion circuits 7 and 9 are
Set the phase by Juro M and Modulo N to a value from 0 to K.
Is converted to the modulo K phase to be taken, and the VCO 5
And the output phase of the frequency divider 2 can be compared.
You.

The adder 8 outputs the output level from the phase conversion circuit 7.
Difference between phase , θ _R and output phase θ ₀ from phase conversion circuit 9
( Θ _R −θ ₀ )
(Taking the modulo K difference) , the output phase of the frequency divider 2 and the
The phase difference from the output phase of the grammatical frequency divider 6 is output .
For example, a case where K = 8 will be described. Now, θ _R
Of when the phase is advanced one unit (1/8 period), the phase difference is as follows.

[0015]

If θ _O is ahead of θ _R by two units (2/8 cycle), the following is obtained.

[0017]

In this way, the phase difference can always be correctly detected by the modulo K binary addition. In addition, the speed of the phase difference detection operation is such that the operation speed of the count value n is the output frequency f _O of the VCO 5, and the phase difference is θ _R −θ _O = K (m / M−n / N) (6) (K / N) · f _O = (K / N) · NΔf = K · Δf (7), which is K times Δf. Typically, K is binary 8 bits, ie, 256, or larger as needed, and can be up to N.

As described above, in the present embodiment, a phase comparison (phase difference detection) operation can be performed much faster than in the conventional example of FIG. 3, and the output of the adder 8 performing the phase comparison operation is expressed by the following equation. According to (7), basically only the component of KΔf or its harmonic component is generated. Therefore, the bandwidth of the LPF 4 is as shown in FIG.
In comparison with the conventional example of the above, it is possible to obtain K times, that is, a much wider band by the equation (7). Therefore, the phase of the VCO 5 is firmly phase-locked to the phase of the reference oscillator 1, and the phase noise caused by the internal noise of the VCO 5 is reliably suppressed.

Since a small step width Δf means a large N, if K is selected to be about N in the equation (7), the speed of the phase comparator operation is almost the same as f ₀ itself. As a result, the bandwidth of the PLL (the bandwidth of the LPF 4) can be made sufficiently wide to effectively suppress the output phase noise caused by the internal noise of the VCO 5.

[0021]

According to the present invention, the following effects can be realized.

(1) It is possible to realize a frequency synthesizer having a PLL characteristic which is sufficiently wide even for a small step width Δf.

(2) As a result, output phase noise caused by internal noise of the VCO can be suppressed.

(3) Since the PLL can have a wide band, it is possible to realize a frequency synthesizer having a fast response to frequency setting.

(4) With the above characteristics, it can be applied to mobile communication requiring a small step width, frequency hopping spread spectrum communication requiring a high-speed response, and other various fields.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a programmable frequency divider 6 and a phase conversion circuit 9 in FIG.

FIG. 3 is a block diagram of an example of a conventional frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference oscillator 2 Divider 4 Loop filter 5 Voltage controlled oscillator 6 Programmable divider 7, 9 Phase conversion circuit 8 Adder 10 D / A converter

Claims (2)

(57) [Claims] 1. A modulo M counting up every period the output of the reference oscillator (M is a natural number) generates a signal having a step frequency output by M divides the reference oscillator by outputting a counted value m A first phase conversion circuit that receives the modulo M count value m from the frequency divider and generates a reference phase signal by an operation of K · (m / M) (K is a natural number); the controlled output phase the voltage
An externally specified value N (where N is
And natural number) a voltage controlled oscillator for generating a signal of a required frequency multiplied, and outputs the modulo N count n in accordance with the value N specified from the count-up external to the receiving every one cycle output of the voltage controlled oscillator By this means of the voltage controlled oscillator
A programmable frequency divider for dividing the output by N, and receiving the modulo N count value n from the programmable frequency divider,
A second phase conversion circuit for generating an output phase signal by an operation of (n / N), the output phase signal from the second phase conversion circuit, and the reference phase signal from the first phase conversion circuit an adder modulo K difference occurs between the flat smooth City receives a D / a converter for converting an analog signal, the output of the D / a converter receives the modulo K difference from the adder frequency synthesizer, characterized in that a loop filter for outputting to the voltage control as the control voltage. 2. The read-only memory according to claim 2, wherein said second phase conversion circuit generates a value K / N for said externally designated value N, and said value K from said read-only memory.
/ N and the modulo N from the programmable divider
The frequency synthesizer according to claim 1, further comprising a multiplier for receiving the count value (n).