JPH0567969A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To attain low spurious radiation in an output signal while keeping power consumption low in the frequency synthesizer employing a direct digital synthesizer. CONSTITUTION:An output of a direct digital synthesizer 1 is given to a frequency converter 19, in which the signal is mixed with a signal from a local oscillation source 17 at a mixer 16 and the frequency of the signal is converted into a high frequency. Then the converted output is used for a reference signal of a phase locked loop to decrease a frequency division ratio of a phase locked loop 8. Since the smaller the frequency division ratio is the, smaller the spurious radiation is, the spurious radiation in the output signal is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer with low spurious and low power consumption.

[0002]

2. Description of the Related Art FIG. 9 shows, for example, Japanese Patent Laid-Open No. 63-2965.
22 or a configuration example of a conventional frequency synthesizer shown in US Pat. No. 4,965,533. In the figure, 1 is a direct digital synthesizer, 2 is an output terminal of the direct digital synthesizer 1, 3 is a phase comparator, 4 is a loop filter, 5 is a voltage controlled oscillator, 6 is a coupler for extracting the output of the frequency synthesizer, and 7 is a frequency divider. A number N frequency divider, 8 is a phase locked loop including a phase comparator 3, a loop filter 4, a voltage controlled oscillator 5, a coupler 6 and a frequency divider 7, and 9 is an output terminal of the phase locked loop 8. .. FIG. 6 shows a configuration example of the direct digital synthesizer 1. In the figure, 10 is a clock, 11 is a phase accumulator, 12 is an input terminal for frequency setting data, 13 is a memory, 14 is a digital / analog converter, and 15 is a filter.

Next, the operation will be described. In the conventional frequency synthesizer shown in FIG. 9, a part of the output (frequency fo) of the voltage controlled oscillator 5 is taken out by the coupler 6, and the signal is frequency-divided by the frequency divider 7 having the frequency division number N to obtain the frequency. Is fo / N. Then, the phase comparator 3 compares the phase of the output signal of the frequency divider (frequency fo / N) with the output signal of the digital synthesizer 1 (frequency fd). When the output signal of the phase comparator 3 is applied to the voltage controlled oscillator 5 as a frequency control signal via the loop filter 4,
The phase locked loop operates so that fo / N and fd match. Output frequency f of the frequency synthesizer at this time
o is given by the following equation.

[0004]

[Equation 1]

Next, the operation of the direct digital synthesizer 1 will be described. Sine wave amplitude data for a predetermined phase is stored in the memory 13 in a digital amount. The phase accumulator 11 is a clock signal (frequency fck) of 1
For each cycle, according to the frequency setting data (k in decimal),
It is means for generating the phase information necessary for reading the amplitude data of the waveform from the memory 13. According to the phase information from the phase accumulator 11, the amplitude data (digital amount) of the waveform is output from the memory 13, and the digital / digital
The analog converter 14 converts the voltage value into an analog value. Then, the filter 15 filters the unnecessary wave output from the digital / analog converter 14. Here, assuming that the number of bits of the phase accumulator 11 is b, the output frequency fd of the direct digital synthesizer 1 is given by the following equation.

[0006]

[Equation 2]

Substituting equation (2) into equation (1), the output frequency fo of the frequency synthesizer is given by the following equation.

[0008]

[Equation 3]

In the frequency synthesizer according to this conventional configuration, by changing the frequency setting data k one by one,
Output frequency fo at the channel interval Δfo given by the following equation
Can be changed.

[0010]

[Equation 4]

In the direct digital synthesizer 1,
The amplitude data of the sine wave is quantized and stored in the memory 13. Therefore, waveform distortion occurs due to the roughness of the quantization. FIG. 11 shows an output spectrum (measurement value) of such a direct digital synthesizer 1. In the figure, spurs associated with quantization are observed. If the phase-locked loop 8 is configured using a signal with such spurious as a reference signal, spurious is also output to the output signal of the frequency synthesizer. Direct digital synthesizer 1 here
The power ratio of carrier and spurious at the output of
1, 2, ...), the power ratio Soi (i = 1, 2, ...) Of carrier wave and spurious at the output of the frequency synthesizer is given by the following equation.

[0012]

[Equation 5]

[0013]

[Equation 6]

[0014]

[Equation 7]

Here, fm is the detuning frequency from the carrier wave of spurious Si, Kp is the sensitivity of the phase comparator 3, Kv is the sensitivity of the voltage controlled oscillator 5, and F (fm) is the gain of the loop filter 4. From the equation (5), if the frequency division number N of the frequency divider 7 is reduced or the absolute value of H (fm) is reduced,
It can be seen that spurious in the output of the frequency synthesizer can be reduced. However, as shown in FIG. 11, since the interval between the spurious and the carrier is narrow, it is difficult to remove the spurious. Therefore, it is necessary to reduce the frequency division number N.

As a method of reducing the frequency division number N, first, it is conceivable to increase the frequency of the reference signal applied to the phase comparator 3, that is, the output frequency fd of the direct digital synthesizer 1. However, in general, if an attempt is made to directly increase the frequency of the output of the digital synthesizer 1, an ECL (Emitter Coupled Lo) capable of high-speed operation can be obtained.
gi) and other elements must be used, resulting in
As shown in FIG. 12, CMOS (Complementa)
ry Metal Oxide Semiconductor
(tor) element, the power consumption is significantly increased. As described above, the conventional frequency synthesizer has a problem that the power consumption of the digital synthesizer 1 directly increases when an attempt is made to reduce the spurious by increasing the frequency of the reference signal.

As a second method, instead of directly increasing the output frequency of the digital synthesizer, it is possible to convert the output to a high frequency by some means and use the converted signal as a reference signal. As a frequency synthesizer using a phase-locked loop as frequency conversion means,
For example, Japanese Patent Laid-Open No. 24-24633 shown in FIG.
There is a frequency synthesizer. An object of the present invention is to increase the frequency setting speed while improving the number of digits (accuracy) of the frequency. In the figure, 1a and 1b are the same direct digital synthesizers as in the above conventional example, 8 is a phase-locked loop having the same function as that shown in FIG. 9, 18 is a filter, and 26 is a multiplier using the phase-locked loop, 16 is a mixer for mixing the output of the frequency synthesizer and the output of the multiplier 26, and 19 is the direct digital synthesizer 1b and the multiplier 2
6, a mixer 16, and a filter 18, which is a frequency converter.

The frequency synthesizer is a frequency obtained by multiplying the output of the direct digital synthesizer 1b by the frequency dividing ratio of the fixed frequency divider 7 and the frequency of the output of the direct digital synthesizer by a multiplier using a phase synchronization loop 8. To. The output is the output of the voltage controlled oscillator 5 (frequency f0)
Are mixed by the mixer 16, and converted into a signal having a frequency of the difference between them by the filter 18. The phase of this signal is directly compared with the output of the digital synthesizer 1a to form a phase synchronization loop.

However, in the above configuration, the frequency converter 19
As for the spurious of the output signal of, the spurious increases from the equation (5) in proportion to the square of the division ratio.
It is the same as the spurious Soi in the frequency synthesizer shown in FIG. Therefore, even if the phase-locked loop 8 including the phase comparator 3, the loop filter 4, and the voltage controlled oscillator 5 is used.
Even if the frequency division ratio is 1, the spurious at the output terminal 9 is not improved at all. That is, the frequency synthesizer shown in FIG. 13 is suitable for generating a signal having a relatively low frequency in a narrow frequency interval, but is not suitable for obtaining a signal with less spurious.

[0020]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to obtain a frequency synthesizer with low spurious power consumption and low power consumption.

[0021]

The invention according to claim 1 (hereinafter,
The frequency synthesizer according to the first invention directly converts the output of the digital synthesizer into a high frequency by a frequency converter, and uses the output signal of the frequency converter as a reference signal source of the phase synchronization loop. ..

A frequency synthesizer according to the inventions of claims 2 and 3 (hereinafter referred to as the second invention) converts an output signal of the frequency synthesizer into a low frequency by a frequency converter, and outputs the output signal of the frequency converter. And a reference signal are compared to form a phase-locked loop.

[0023]

In the frequency synthesizer according to the first aspect of the invention, the output frequency of the low-frequency direct digital synthesizer with low power consumption is converted into a direct digital synthesizer by a frequency converter including a mixer, a local oscillator, and a filter. It is converted to a high frequency by adding the frequency of 1 and the frequency of the local source. The output of this frequency converter is used as the reference signal source of the phase locked loop to form a frequency synthesizer.

In the frequency synthesizer according to the second aspect of the invention, the output signal of the frequency synthesizer is converted into a low frequency by directly subtracting the output signal of the frequency synthesizer from the frequency of the digital synthesizer or the local oscillator. Then, by phase-detecting the low-frequency output and the reference signal, a phase-locked loop is constructed and a frequency synthesizer is constructed.

[0025]

EXAMPLES Example 1. An embodiment of the first invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention according to claim 1 and is shown in FIG.
Is a mixer for mixing frequencies, 17 is a local oscillation source composed of an oscillator such as a crystal oscillator, 18 is a filter, 1
Reference numeral 9 is a frequency converter composed of a mixer 16, a local oscillator 17, and a filter 18, and the other parts correspond to the same or corresponding parts as those of the conventional example shown in FIG.

Next, the operation will be described. In the frequency synthesizer according to the first aspect of the present invention, the output of the low-frequency direct digital synthesizer 1 with low power consumption (frequency fd) is mixed with the output of the local oscillation source 17 (frequency fxo) by the mixer 16, and the direct digital synthesizer is used. It is converted into a high frequency obtained by adding the output frequency of 1 and the output frequency of the local oscillation source 17. The output of the mixer 16 includes leaky waves of the local oscillation frequency and unnecessary waves such as image signals, and is filtered by the filter 18. The output frequency fc of the frequency converter 19 including the mixer 16, the local oscillation source 17, and the filter 18 is given by the following equation.

[0027]

[Equation 8]

Therefore, the output frequency fo of the frequency synthesizer in this case is given by the following equation in consideration of the equations (1) and (2).

[0029]

[Equation 9]

When the same output frequency fo is to be obtained from the equations (1) and (9), the frequency dividing ratio N ′ of the frequency synthesizer of FIG. 1 becomes N · fd / (fd + fxo), It can be made smaller than the frequency division ratio of the frequency synthesizer. At this time, before (fd) and after (fc) frequency conversion
Since the spurious (Si) does not change in, the output spurious can be reduced according to the ratio of N ′ and N according to the equation (5). Therefore, according to the present invention, the reference signal applied to the phase comparator 3 can be increased in frequency while using the low-frequency direct digital synthesizer 1 with low power consumption, and the output spurious can be suppressed by reducing the frequency division ratio.

Further, similar to the conventional frequency synthesizer, by changing the frequency setting data k one by one, Δf obtained by replacing N in the equation (4) with N '.
Frequency can be changed with o channel interval.

Example 2. In the above description, the clock 10 of the digital synthesizer 1 and the local oscillation source 17 are shown as different oscillators, but they may be shared as shown in FIG. In the figure, 20 is a common oscillator (frequency fxo), 21 is a frequency divider with a frequency division number m, and FIG.
The same or corresponding parts are designated by the same reference numerals.

Also in the second embodiment, the frequency division ratio N'of the frequency synthesizer of FIG. 2 is N.fd / (fd + fxo), which can be made smaller than that of the frequency synthesizer of FIG. The frequency of the signal can be increased, and output spurious can be suppressed by reducing the frequency division ratio.

On the other hand, the frequency setting interval is different from that shown in FIG. In the frequency synthesizer having the configuration shown in FIG.
The following relation holds between fck and fxo,

[0035]

[Equation 10]

Substituting equation (10) into equation (9), the output frequency fo of the frequency synthesizer is given by the following equation.

[0037]

[Equation 11]

Therefore, by changing the frequency setting data k one by one, the frequency can be changed at the channel interval of Δfo given by the following equation.

[0039]

[Equation 12]

Example 3. FIG. 3 is a block diagram showing an embodiment of the second invention, and the reference numeral in the drawing corresponds to the reference numeral of the conventional example shown in 9.

In the frequency synthesizer according to the present invention, the output of the frequency divider 7 (frequency fo / N) and the output of the local oscillation source 17 (frequency fxo) are mixed by the mixer 16, and the difference frequency given by the following equation is obtained. The filter 18 filters and outputs fr.

[0042]

[Equation 13]

The output of the frequency converter 19 (frequency fr
) And the output of the direct digital synthesizer 1 (frequency fd
) Is compared with the phase comparator 3. When the output is applied as a frequency control signal to the voltage controlled oscillator 5 via the loop filter 4, the phase locked loop 8 operates so that fr and fd in the equation (13) match. The output frequency fo of the frequency synthesizer at this time is given by the following equation.

[0044]

[Equation 14]

From this equation, the frequency division number N is obtained by the following equation.

[0046]

[Equation 15]

As can be seen from the equation (15), the frequency division number can be lowered by increasing the frequency fxo of the local oscillation source 17 of the frequency converter 19 without directly increasing the frequency fd of the digital synthesizer 1. Therefore, in the frequency synthesizer according to the present invention, a low frequency direct digital synthesizer 1 with low power consumption can be used while achieving low spurious by reducing the frequency division number.

In the second invention, it goes without saying that the clock 10 of the digital synthesizer 1 and the local oscillation source 17 of the frequency converter 19 can be commonly used as in the second embodiment.

Fourth Embodiment FIG. 4 is a block diagram showing another embodiment of the second invention. The difference from the third embodiment is that the digital synthesizer 1 is directly used as a local oscillation source in the frequency converter 19. A fixed local oscillation source 17 is used as the reference signal source of the input of the phase comparator 3.

In the frequency synthesizer having this structure, the output (frequency fo / N) of the frequency divider 7 is fed to the mixer 16
Is directly mixed with the output of the digital synthesizer 1 (frequency fd), and the difference frequency fr given by the following equation is filtered by the filter 18 and output.

[0051]

[Equation 16]

The signal output from the frequency converter 19 and the output of the local oscillation source 17 such as a crystal oscillator (frequency fx
and o) are compared in phase to form a phase locked loop 8. In the frequency synthesizer according to the present embodiment, the frequency dividing number N is expressed by the equation (15) and the output frequency fo is calculated by the equation (1) as in the third embodiment.
Given in 4). Therefore, the same effect as that of the third embodiment is obtained.

Embodiment 5 FIG. 5 is a block diagram showing another embodiment of the second invention. The difference from Embodiment 3 lies in the positions of the frequency converter 19 and the frequency divider 7 in the phase locked loop 8. It has been replaced.

In the phase locked loop having the configuration shown in FIG. 5, the output of the voltage controlled oscillator 5 (frequency fo) is mixed with the output of the local oscillation source 17 (frequency fxo) by the frequency converter 19, and the frequency of the difference between them is mixed. Convert to (fo-fxo). Further, the output of the frequency converter 19 is divided by N by the frequency divider 7.
Divide into. The phase of this is directly compared with the output (frequency fd) of the digital synthesizer 1 to form the phase locked loop 8. Output frequency fo of the frequency synthesizer at this time
Is given by

[0055]

[Equation 17]

From this equation, the frequency division number N is given by the following equation.

[0057]

[Equation 18]

As can be seen from the equation (18), the frequency division number can be lowered by increasing the frequency fxo of the local oscillation source 17 of the frequency converter 19 without directly increasing the frequency fd of the digital synthesizer 1. Therefore, the same effect as that of the third embodiment is obtained.

Embodiment 6 FIG. 6 is a block diagram showing another embodiment of the second invention. In the third embodiment, as the frequency converter 19, the output of the local oscillation source 17 (frequency fxo) and the output of the frequency divider 7 (output (frequency fxo
The output of the frequency (fo / N-fxo) of the difference of o / N) has been described, but as shown in FIG.
The output of 7 is multiplied by the frequency by the multiplier 26 and the output of the frequency divider 7 is mixed, and the difference frequency (fo / N
-H · fxo) may be output. Here, as the means for multiplying the frequency by h, in addition to the means described in the conventional example, the mixer 16 may be operated in a higher order. Also in this embodiment, the same effect as that of the third embodiment is obtained.

Embodiment 7 In the above description, as the direct digital synthesizer 1,
Clock 10, phase accumulator 11, memory 13,
The description has been given of the configuration of the digital / analog converter 14 and the IEEE 42nd issued in 1988.
Annual Frequency Control
It may be a direct digital synthesizer consisting of a clock and a phase accumulator that generates the rectangular wave shown on pages 352 to 356 of the Symposium Digest. FIG. 7 shows the configuration of a direct digital synthesizer that generates this rectangular wave. Even if a direct digital synthesizer having such a configuration is used, the same effect can be obtained.

Eighth Embodiment In the above description, the case where the frequency divider 7 is used as the phase locked loop 8 has been described, but the same effect can be obtained even if the sampling phase detector 22 is used as shown in FIG. Play.

[Embodiment 9] In the above description, the phase locked loop 8 is described by taking the analog phase locked loop as an example. However, the phase comparator 3 and the loop filter 4 may be a digital phase locked loop formed by an arithmetic circuit. Has the same effect.

[Embodiment 10] In the above description, description has been made with reference to the drawings composed of blocks corresponding to functions, but in the actual structure, it is not necessary to be divided into blocks, and silicon, gallium arsenide or the like is not necessary. It may be formed integrally with the semiconductor substrate or formed on a plurality of semiconductor substrates, and the same effect is obtained.

[0064]

As described above, according to the first aspect of the present invention, since the output of the direct digital synthesizer is directly converted into a high frequency by the frequency converter and used as the reference signal, the low frequency direct digital synthesizer with low power consumption is used. However, the frequency of the reference signal input to the phase comparator can be increased, whereby the frequency division number in the phase synchronization loop can be reduced, and as a result, spurious can be reduced.

According to the second aspect of the invention, since the output of the frequency synthesizer is converted to a low frequency by the frequency converter, the reference signal input to the phase comparator is used while using the low frequency direct digital synthesizer with low power consumption. It is possible to lower the frequency of the signal to be compared with, thereby reducing the frequency division number in the phase synchronization loop, and as a result, reducing spurious.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a first invention.

FIG. 2 is a configuration diagram showing another embodiment of the first invention.

FIG. 3 is a configuration diagram showing an embodiment of a second invention.

FIG. 4 is a configuration diagram showing another embodiment of the second invention.

FIG. 5 is a configuration diagram showing another embodiment of the second invention.

FIG. 6 is a configuration diagram showing another embodiment of the second invention.

FIG. 7 is a configuration diagram showing another embodiment of the direct digital synthesizer according to the first invention and the second invention.

FIG. 8 is a configuration diagram showing another embodiment of the phase locked loop in the first invention and the second invention.

FIG. 9 is a configuration diagram showing a conventional example of a frequency synthesizer.

FIG. 10 is a block diagram of a direct digital synthesizer.

FIG. 11 is a diagram showing an example of an output spectrum of a direct digital synthesizer.

FIG. 12 is a diagram showing a relationship between power consumption and operating frequency of an element used in a direct digital synthesizer.

FIG. 13 is a configuration diagram showing another conventional example of a frequency synthesizer.

[Explanation of symbols]

 1 Direct Digital Synthesizer 2 Output Terminal 3 Phase Comparator 4 Loop Filter 5 Voltage Controlled Oscillator 6 Coupler 7 Divider of Dividing Number N 8 Phase Lock Loop 9 Output Terminal 10 Clock 11 Phase Accumulator 12 Frequency Setting Data Input Terminal 13 Memory 14 Digital / Analog Converter 15 Filter 16 Mixer 17 Local Oscillation Source 18 Filter 19 Frequency Converter 20 Common Oscillator 21 Frequency Divider m Divider 22 Sampling Phase Detector 26 Multiplier

Claims (3)

[Claims] 1. A memory which is means for storing amplitude data of a waveform for a predetermined phase, and a phase accumulator which is means for generating phase information for reading the amplitude data of the waveform from the memory. And the amplitude data of the waveform output from the memory according to the instruction from the phase accumulator.
A direct digital synthesizer comprising a digital / analog converter for converting a digital signal into an analog signal and a clock for supplying a clock signal to the phase accumulator and the digital / analog converter is used as a reference signal source. In a frequency synthesizer having a phase-locked loop, the output of the direct digital synthesizer is converted to a high frequency by a frequency converter, and the output signal of the frequency converter is used as a reference signal source for the phase-locked loop. A frequency synthesizer comprising a phase-locked loop. 2. A memory which is means for storing amplitude data of a waveform for a predetermined phase, and a phase accumulator which is means for generating phase information for reading the amplitude data of the waveform from the memory. And the amplitude data of the waveform output from the memory according to the instruction from the phase accumulator.
A direct digital synthesizer comprising a digital / analog converter for converting a digital signal into an analog signal and a clock for supplying a clock signal to the phase accumulator and the digital / analog converter is used as a reference signal source. In a frequency synthesizer that constitutes a phase-locked loop, the output signal of the frequency synthesizer is converted to a low frequency by a frequency converter, and the phase-locked loop is obtained by comparing with a reference signal generated by the direct digital synthesizer. A frequency synthesizer characterized by being configured. 3. A frequency synthesizer in which a phase-locked loop is configured by using a local oscillator that generates a signal of a constant frequency as a reference signal source, and an output signal of the frequency synthesizer is an amplitude demultiplexer of a waveform with respect to a predetermined phase. -A memory which is a means for storing data, a phase accumulator which is a means for generating phase information for reading the amplitude data of a waveform from the memory, and an instruction from the phase accumulator Amplitude data of the waveform output from the memory
Frequency converter using a direct digital synthesizer composed of a digital / analog converter for converting a digital signal into an analog signal, and a clock for supplying a clock signal to the phase accumulator and the digital / analog converter. The frequency synthesizer is characterized in that a phase-locked loop is constructed by converting the frequency to a lower frequency and comparing with a reference signal generated by the local oscillator.