JP3145422B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Object of the invention]

[0002]

The present invention relates to relates to a frequency synthesizer that is required when creating an atomic oscillator including rubidium atomic oscillator, in particular, the input signal is given frequency from an oscillator such as a crystal oscillator is f ₁ center frequency and frequency modulating the is related to the frequency synthesizer for _{f 1 P 0 + f 2 K} 0/2 M a and a maximum frequency shift allowed to generate an output signal which is f ₂ K _H / ₂ ^M.

[0003]

2. Description of the Related Art Conventionally, as a frequency synthesizer of this kind, for example, a carrier signal of several tens MHz is input to a variable phase circuit having a varactor diode as a capacitance of an LC resonance circuit, and a sine wave signal is phase-controlled. There has been proposed a device in which a frequency modulation signal is created by inputting a voltage.

[0004]

[Problems to be solved] However, the conventional frequency synthesizer has the disadvantage that (i) the center frequency and the maximum frequency deviation cannot be set with high accuracy, and (ii) the center frequency is caused by the characteristic distortion of the varactor diode. And (iii) it is extremely difficult to generate a high-precision signal required by a rubidium atomic oscillator or the like.As a result, (iv) a rubidium atomic oscillator or the like is suitably used. There was a disadvantage that it was not possible to oscillate.

Therefore, in order to eliminate these drawbacks, the present invention modulates the frequency of an input signal having a frequency of f ₁ given from an oscillator such as a crystal oscillator to obtain a center frequency of f ₁ P ₀ + f ₂ K. ₀ / ^2M and maximum frequency deviation is f ₂
A frequency synthesizer for allowing generating an output signal which is K _H / 2 ^M there is provided cents.

[0006]

Configuration of the Invention

[0007]

[Solution to Problem] The solution to the problem provided by the present invention is as follows. Receives an input signal with frequency f ₁
And the first synthesized signal having the frequency f ₁ P ₀ and the frequency f
₁ / P ₁ and (= f ₂₎ a is to generate a second combined signal <br/> first frequency synthesis circuit which forces out, respectively therewith (20), before
Serial second composite signal is frequency receiving f ₂ K _3/2 ^M a is you output a modulated signal is generated modulated signal generator circuit (3
0), the second composite signal with the modulation signal and the received by <br/> center frequency f ₂ K _0/2 ^M a and a maximum frequency shift f
A ₂ K _H / ₂ ^M a is frequency modulated shifted signals generated you output frequency shift circuit (40), wherein
The modulated signal is set to 1
First flip-flop for holding and outputting for the clock period
-Up (41), the frequency _{f 0 (= f 2 K 0} /2 M; 0 ≦ K
Data K ₀ specifying ₀ ≦ 2 ^M −1) and maximum frequency deviation
_{specify; (0 ≦ K H ≦ 2} M -1 = f 2 K H / 2 M) f H
Receiving the modulated data K _H and the modulated signal,
Data K ₀ + K _H or data K ₀ -K _H according to the value
A first full adder (42) for outputting, the first full adder
Said al data K ₀ + K _H or data K ₀ -K _H No.
Two composite signals are used as clock signals for one clock period
A second flip-flop (43) for holding and outputting
The input data is referred to as the second combined signal as a clock signal.
To hold and output for one clock period.
Flip-flop (45) from the third flip-flop
Data _An-1 and the data from the second flip-flop
Data K ₀ + K _H or data K ₀ receives -K _H data A
_n (= data A _n-1 + K ₀ + K _H , or = data A
out _n-1 + a K ₀ -K _H) to said third flip-flop
A second full adder (44), said third flip-flop.
Sine wave data Y _n in response to data A _n-1
Output memory (46), and sine wave from the memory
Digital analyzer that receives data and outputs analog signal Y
Frequency shift circuit (40) having log converter (48)
When the first composite signal and the shift signal and the medium <br/> heart frequency received a is _{f 1 P 0 + f 2 K} 0/2 M a and the maximum frequency shift at f ₂ K _H / ₂ ^M the second frequency synthesis circuit for outputting a third engagement <br/> formed signal is frequency modulated (five
0) is the frequency synthesizer device having a ".

[0008]

The frequency synthesizing apparatus according to the present invention has the following features. Frequency is f
_{The first} signal having a frequency of f ₁ P ₀ in response to an input signal of 1
And the second signal whose frequency is f ₁ / P ₁ (= f ₂ )
A first frequency synthesizer circuit to force out, respectively it combined signal and to generate a frequency receiving said second combined signal f ₂
Receiving a modulation signal generation circuit you output a modulated signal is generated which is K _3/2 ^M, the second composite signal with the said modulation signal
Only the center frequency is a frequency shift circuit you generates and outputs a frequency-modulated shift signal is f ₂ K _0/2 ^M a and a maximum frequency shift f ₂ K _H / ₂ ^M, wherein Second
The modulated signal is used for one
1st flip-flop that holds and outputs for the same period
Flop, the frequency _{f 0 (= f 2 K 0} /2 M; 0 ≦ K 0 ≦ 2 M -
Data K ₀ specifying 1) and the maximum frequency shift f _H (= f
^{_{2 K H / 2 M; 0}} ≦ K H ≦ 2 data specifying ^M -1)
Receiving K _H and the modulation signal and according to the value of the modulation signal
The data K ₀ + K _H or the data K ₀ −K _H is output.
1 full adder, data K ₀ + K from the first full adder
_H or the data K ₀ -K _H to the second synthesized signal.
Clock signal for one clock period and output
2 flip-flops, and input data to the second flip-flop.
The synthesized signal is kept as a clock signal for one clock period.
A third flip-flop for holding and outputting the third flip-flop.
Data _An-1 from the flip-flop and the second flip-flop.
Data K ₀ + K _H or data K ₀ −K _{H from the} flop
Receiving data A _n (= data _{A n-1 + K 0 +} K H, or
Others are = data _{A n-1 + K 0 -K} H) said third flip the
A second full adder for outputting to the flip-flop,
Receiving data _An-1 from the lip flop
Memory and outputs the data Y _n, and a sine wave from the memory
Digital analyzer that receives data and outputs analog signal Y
A frequency shift circuit having a log converter, the first engagement <br/> formed signal and the shift signal and the center frequency received a f ₁ P
_{0 + f 2 K 0/2} M a and a maximum frequency shift f ₂ K _H /
Since 2 ^M a is the third synthesis signal is generated that is frequency-modulated and a second frequency synthesizer circuit for outputting,
(i) the frequency is the center frequency of the input signal is f ₁ f _{1
P 0 + f 2 K 0/} 2 M a and a maximum frequency shift f ₂ K _H
/ 2 ^M to generate a frequency-modulated output signal, and (ii) a rational number K ₃ and an integer K ₀ ,
By simply designating K _H , the frequency modulation signal having the desired center frequency and the desired maximum frequency shift is generated using the desired modulation frequency.

[0009]

Next, a preferred embodiment of a frequency synthesizer according to the present invention will be described in detail with reference to the accompanying drawings.

However, the embodiments described below are:
It is described for the purpose of facilitating or facilitating the understanding of the present invention and is not described for limiting the present invention.

In other words, each element disclosed in the embodiments described below includes all design changes and equivalent replacements that fall within the spirit and scope of the present invention.

(Attached drawing)

FIG. 1 is a block diagram showing an embodiment of a frequency synthesizer according to the present invention.

[0014] Figure 2 is a block diagram for showing in detail a portion of the embodiment shown in FIG. 1, in particular, shows a frequency synthesis circuit 20.

FIG. 3 is a block diagram showing a part of the embodiment shown in FIG. 1 in detail, and particularly shows a frequency shift circuit 40 .

[0016] Figure 4 is a block diagram for showing in detail a portion of the embodiment shown in FIG. 1, in particular, shows a frequency synthesis circuit 50.

(Configuration of Embodiment)

First, the configuration of an embodiment of the frequency synthesizer according to the present invention will be described in detail with reference to FIGS.

Overall configuration

Reference numeral 10 denotes a frequency synthesizer according to the present invention, and an appropriate signal source (for example, a crystal oscillator; not shown)
From an analog input signal or a digital input signal having a frequency of f ₁ (hereinafter, only the analog input signal will be described), and a digital signal having a frequency of f ₁ P ₀ (“ A digital signal whose frequency is f ₁ / P ₁ (indicated as “f ₂ ” for convenience), also called “digital composite signal”; P ₀ is a positive integer.
(Also referred to as "digital composite signal"; P ₁ is a positive integer) first each occurrence and, a frequency synthesis circuit 20 for outputting the second output terminal, a second output of the frequency synthesizer circuit 20 digital modulation signal frequency from the digital composite signal given frequency from the frequency synthesizing circuit 20 is connected to an f ₁ / P ₁ (i.e., f ₂₎ is f ₂ K _3/2 ^M to the end (K ₃ is a positive rational number; M comprises a modulation signal generating circuit 30 for allowing generating a positive integer).

In the frequency synthesizer 10 according to the present invention, first and second input terminals are connected to a second output terminal of the frequency synthesizer circuit 20 and an output terminal of the modulation signal generating circuit 30 , respectively. and has a frequency synthesizer circuit 20 is given frequency from f ₁ / P ₁ (i.e., f ₂₎ is a digital composite signal and a frequency applied from the modulation signal generation circuit 30 is f ₂ K _3/2
^The center frequency is f ₂ K ₀ from the digital modulation signal of ^M.
/ 2 ^M (referred to as “f ₀ ” for convenience) and a frequency-modulated analog signal having a maximum frequency shift of f ₂ K _H / 2 ^M (referred to as “f _H ”) (also referred to as “shift signal”). K
_0, K _H is the frequency shift circuit 40 for outputting from the output terminal to generate a positive integer), first against the output terminal of the first output terminal and the frequency shift circuit 40 of the frequency synthesizer circuit 20 ,
A frequency synthesizing circuit to which second input terminals are respectively connected;
Frequency given from 20 is f ₁ P ₀ digital composite signal and the center frequency supplied from the frequency shift circuit 40 is f ₂ K _0/2 ^M a and the maximum frequency deviation f ₂ K _H / ₂ ^M
In a frequency modulated center frequency and a shift signal _{f 1 P 0 + f 2 K} 0/2 M a and a maximum frequency shift f ₂
A frequency synthesizing circuit 50 for generating a frequency-modulated digital signal of K _H / 2 ^M (also referred to as a “digital synthesized signal”) and outputting it from an output terminal is provided.

Frequency synthesis circuit 20

The frequency synthesis circuit 20, a frequency from the analog input signal frequency applied to input terminal is f ₁ is f ₁
A comparator 21 for generating a digital signal is the first input frequency is connected is supplied to a digital signal and a second input is f ₁ to the output terminal of the comparator 21 frequency is a phase detector 22 for outputting a voltage signal corresponding to the phase difference determines a phase difference between the digital signal is f ₁ (also referred to as a "divided signal"), the phase detector 22 The input terminal is connected to the output terminal. The voltage signal output from the phase detector 22 is integrated, held internally, and output (specifically, when the voltage signal output from the phase detector 22 is 0, the internal When the voltage signal output from the phase detector 22 is not 0, the integrated value held by the phase detector 22 is added to the internally held integrated value. And a loop filter 23 for holding and outputting the data.

The frequency synthesis circuit 20 also outputs an oscillation signal the oscillation frequency is f ₁ P ₀ according to the output signal of the loop filter 23 is input is connected to the output terminal of the loop filter 23 Voltage controlled crystal oscillator 24
When the frequency of an output signal oscillation signal frequency is input supplied from the voltage controlled crystal oscillator 24 is connected to the output terminal of the voltage controlled crystal oscillator 24 is f ₁ P ₀ from the first output terminal toward input of combining circuit 50 output and the frequency from the second output terminal is inclusion and distributor 25 for outputting an oscillation signal is f ₁ P _0.

The frequency synthesizing circuit 20 further has an input terminal connected to the second output terminal of the distributor 25 and a frequency f.
An amplifier 26 for amplifying and outputting appropriate to ₁ P ₀ at which the oscillation signal, the oscillation signal frequency is f ₁ P ₀ is input is connected to the output terminal of the amplifier 26 1 / P _0-divided to a frequency is inclusion of a frequency divider 27 for providing a digital signal is f ₁ (i.e. frequency-divided signal) to the second input of phase detector 22.

The frequency synthesizing circuit 20 also divides a digital signal having an input terminal connected to the output terminal of the comparator 21 and having a frequency of f ₁ by 1 / P ₁ to have a frequency of f _1. /
A frequency divider 28 for generating a digital composite signal of P ₁ (that is, f ₂ ) and providing the digital composite signal to the modulation signal generation circuit 30 and the frequency shift circuit 40 is included.

Frequency shift circuit 40

The frequency shift circuit 40 includes the frequency synthesizer 20
The clock input terminal and the data input terminal are respectively connected to the second output terminal of the second circuit and the output terminal of the modulation signal generating circuit 30 , and the frequency given from the frequency synthesis circuit 20 is f ₂
Digital composite signal frequencies provided from the modulation signal generation circuit 30 as a clock signal is a D-type Furipufuroppu 41 for holding a modulated signal is f ₂ K _3/2 ^M by one clock period is, D-type frequency f ₀ the first input terminal to the output end provided to the second input terminal is connected to the flip-flop _{41 (= f 2 K 0/} 2 M; 0 ≦ K 0 ≦ 2 M
Data K ₀ that specify -1) and the maximum frequency deviation f _H (=
particular 0 ≦ K _H ≦ 2 modulation signal ^M -1) is frequency and data K _H given from D-type flip-flop 41 to specify an ^{_{f 2 K 3/2 M;}} f 2 K H / 2 M In order to determine the sign of the data K _H according to the value of the digit (for example, when the value of the specific digit is 0, it is determined to be + and when it is 1, it is determined to be −), and then added to each other and output as data K ₀ ± K _H And an N-bit full adder 42. Here, K ₀ ± K _H means 2 ^M / f ₃ K that takes a value of K ₀ + K _H for T seconds and a value of K ₀ −K _H for T seconds in synchronization with the clock signal.
₃ sec refers to the period process (but _{^{2T <2 M / f 3 K}} 3)
.

The frequency shift circuit 40 includes a full adder 42
Has a data input terminal connected to the output terminal thereof and a clock input terminal connected to the output terminal of the frequency synthesis circuit 20. The frequency f ₀ is obtained from the data K ₀ ± K _H provided from the full adder 42. ± f _H frequency-modulated data K ₀ ±
A D-type flip-flop 43 for generating K _H , one input terminal of which is connected to the output terminal of the D-type flip-flop 43, and data _An-1 and D-type data supplied to the other input terminal The data K ₀ ± K _{H applied} to one input terminal from the flip-flop 43 are added to each other to obtain data A _n−1 + K
_And an M-bit full adder 44 for outputting as ₀ ± K _H (= A _n ). Here, f ₀ ± f _H is K ₀
In cycle process of ± K _H, when the K ₀ + K _H a frequency _{f 0 + f H, K 0} -K frequency when the _H is f ₀
It says that it is a -f _H.

The frequency shift circuit 40 further includes a full adder 44
The one input terminal is connected to the output terminal and the other of the second frequency provided from a frequency synthesizer circuit 20 is connected to the output terminal of the input end frequency synthesizer circuit 20 is f ₂
A D-type flip-flop 45 of the M bits for holding the digital signal by one clock period of data A _n given from the full adder 44 as the clock signal is, the output terminal of the D-type flip-flop 45 output frequencies from the data a _n of the D-type flip-flop 45 inputs are connected is f ₀ ± f _H sine wave data Y _n = round english (us)
L-bit read-only memory 46 for creating [(2 ^L -1) {1 + sin (2πA _n / ^2M )} / 2], and read-only memory
The input terminal is connected to the output terminal of 46 and includes an L-bit (for example, 8-bit) D-type flip-flop 47 for simultaneously outputting an L-bit output. Here, round [] means that, when a numerical value in [] has a decimal part, the decimal part is rounded off.

The input terminal of the frequency shift circuit 40 is connected to the output terminal of the D-type flip-flop 47, and the frequency given from the D-type flip-flop 47 is f _0.
± frequency sine wave data Y _n for is f _H is f ₀ ± f _H
Is the analog signal Y = asin2π (f ₀ + f _H w
(t)) t a digital-to-analog converter 48 for converting
The input terminal is connected to the output terminal of the digital-to-analog converter 48, and the analog signal Y having a frequency of f ₀ ± f _H given from the digital-to-analog converter 48 is appropriately amplified and a frequency synthesis circuit 50 is provided. Amplifier for output to
And 49. Here, w (t) refers to a rectangular wave whose period synchronized with the clock signal is 2 ^M / f ₃ K ₃ seconds, the first T seconds being 1 and the second T seconds being −1. . A is a desired coefficient.

Frequency synthesis circuit 50

The frequency synthesis circuit 50, a first synthesized signal frequency supplied from a connected and a frequency synthesizer circuit 20 is f ₁ P ₀ to the output terminal of the input end frequency synthesizer circuit 20 suitably An amplifier 51 for amplifying and outputting, and an amplifier
One input terminal is connected to the output terminal of 51, and the synthesized signal whose frequency given from the amplifier 51 is f ₁ P ₀ and the frequency f ₁ P ₀ + f ₀ ± f given to the other input terminal. _H
And a mixer 52 for outputting a mixed signal which is a product of the combined signal of the two.

The frequency synthesizing circuit 50 has a frequency component whose input terminal is connected to the output terminal of the mixer 52 and whose frequency of the mixed signal given from the mixer 52 is other than f ₀ ± f _H. , A comparator 53A connected to the output terminal of the band filter 53 for generating a digital signal having a frequency of f ₀ ± f _H , and an output terminal of the frequency shift circuit 40 . Is connected to the input terminal, and the frequency given from the frequency shift circuit 40 is f ₀ ±
analog signal Y is f _H and bandpass filter 54 for removing high frequency noise and low frequency noise, the connected and frequency to the output terminal of the bandpass filter 54 is f ₀ ± f _H
And a comparator 55 for creating a digital signal.

The frequency synthesis circuit 50 further includes comparators 53A, 55
A digital signal whose frequency is f ₀ ± f _H given from the band-pass filter 53 via the comparator 53A and a band-pass filter
A phase detector 56 for obtaining a phase difference between the digital signal having a frequency f ₀ ± f _H given through a comparator 55 and outputting a voltage signal corresponding to the phase difference; The input terminal is connected to the output terminal of the detector 56. The voltage signal output from the phase detector 56 is integrated, held internally, and output (specifically, the voltage signal output from the phase detector 56 becomes 0).
In this case, the integrated value held therein is held and output as it is, and the voltage signal output from the phase detector 56 is 0.
If not, a loop filter 57 for adding the integral value of the voltage signal to the integral value held therein and holding the same internally and outputting the same is included.

In addition, the frequency synthesizing circuit 50 has an input terminal connected to the output terminal of the loop filter 57, and oscillates in accordance with the output signal of the loop filter 57 to oscillate at a frequency f ₁ P ₀ +.
A voltage-controlled crystal oscillator 58 for outputting an oscillation signal of f ₀ ± f _H , and an input terminal connected to an output terminal of the voltage-controlled crystal oscillator 58 and having a frequency f ₁ given from the voltage-controlled crystal oscillator 58 P ₀ + f ₀ ± f frequency f ₁ P from the output to and the second output terminal of the oscillation signal as a combined signal from the first output terminal of the _{H 0} + f ₀ ± f _H distributor 59 for outputting an oscillation signal of And an input terminal thereof is connected to the second output terminal of the distributor 59 to appropriately amplify the oscillation signal of the frequency f ₁ P ₀ + f ₀ ± f _H toward the other input terminal of the mixer 52. And an amplifier 59A for outputting. Where the frequency f
The oscillation signal of ₁ P ₀ + f ₀ ± f _H has a modulation frequency of f ₂ K
_3/2 is ^M, the center frequency is and the maximum frequency deviation is f ₁ P ₀ + f ₀ is a frequency modulated synthesized signal is f _H.

(Operation of Embodiment)

Further, the operation of one embodiment of the frequency synthesizer according to the present invention will be described in detail with reference to FIGS.

The frequency synthesizer 10 according to the present invention includes an analog input signal or a digital input signal (here, analog input signal) whose frequency is f ₁ given from an appropriate signal source (for example, a crystal oscillator; not shown) to an input terminal. Only the input signal will be described), so that the center frequency is f ₁ P ₀ + f ₂
K _0/2 ^M (= f ₁ P ₀ + f ₀ ) and the maximum frequency shift is f
_A frequency-modulated composite signal of ₂ K _H / 2 ^M (= f _H ) is created and output from the output terminal. This will be described in detail for each component.

Frequency synthesis circuit 20

The frequency synthesizing circuit 20 operates as described in detail below. The frequency synthesizing circuit 20 converts an analog input signal having a frequency f _{1 applied} to an input terminal thereof into a synthetic signal having a frequency f ₀ P ₀ and a frequency f ₀ P _0. f ₁ / P ₁ (that is, f ₂ ) and a synthesized signal having a frequency f ₀ P ₀ is output from the first output terminal to the first input terminal of the frequency synthesis circuit 50 . And outputs a synthesized signal having a frequency of f ₁ / P ₁ (that is, f ₂ ) from the second output terminal to the input terminal of the modulation signal generation circuit 30 and the first input terminal of the frequency shift circuit 40 . ing.

That is, the comparator 21 compares the analog input signal having the frequency f ₁ provided from the appropriate signal source to the input terminal with the appropriate reference value, so that the frequency f _{1 is obtained.}
A 1-bit digital signal is created, and the phase detector 22
And a first input terminal of the frequency divider 28.

The phase detector 22 has a comparator 21 connected to a first input terminal.
Meanwhile from the frequency divider 27 at the output terminal of the later-described digital signal frequency applied from the output end is f ₁ of the second frequency provided to the input terminal is compared with the divided signal is f ₁ , And generates and outputs a voltage signal corresponding to the phase difference, and supplies the voltage signal to the input terminal of the loop filter 23.

The loop filter 23 integrates the voltage signal supplied from the phase detector 22 to the input terminal and holds the integrated signal, and outputs the integrated value held therein from the output terminal to output a voltage control crystal. It is provided to the input terminal of the oscillator 24. Specifically, (i) when the voltage signal given to the input terminal from the phase detector 22 is 0, the loop filter 23 holds the internally held integral value as it is, and Is output from the output terminal as it is to the input terminal of the voltage controlled crystal oscillator 24. (ii) When the voltage signal supplied from the phase detector 22 to the input terminal is not 0, the integrated value of the voltage signal is It is added to the internally held integral value, held internally as a new integrated value, and the new integrated value is output from the output terminal and applied to the input terminal of the voltage controlled crystal oscillator 24.

The voltage controlled crystal oscillator 24 is a loop filter
It oscillates according to the signal given to the input terminal from 23,
An oscillation signal having a frequency of f ₁ P ₀ is generated and output, and is provided to an input terminal of the distributor 25.

The distributor 25 sends an oscillation signal having a frequency of f ₁ P ₀ supplied from the voltage controlled crystal oscillator 24 to the input terminal from the first output terminal to the first input terminal of the frequency synthesizing circuit 50 . It outputs an oscillation signal having a frequency of f ₁ P ₀ from the second output terminal to the input terminal of the amplifier 26. The amplifier 26 appropriately amplifies and outputs an oscillation signal having a frequency of f ₁ P ₀ , and supplies the amplified signal to an input terminal of a frequency divider 27.

The frequency divider 27 divides the frequency of the oscillation signal having the frequency f ₁ P ₀ into 1 / P ₀ to generate a digital signal having the frequency f ₁ (that is, a frequency-divided signal). 22 to the second input.

The frequency divider 28 divides the frequency of the digital signal having the frequency f ₁ supplied from the output terminal of the comparator 21 by 1 / P ₁ and divides the frequency by f ₁ / P ₁ (that is, f ₂ ). A certain digital signal is generated and supplied to the input terminal of the modulation signal generation circuit 30 and the first input terminal of the frequency shift circuit 40 .

Modulation signal generation circuit 30

The modulation signal generation circuit 30 includes the frequency synthesis circuit 20
A second frequency provided from the output end f ₁ / P ₁ (i.e. f ₂₎ frequency from the digital signal is f ₂ K _3/2
Generates and outputs a modulated signal that is ^M , a frequency shift circuit
Forty second inputs are provided.

Frequency shift circuit 40

The frequency shift circuit 40 operates as described in detail below, and synthesizes the frequency given from the second output terminal of the frequency synthesizer 20 as f ₁ / P ₁ (ie, f ₂ ). The frequency given by the signal and the modulation signal generation circuit 30 is f
And a is a modulated signal ₂ K _3/2 ^M, the center frequency f
₀ (= f ₂ K _0/2 ^M ) and the maximum frequency deviation is f ₂ K _H /
2 ^M frequency modulated analog signal Y = asin 2
π (f ₀ + f _H w (t)) t is created and output to the frequency synthesis circuit 50 .

[0053] That is, D-type Furipufuroppu 41, a second frequency provided from the output to the clock input of the frequency synthesizer circuit 20 has a clock signal to a digital signal is f _2, from the modulation signal generation circuit 30 frequency given to the data input terminal is supplied to the first input terminal of full adder 42 holds only period corresponding modulated signal is f ₂ K _3/2 ^M in one clock period of the clock signal .

The full adder 42 has a frequency f given from the output terminal of the D-type flip-flop 41 to the first input terminal.
₂ K _3/2 a is depending on the value of a particular digit of a digital signal ^M, the frequency f ₀ given to the second input terminal (= f ₂ K ₀ /
Data K for specifying the 2 ^M) ₀ and the maximum frequency deviation f _H (= f ₂
And a data K _H for designating the K _H / 2 ^M), when determining the sign of the data K _H (value of a specific digit is 0 + and when determining vital 1 - and decisions) was then, added to each other, Data K ₀ ±
It is output as K _H and given to the (N + 1) -bit D-type flip-flop 43.

The D-type flip-flop 43 operates as a clock signal using a digital signal whose frequency is f ₂ given from the output terminal of the frequency synthesis circuit 20 to the clock input terminal. The data K ₀ ± K _H given to the data input terminal is output for one clock period while being held and supplied to the first input terminal of the M-bit full adder 44.

The full adder 44 adds the data K ₀ ± K _{H applied} to one input terminal from the D-type flip-flop 43 and the data _{An-1 applied} to the other input terminal to each other, and outputs the data. A _n-1 + K ₀ ± K _H (= A _n ) is generated and output, and is applied to the data input terminal of the M-bit D-type flip-flop 45.

The D-type flip-flop 45 operates using a digital signal whose frequency is f ₂ given from the frequency synthesizing circuit 20 at the clock input terminal as a clock signal, and outputs from the output terminal of the full adder 44 to the data input terminal. the data a _n given to holding only one clock period and outputs the data a _n is the result, giving the input end of the L-bit read-only memory 46. That is, the full adder 44 and the D-type flip-flop 45 function as an accumulator.

[0058] read-only memory 46, sine wave data Y _n = rou from the data A _n that is output from the D-type flip-flop 45
nd [(2 ^L −1) {1 + sin (2πA _n / 2 ^M )} / 2] is generated and output, and is given to an L-bit (for example, 8-bit) D-type flip-flop 47.

[0059] D-type flip-flop 47, by simultaneously output a sine wave data Y _n for L bits provided to the input end from the output end of the read only memory 46 holds one clock period, the digital-analog converter To the input end of the unit 48.

The digital-to-analog converter 48 outputs the sine wave data Y _n supplied from the D-type flip-flop 47 to the input terminal.
Is the analog signal Y = a sin2 whose frequency is f ₀ ± f _H
π (f ₀ + f _H w (t)) t, which is output to the amplifier 49. The analog signal Y has a modulation frequency of f ₂ K ₃
/ 2 ^M , a frequency-modulated composite signal having a center frequency of f ₀ and a maximum frequency shift of f _H.

[0061] amplifier 49, the center frequency given from the digital-to-analog converter 48 and outputs the amplified appropriately analog signal Y is _{f 0 (= f 2 K 0} /2 M), the frequency synthesizer circuit 50 It is provided to the second input terminal.

Frequency synthesis circuit 50

The frequency synthesizing circuit 50 operates as described in detail below, and the frequency shift circuit 40 and the synthesized signal whose frequency given from the first output terminal of the frequency synthesizing circuit 20 is f ₁ P _0. frequency given from an f ₀ ± f _H analog signal _{Y = asin2π (f 0 + f} H w (t)) and a t, the synthetic signal frequency is _{f 1 P 0 + f 0 ±} f H ( i.e. modulation frequency is f ₂ K _3/2 ^M, the center frequency is output to create a frequency modulated synthesized signal) is f ₁ P ₀ + f ₀ a and the maximum frequency shift f _H.

That is, the amplifier 51 is connected to the frequency synthesizer 20
First frequency supplied from the output terminal and outputs the amplified appropriately synthesized signal is f ₁ P _0, is applied to one input terminal of the mixer 52.

The mixer 52 is configured such that the combined signal of the frequency f ₁ P ₀ supplied from the output terminal of the amplifier 51 to one input terminal and the frequency supplied to the other input terminal are represented by f ₁ P ₀ + f ₀ ± f _H. By synthesizing the synthesized signal with
₀ ± f _H signal and frequency 2f ₁ P ₀ + f ₀ ± f _H
A mixed signal having the following signal is generated and output, and is supplied to the bandpass filter 53.

The bandpass filter 53 removes unnecessary frequency components from the mixed signal supplied from the output terminal of the mixer 52 and supplies the resultant signal to the comparator 53A. The comparator 53A converts the output of the bandpass filter 53 into a digital signal by comparing it with an appropriate reference value and supplies the digital signal to one input terminal of the phase detector 56.

The band-pass filter 54 removes high-frequency noise and low-frequency noise from a digital signal having a center frequency of f ₂ K _0/2 ^M supplied to the input terminal from the frequency shift circuit 40 and supplies the same to the comparator 55. I have.

The comparator 55 compares the output signal of the bandpass filter 55 with an appropriate reference value so that the frequency becomes f ₀ ± f.
Create and output a digital signal that is _H
To the other input terminal.

The phase detector 56 has a frequency f ₀ given to one input terminal from the bandpass filter 53 via the comparator 53A.
Comparator from digital signal with ± f _H and bandpass filter 54
The frequency applied to the other input terminal via 55 is f ₀ ± f
The phase difference is obtained by comparing the digital signal with _H , and a voltage signal corresponding to the phase difference is generated and output, and is supplied to the input terminal of the loop filter 57.

The loop filter 57 integrates the voltage signal given from the phase detector 56 and holds it inside, and outputs the integrated value held inside and outputs it to the voltage-controlled crystal oscillator 58. . Specifically, the loop filter 57
(i) When the voltage signal output from the phase detector 56 is 0, the integrated value held inside is held as it is, and the integrated value is output as it is and given to the voltage controlled crystal oscillator 58. And (ii) when the voltage signal output from the phase detector 56 is not 0, add the integrated value of the voltage signal to the internally held integrated value, and hold the internally as a new integrated value;
The new integrated value is output from the output terminal and applied to the input terminal of the voltage controlled crystal oscillator 58.

The voltage controlled crystal oscillator 58 is a loop filter
The oscillator oscillates at a frequency corresponding to the signal given to the input terminal from 57, outputs an oscillation signal having a frequency of f ₁ P ₀ + f ₀ ± f _H , and gives the signal to the input terminal of the distributor 59.

The distributor 59 generates an oscillating signal having a frequency given by the voltage controlled crystal oscillator 58 of f ₁ P ₀ + f ₀ ± f _H.
(Ie, a transmission signal having a center frequency of f ₁ P ₀ + f ₀ and a maximum frequency shift of f _H ) is output from the first output terminal as a composite signal, and the amplifier 59A is output from the second output terminal. To the input end.

The amplifier 59A has a frequency of f ₁ P ₀ + f ₀ ±
amplifies appropriate oscillation signal is f _H output, the mixer 52
To the other input terminal.

[0074]

As is apparent from the above description, the frequency synthesizer according to the present invention has the following features. First synthesized signal and a frequency frequency receiving input signals is f ₁ is the circumferential <br/> wavenumber is f ₁ P ₀ is f ₁ /
P ₁ (= f ₂₎ first frequency synthesis circuit which second it <br/> respectively output force resultant signal and to generate the a, frequency receiving said second combined signal f ₂ K _3/2 and the modulation signal generation circuit you output a modulated signal is generated which is ^M, the second composite signal with the modulated signal and the center frequency received a f ₂ K ₀ /
2 ^M a and a maximum frequency shift is a frequency shift circuit you generates and outputs a frequency-modulated shift signal is f ₂ K _H / ₂ ^M, the second composite signal and the clock signal
Hold and output the modulated signal for one clock period.
The first flip-flop having the frequency f ₀ (= f ₂ K ₀ /
^{_{2 M; 0 ≦ K 0 ≦}} 2 M -1) data K ₀ to specify the most
Large frequency shift f _H (= f ₂ K _H / 2 ^M ; 0 ≦ K _H ≦ 2 ^M
-1) Receiving data K _H specifying the above and the modulation signal
Data K ₀ + K _H or data K ₀ + K _H according to the value of the modulation signal
A first full adder for outputting K ₀ -K _H , the first full adder
Before data K ₀ + K _H or data K ₀ −K _H
The second synthesized signal is a clock signal for one clock period
A second flip-flop that holds and outputs
Data obtained using the second synthesized signal as a clock signal.
Third flip-flop for holding and outputting for one clock period
Rop, data _An-1 from the third flip-flop.
And the data K ₀ + K _H from the second flip-flop.
Alternatively , receiving data K ₀ −K _H and receiving data A _n (= data
_{A n-1 + K 0 +} K H , or = data A _n-1 + K ₀ -
K _H ) to the third flip-flop.
Full adder, data A from the third flip-flop
memory for outputting the sine wave data Y _n receives the _n-1, Oyo
Receiving the sine wave data from the memory and the analog signal Y
Shifter with digital-to-analog converter that outputs
Receiving a preparative circuit, said first composite signal and the said shift signal
The only and the center frequency is frequency-modulated _{f 1 P 0 + f 2 K} 0/2 M a and a maximum frequency shift is f ₂ K _H / ₂ ^M
Since 3 of the synthesis signal is generated and a second frequency synthesizer circuit to output, (i) the frequency is the center frequency from the input signal of the f ₁ and at _{f 1 P 0 + f 2 K} 0/2 M Frequency-modulated high accuracy with maximum frequency deviation of f ₂ K _H / 2 ^M
Has the effect of generating a minimal output signal, thus (ii) rational K ₃ and integer K _0, K _H a desired only to specify the center is the frequency a and the desired maximum frequency shift frequency modulation signal of the desired There is an effect that can be generated using the modulation frequency.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a frequency synthesizer according to the present invention.

FIG. 2 is a block diagram showing in detail a part of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram showing a part of the embodiment shown in FIG. 1 in detail.

FIG. 4 is a block diagram showing a part of the embodiment shown in FIG. 1 in detail.

[Description of Signs] 10 Frequency synthesis device 20 Frequency synthesizer 21 ... Comparator 22 ... Phase detector 23 ...・ ・ ・ ・ ・ ・ ・ Loop filter 24 ・ ・ ・ ・ ・ ・ ・ ・ ・ Voltage controlled crystal oscillator 25 ・ ・ ・ ・ ・ ・ ・ ・ ・・ ・ ・ ・ ・ ・ ・ ・ ・ Distributor 26 ・ ・ ・ ・ ・ ・ ・ ・ ・ Amplifier 27 ・ ・ ・ ・ ・ ・ ・ ・ ・Divider 28 ・ ・ ・ ・ ・ ・ ・ ・ ・ Divider 30・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Modulation signal generation circuit 40 Frequency shift circuit 41 D-type flip Flip-flop 42 Full adder 43 D-type flip-flop 44 ... Full adder 45 ... D-type flip-flop 46 ... ... Read-only memory 47 D-type flip-flop 48 ···· Digital-to-analog converter 49 ······ Amplifier 50 ··········· Frequency synthesis circuit 51 ... Amplifier 52 ... Mixer 53 ...・ ・ ・ ・ ・ ・ ・ ・ Band filter 53A ・ ・ ・ ・ ・ ・ ・ ・ Comparison 54 Band filter 55 Comparator 56 ... Phase detector 57 ... Loop filter 58 ...・ ・ ・ ・ Voltage-controlled crystal oscillator 59 ・ ・ ・ ・ ・ ・ ・ ・ ・ Distributor 59A ・ ・ ・ ・ ・ ・ ・ ・ Amplifier

Claims (1)

(57) [Claims] (1) Frequency receiving input signals is f ₁ is first synthesized signal and the frequency <br/> frequency is f ₁ P ₀ f ₁
/ P ₁ and the first frequency synthesizer circuit (= f ₂₎ a is to generate a second combined signal to force out Re its <br/>-resolution (20), receiving said second combined signal frequency Te is you generates and outputs a modulated signal is f ₂ K _3/2 ^M modulation signal generating circuit (3
0), the second composite signal with the modulated signal and the center frequency received a is f ₂ K _0/2 ^M a and the maximum frequency deviation f ₂ K _H /
A 2 ^M a is frequency modulated shifted signals generated you output <br/> frequency shift circuit (40), said second coupling
The modulated signal is a clock signal and the modulated signal is one clock.
The first flip-flop (4
1), the frequency _{f 0 (= f 2 K 0} /2 M; 0 ≦ K 0 ≦ 2 M
Data K ₀ that specify -1) and the maximum frequency deviation f _H (=
f ₂ K _H / 2 ^M ; data specifying 0 ≦ K _H ≦ 2 ^M -1)
Depending on the value of the modulation signal receiving said modulated signal and data K _H
To output data K ₀ + K _H or data K ₀ −K _H
A first full adder (42), data from the first full adder;
Data K ₀ + K _H or data K ₀ −K _H in the second synthesis
Hold the signal as a clock signal for one clock period
A second flip-flop (43) to output,
Data is stored in one clock using the second synthesized signal as a clock signal.
Third flip-flop that holds and outputs for the lock period
(45), the data A from the third flip-flop
_n-1 and data K ₀ + from the second flip-flop.
K _H or data K ₀ receives -K _H data A _n (= de
Data A _n-1 + K ₀ + K _H , or = data A _n-1 + K
₀ −K _H ) to the third flip-flop.
2 full adder (44), the third flip-flop
Outputs a sine wave data Y _n receives data A _n-1 of al
A memory (46) and sine wave data from the memory
Digital-to-analog conversion that receives and outputs an analog signal Y
Vessel (48) and the frequency shift circuit (40) having a said first composite signal and the shift signal and the center frequency received a _{f 1 P 0 + f 2 K} 0/2 M a and a maximum frequency shift f ₂ K _H / 2 third second frequency synthesizer circuit (50) for combining signals generated output that is frequency modulated with ^M frequency synthesizer having a.