JPH088742A - Pll circuit - Google Patents

Abstract

PURPOSE:To attain a small dividing ratio by dividing a decimal point in order to set the finer frequency and also to secure a high response of a PLL circuit for a frequency synthesizer. CONSTITUTION:A direct digital synthesizer 50A uses the intermediate frequency fCO=fout-fLO which is lower than the oscillation frequency fout of a voltage control oscillator 40 by a degree equal to the local oscillation frequency fLO. Then the synthesizer 50A applies the cumulative addition to a dividing ratio 1/N=phiN/2<n> in each clock cycle 1/fCK to output a discrete digital signal S7 of frequency fDDS=(phiN/2<n>).fCK.A multiplying DA converter 20A performs the multiplication of the signal S7 and an analog reference signal S1 of frequency fref to output an analog error signal S2 which is proportional the phase difference thetabetween both signals S7 and S1. Thus the oscillation frequency fout=(2<n>/phiN).fref+fLO is obtained in a phase locked state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention uses a PLL circuit, in particular, a multiplying DA converter as a phase detector and a DDS (Direct Digital Synthesizer) as a frequency divider. The present invention relates to a PLL circuit used in a frequency synthesizer that can be set to.

[0002]

2. Description of the Related Art Generally, as is well known, a PLL circuit is an abbreviation for Phase Locked Loop circuit, which makes the phase of the oscillation frequency of a voltage controlled oscillator match the phase of a reference frequency. A circuit. Figure 5
Is a PLL used in a conventional frequency synthesizer.
It is an example of a circuit. In FIG. 5, reference numeral 1 is a reference frequency oscillator, 2 is a phase detector, 3 is a low pass filter, 4 is a voltage controlled oscillator, and 5 is a frequency divider. Voltage controlled oscillator 4
The output frequency f _{out of} is divided into 1 / N by the frequency divider 5,
Phase shift of the reference frequency f _r the phase and the reference frequency oscillator divided frequency is detected by the phase detector 2. As a result, an error signal proportional to the phase difference between the two frequencies is output from the phase detector 2, and unnecessary high frequency components are removed by the low pass filter 3 to serve as a control input for the voltage controlled oscillator 4. As a result, f _out is changed in the direction in which the error signal decreases, and in the state where the phase is locked, f _out = fr · N
Becomes That is, the conventional PLL circuit, by the N variable, the oscillation frequencies of the N times of a single frequency f _r f
_I was getting _out .

[0003]

However, in the conventional PLL circuit shown in FIG. 5, if the oscillation frequency is freely set and used, a high frequency division ratio is used, and the PLL loop is damaged due to the high frequency division ratio. The natural vibration frequency of is lowered. On the other hand, in order to realize a high-speed settling response, it is difficult to set a fine frequency because the frequency division ratio must be low. Furthermore, even if the frequency divider 5 of the conventional PLL circuit is composed of a palace swallow counter capable of relatively free frequency division setting with a frequency division ratio lower than that of a normal frequency divider, There was a limit to the setting of fine frequency.
That is, conventionally, it has not been possible to satisfy both the fine frequency setting and the high-speed response. It is an object of the present invention to realize a low frequency division ratio by enabling decimal point frequency division in a PLL circuit, fine frequency setting, and high speed response.

[0004]

The present invention is based on the above-mentioned conventional P
In view of the problem of the limit of fine frequency setting due to the integer division included in the LL circuit, the phase-locked loop includes the direct digital synthesizer 50A and the multiplying DA converter 20A, thereby enabling the division of the decimal point. Therefore, the above problems are to be solved.

[0005]

Therefore, according to the configuration of the present invention, as shown in FIG. 1, the frequency f _CO = f _out -f _LO obtained by down converting the oscillation frequency f _out of the voltage controlled oscillator 40 is used as the clock frequency f.
_The direct digital synthesizer 50A is operated as _CK , and the division ratio is 1 / N = every clock cycle 1 / f _CK.
Φ _N / 2 ⁿ frequency f _DDS outputted by cumulatively adding the = ([Phi
The digital sawtooth wave S ₇ ( _N / ²ⁿ ) · f _CK (FIG. 4B) is input to the multiplying DA converter 20A and is proportional to the phase difference θ of the reference frequency f _ref with respect to the analog reference signal S ₁ . The analog error signal S ₂ is sent to the voltage controlled oscillator 4
By setting the control input to 0, the oscillation frequency f _out = (2 ⁿ / Φ _N ) · f _ref + f _LO can be obtained in the phase locked state, so the frequency division ratio 1 / N = Φ _N / 2 ⁿ
By properly setting, the decimal point frequency division can be performed.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings by way of embodiments. FIG. 1 is an overall view showing an embodiment of the present invention, and FIG. 2 is a detailed view showing an embodiment of the present invention. Reference numeral 10
Is a reference frequency oscillator, 20 is a phase detector, 30 is a low pass filter, 40 is a voltage controlled oscillator, 50 is a frequency divider, and 6
0 is a down converter and 70 is an upper converter.

A. Configuration As shown in FIG. 1, the PLL circuit according to the present invention includes a reference frequency oscillator 10, a phase detector 20, a low pass filter 30, a voltage controlled oscillator 40, a down converter 60, and a frequency divider. A phase locked loop is constituted by 50 and. Further, as an apparatus for generating the local oscillation frequency f _LO of this phase locked loop, the upper converter 7
0 is provided.

The reference frequency oscillator 10 is an oscillator that oscillates an analog signal S ₁ having a constant reference frequency f _ref , and is composed of, for example, a crystal oscillator 10A (FIG. 2).

The phase detector 20 receives the reference signal S ₁ and
A comparison signal S _7, which will be described later, is input, a phase shift between the two signals is detected, and an error signal S ₂ proportional to the phase difference is output.
In the present invention, this phase detector 20 is a multiplier D
It is composed of an A converter 20A. This multiplying DA converter 20A multiplies an analog reference signal S ₁ by a discrete digital signal S ₇ which is a comparison signal, and an analog error signal S ₂ proportional to the phase difference θ between the two signals S ₁ and S _7. The reference voltage V _ref obtained by dividing the power supply voltage V _CC by the resistors R ₁ and R ₂ is applied to the input side of the DA converter.

The low pass filter 30 includes a loop filter 30A for controlling a PLL loop and an error signal S
Reference filter 3 that removes harmonic components from ₂
0B and 0B, as shown in FIG.

The voltage controlled oscillator 40 is a variable frequency oscillator that changes the oscillation frequency f _out using the error signal S ₃ that has passed through the low pass filter 30 as a control input. The upper converter 70 has a unique multiplication ratio N _T, by increasing the reference frequency f _ref to an integral multiple N _T, a device for obtaining the local oscillation frequency _{f LO = f ref × N T} , FIG. As shown in FIG. 2, it is composed of a frequency multiplier 70A and a bandpass filter 70B. Down above
The converter 60 has an oscillation frequency f of the voltage controlled oscillator 40.
_out and the local oscillation frequency f of the upper converter 70
_{From LO} , the intermediate frequency f _CO = f lower than the oscillation frequency f _out
As shown in FIG. 2, the mixer 60A, the bandpass filter 60B, and the comparator 60 are devices for obtaining _out- f _LO .
It is composed of C and.

The frequency divider 50 has a variable frequency division ratio 1 / N = Φ.
_The frequency f _divided by the intermediate frequency f _CO = f _out −f _LO generated by the down converter 60, which has _N / 2 ^n.
_This is a device for obtaining _DDS = (Φ _N / 2 ⁿ ) · f _CK . In the present invention, the frequency divider 50 is composed of the direct digital synthesizer 50A. As shown in FIG. 2, the direct digital synthesizer 50A is composed of an arithmetic unit 50A1 and a D-type register 50A2, and has a clock signal S _{6 having the} intermediate frequency f _CO = f _out −f _LO as a clock frequency f _CK. , The phase increment value Φ _N and the maximum value 2 ^{n of the} computing unit 50A1 as will be described later.
If, frequency f _DDS = (Φ determined by the clock frequency f _CK
This is a device for outputting a discrete digital signal S ₇ of _N / 2 ⁿ ) · f _CK .

B. Operation An operation of the PLL circuit having the above configuration will be described below with reference to FIGS. 2, 3, and 4. FIG. 2 is a detailed view showing the embodiment of the present invention as described above. In FIG. 3, the frequency f is plotted on the horizontal axis, the frequency band of the signal output from each device described above (FIG. 3A), and the characteristics of the filter through which the output signal passes (see FIG. B)) is drawn. FIG. 4 is a waveform diagram of each part of the direct digital synthesizer 50A constituting the frequency divider 50 and a waveform diagram of the reference signal S ₁ .

As shown in FIG. 3, the reference frequency f _{ref is set} to 1
The operation in the case where the oscillation frequency f _out of the voltage controlled oscillator 40 is finely set between 940 and 960 MHz based on 1 MHz will be described. First, as shown in FIG. 2, from the reference oscillator 10, the reference frequency f _ref =
The analog reference signal S _{1 of 1} MHz is input to the multiplying DA converter 20A via the capacitor C ₁ and the frequency multiplier 7 of the upper converter 70 is also supplied.
Input to 0A. In the frequency multiplier 70A, the local oscillation frequency f _LO = f due to the inherent multiplication ratio N _T = 930.
_ref × N _T = 1 MHz × 930 = 930 MHz is obtained, an analog signal S ₅ oscillating at this local oscillation frequency f _LO = 930 MHz is output, and the band pass filter 70B is output.
To enter.

In the bandpass filter 70B, as shown in FIG. 3, by increasing the purity of the spectrum of the local oscillation frequency f _LO , only the analog signal S ₅ having a frequency of 930 MHz passes, and the down converter of the next stage. 60 mixer 60A.

In the mixer 60A, the local oscillation frequency f _LO =
930MHz analog signal S ₅ and voltage controlled oscillator 4
Analog signal S ₄ of oscillation frequency f _out output from 0
Is multiplied by f _CO = f _out −f _LO = f _out −93
An analog signal S ₈ oscillating at a frequency of 0 MHz is output. The oscillation frequency f _out of the voltage controlled oscillator 40 is 940
Since it has a usable frequency range of MHz to 960 MHz, the analog signal S ₈ output from the mixer 60A is
As a result, a beat down frequency of 10 MHz to 30 MHz can be obtained, and as shown in FIG.
By passing B, unnecessary beat down frequencies other than 10 MHz to 30 MHz are removed. Furthermore,
The analog signal S that has passed through the band pass filter 60B
₈ is input to a comparator 60C that has a hysteresis characteristic and secures stability against noise, and by being waveform-shaped, a rectangular-wave digital signal S ₆ is input to the direct digital synthesizer 50A as a clock signal.

Direct digital synthesizer 50
As shown in FIG. 4, A operates with the frequency f _CO = f _out -f _LO = f _out -930 MHz of the rectangular wave clock signal S ₆ as the clock frequency f _CK . That is, by inputting the phase increment value Φ _N , the variable frequency division ratio 1 / N = Φ _N / 2 set by the setting unit 50A11 is set every clock cycle t = 1 / f _CK shown in FIG. ^The arithmetic unit 50A1 cumulatively adds ⁿ to the maximum value 2 ⁿ (FIG. 4 (B)). As a result, a digital sawtooth discrete digital signal S ₇ as shown in the figure is output.

In FIG. 4B, the frequency division ratio 1 / N cumulatively added up to the maximum value 2 ⁿ is expressed by the following equation. In _{1 / N = Φ N / 2} n ··· this formula, n the number of bits of the arithmetic unit 50A1,
Φ _N represents the phase increment value of the calculator 50A1. The phase increment value Φ _N is a coefficient when 2 ⁿ is viewed in full scale, and the binary value is represented by a decimal value. In the case of the present embodiment, the 2 ⁿ (100%) value is normalized to the value of the clock frequency f _CK . Therefore, the division ratio 1 / N
Becomes Φ _N / 2 ⁿ as shown in the above equation. Also,
As described above, the clock cycle t is t = 1 / f _CK = 1 / f _CO ... Therefore, the direct digital synthesizer 50A
The period T of the discrete digital signal S ₇ output from T = Nt = (2 ⁿ / Φ _N )  (1 / f _CK ) ... _Therefore , the output frequency f _DDS is f _DDS = 1 / T = (Φ _N / 2 ⁿ ) · f _CK ...

This output frequency f _DDS = (Φ _N / 2 ⁿ ).
The discrete digital signal S ₇ having f _CK is input to the multiplying DA converter 20A, is multiplied by the analog reference signal S ₁ (FIG. 4C) having the reference frequency f _ref , and the phase difference θ between the two signals is inputted. An analog error signal S ₂ proportional to ((C) of FIG. 4) is output. In the above case, the sine wave is used as the waveform of the analog reference signal S ₁ (FIG. 4 (C)), but any of a rectangular wave, a triangular wave and a sawtooth wave may be used. In addition, the discrete digital signal S ₇ (see FIG.
The waveform of (B) represents the state of integer division, and in the case of decimal division, the phase of the waveform changes for each cycle. The analog error signal S ₂ is input to the loop filter 30A of the low-pass filter 30 to remove harmonic components and leave only DC components to ensure loop stability (see FIG. 3).
(B)), and further input to the reference filter 30B to remove the phase detection noise generated in the previous multiplying DA converter 20A (FIG. 3).
(B)).

The analog error signal S ₃ from which the harmonic components have been removed in this way becomes the control input of the voltage controlled oscillator 40. As a result, the voltage-controlled oscillator 40 causes the oscillation frequency f _out to decrease the analog error signal S _3.
Variable, direct digital synthesizer 50
The output frequency f _{DDS of A} = (Φ _N / 2 ⁿ ) f _CK is matched with the reference frequency f _ref to perform phase lock. That is, from the above equation, f _CK = f _CO = f _out
Because it is -f _LO · · ·, this Toto, the oscillation frequency f _out becomes ^{_{f out = (2 n / Φ}} N) · f DDS + f LO ···. In the state in which f _{DDS in the} equation matches the reference frequency f _ref and is phase locked, f _DDS = f _ref , and thus f _out = (2 ⁿ / Φ _N ) · f _ref + f _LO ...

Therefore, f _ref = 1MH in this embodiment.
z (FIG. 3A) and f _LO = 930 MHz (FIG. 3A)
Substituting into the above formula, f _out = (2 ⁿ / Φ _N ) +930 ... In the formula, the oscillation frequency f _out is 940 MHz to 96
To make fine settings in the range of 0 MHz (Fig. 3 (A)),
Frequency division ratio setting unit 50A1 of arithmetic unit 50A1 constituting the direct digital synthesizer 50A (FIGS. 1 and 2)
1, the phase increment value Φ _N is digitally input so that the variable frequency division ratio 1 / N = Φ _N / 2 ⁿ becomes (1/10) to
The decimal point may be set within the range of (1/30).

[0022]

As described above, according to the present invention, the PLL
Since the circuit is composed of the direct digital synthesizer 50A and the multiplying DA converter 20A, it is possible to divide the decimal point, which brings about a technical effect that the frequency can be finely set.
Further, since a PLL circuit having a low frequency division ratio 1 / N = Φ _N / 2 ⁿ can be realized, the phase noise can be reduced, the settling time of the phase lock loop can be shortened, the frequency characteristic can be stabilized, and the reference frequency can be reduced. There is an effect that an analog signal waveform can be used for supplying f _ref .

[0023]

[Brief description of drawings]

FIG. 1 is an overall view showing an embodiment of the present invention.

FIG. 2 is a detailed view of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is a waveform chart of each part of the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 10 Reference Frequency Oscillator 20 Phase Detector 30 Low Pass Filter 40 Voltage Controlled Oscillator 50 Frequency Divider 60 Down Converter 70 Upper Converter 20A Multiplying DA Converter 50A Direct Digital Synthesizer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03L 7/18 B

Claims (5)

[Claims] 1. A PLL circuit comprising a reference frequency oscillator, a phase detector, a low-pass filter, a voltage controlled oscillator, and a frequency divider, wherein a local frequency is _derived from an oscillation frequency f _out oscillated from the voltage controlled oscillator 40. Intermediate frequency f _CO = f _out lower by the oscillation frequency f _LO
-F _LO is the clock frequency f _CK and the clock cycle is 1 / f
Direct digital synthesizer that outputs a discrete digital signal S ₇ of frequency f _DDS = (Φ _N / 2 ⁿ ) · f _CK by cumulatively adding the division ratio 1 / N = Φ _N / 2 ⁿ for each _CK A frequency divider 50 composed of 50 A is provided, and a discrete digital signal S ₇ having the frequency f _DDS = (Φ _N / 2 ⁿ ) · f _CK and an analog reference signal S having the reference frequency f _ref are provided.
By multiplying ₁ and includes both signals S _7, S ₁ of the phase detector 20 constructed in accordance with the multiplying DA converter 20A which outputs an error signal S ₂ analog which is proportional to the phase difference theta, phase lock Frequency f _out = (2 ⁿ / Φ
A PLL circuit characterized by obtaining _N ) .f _ref + f _LO . 2. The multiplying DA converter 2
0A and the voltage controlled oscillator 40 between the low pass filter 30
2. The PLL circuit according to claim 1, wherein the low-pass filter 30 includes a loop filter 30A and a reference filter 30B. 3. A down converter 60 is inserted between the direct digital synthesizer 50A and the voltage controlled oscillator 40, and an upper converter 70 is inserted between the down converter 60 and the reference frequency oscillator 10. The PLL circuit according to claim 1, wherein 4. The down converter 60 comprises a mixer 60A, a bandpass filter 60B and a comparator 60C.
The PLL circuit according to claim 3, which is configured by: 5. The PLL circuit according to claim 3, wherein the upper converter 70 includes a frequency multiplier 70A and a bandpass filter 70B.