JPH1041816A - Signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate frequency setting, especially the output of a frequency between respective DDS outputs at an exact integer ratio by setting the frequency having no fraction, through phase addition data setting of an integral value. SOLUTION: At a PLL circuit 60, a phase-locked loop is controlled by a phase comparator 20, so that the phase of an output signal from an external reference clock generator 10 is equal to the phase of an output signal from a PLL-DDS 30. As a result, in the locked state of the PLL 60, the frequency of an output signal fs from the reference clock generator 10 is equal with a frequency fb of the output from the PLL=DDS 30. Thus, even when the clock frequency of the reference clock generator 10 is not a power of 2, the output frequency of the PLL=DSS 30 can be easily set to the frequency having no fraction and further, even when plural DDS are connected, the DDS output of the accurate integer ratio can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator having a DDS output, and more particularly to a signal generator capable of easily setting a frequency and outputting the frequencies of a plurality of DDS outputs accurately at an integer ratio.

[0002]

2. Description of the Related Art FIGS.
And FIG. As shown in FIG. 2, the configuration of a conventional signal generator having a DDS output includes a reference clock generator 10, a DDS71 of a direct digital synthesizer, and DDS72 to DDS7m.

A reference clock generator 10 generates a signal having a predetermined frequency as a reference. For example, 1MHz, 5M
Hz, 10 MHz, 50 MHz, 100 MHz, etc. In general, powers of two are not used.

Next, an example of a DDS which is a direct digital synthesizer will be briefly described with reference to FIG. 3 showing a block diagram of an internal principle and FIG. 4 showing an output signal waveform. A DDS (Direct Digital Synthesizer) is a synthesizer that digitally outputs a digital sine wave signal of an arbitrary frequency.

[0005] For example, as shown in FIG.
A bit length phase addition setting register 33 and an adder 34
An address counter 35 for generating an address for one cycle of a digital sine waveform, a ROM table memory 36 for outputting 12-bit data for generating a digital sine waveform, a DA converter 37, and a low-pass filter. LPF38.

When the phase addition data is set in the phase addition setting register 33, the adder 34 converts the reference clock input into a clock frequency corresponding to the phase addition data and outputs the converted clock.

The clock frequency of the DDS output can be generated at a high resolution pitch as shown in the following equation (1), and the continuity of the phase of the output waveform is maintained even when the setting is switched. Will be kept. This clock frequency is given to the address counter 35 to be counted. ^{_{f DDS = (DATA / 2 n}} ) · f c ···· (1) where, f _DDS: the DDS output clock frequency n: Size (bits) f _c of the phase addition setting register: the reference clock frequency DATA: Phase addition data

Then, by counting the clock frequency, an address for the ROM table memory 36 is generated and output.

When the address is generated and the contents of the ROM table memory 36, that is, 12-bit sine wave code data are DA-converted, a digital step-like sine waveform shown in FIG. 4A is obtained. The step-like sine waveform is smoothed by the LPF 38 to become a smooth sine waveform shown in FIG.

From the above equation (1), the following equation (2) is obtained. DATA = (f _DDS / f _c ) 2 ⁿ ... (2) For example, when the above-mentioned DDS is used for the DDS 71 and the DDS 72, the frequency of the reference clock is 100 MHz, the phase addition setting register is 32 bits, and the DDS 71 DATA1 of the phase addition data in which the frequency of the output 1 of the DDS72 is 10 kHz and the frequency of the output 2 of the DDS72 is 20 kHz
And DATA2 are calculated from the above equation (2), and have the following values, each of which is not an integer. DATA1 = 429496.7 · · · DATA2 = 858933.4 · · ·

Therefore, the phase addition data that can actually be set is DATA1 = 429496 DATA2 = 858993. The frequency of output 1 and output 2 at that time is (1)
From the equation, f _DDS1 = 9.9999301 kHz f _DDS2 = 19.99999931 kHz

Thus, the frequency of output 1 and output 2 is 1
It is not 0 kHz or 20 kHz, and the frequency ratio is not an exact 1: 2 integer ratio. When measuring at this frequency, there is little effect on the measurement in a short time, but there is a problem that a phase shift occurs between the two output signals when the measurement is performed continuously for a long time. On the other hand, if only the frequency ratio is to be multiplied by an integer, the phase addition data may be set to be an integral multiple, but in that case, the desired frequency is not obtained.

[0013]

As described above, D
In the conventional signal generator using the DS, the generated signal frequency cannot be set to an accurate integer ratio, or the signal frequency becomes an odd frequency, so that there is a practical inconvenience that it is difficult to set a desired frequency. Accordingly, the present invention has been made in view of such a problem, and has as its object to provide a DDS output capable of setting a target frequency without a fraction such as 10 kHz or 20 kHz and generating a frequency having an accurate integer ratio. It is intended to provide a signal generator.

[0014]

According to a first aspect of the present invention, there is provided a reference clock generator, comprising: a first clock generator for receiving an output signal of the first clock generator; PL oscillating using DDS as phase feedback means
A signal generator comprising: an L circuit; and a second DDS for generating a desired signal in response to an output of the PLL circuit, wherein a fractional frequency can be generated by setting an integer value of phase addition data. The main point is.

That is, according to a second aspect of the present invention, there is provided a reference clock generating means, and an output signal of the reference clock generating means is supplied to one phase comparison input terminal of a PLL circuit. A PLL circuit that receives the output of the VCO by the DDS and supplies the output of the DDS to the other phase comparison input terminal of the PLL circuit to oscillate; and a plurality of PLL circuits that receive the output of the PLL circuit and generate a desired frequency. DDS
And a signal generator capable of outputting a frequency having a desired integer ratio.

That is, in order to achieve the above object, the invention according to claim 3 provides a reference clock generator 10 for generating a reference clock and a signal of the reference clock generator 10 being connected to one end of a phase comparison input. Receiving phase comparator 20, and a loop filter 4 for removing output noise of the phase comparator 20
0, a VCO 50 of an oscillator controlled by the output voltage of the loop filter 40, and a PLL-DD that feeds back the output of the VCO 50 to the other end of the phase comparison input of the phase comparator 20
S30 and a plurality of DDSs 71, 72 to 7 m for generating a desired frequency in response to the output of the VCO 50 of the oscillator.
The DDS 71, 72 to 7 m and the PLL
A signal generator characterized in that a frequency having a desired integer ratio can be generated by giving phase addition data to the DDS 30.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. As shown in FIG. 1, the configuration of the present invention comprises a reference clock generator 10 and a PLL circuit 60.
And DDSs 71 and 72 to 7 m.

In the PLL circuit 60 shown in FIG. 1, the phase locked loop is controlled by the phase comparator 20 so that the output signal of the external reference clock generator 10 and the output signal of the PLL-DDS 30 coincide with each other. You. In addition, PLL
The DDS in the circuit 60 is the DDS 71, 72 outside the PLL circuit.
Although the same one can be used for .about.7 m, the PLL-DDS 30 is used for easy distinction for convenience of explanation.

As a result, in the locked state of the PLL circuit 60, the frequency f of the output signal of the reference clock generator 10
_a becomes equal to the frequency f _b of the output signal of the PLL-DDS 30, and the equation (1) is obtained. f _a = f _b (1)

On the other hand, the output frequency of the DDS shown in FIG.
The following general formula (2) is used as in the description of the related art. f _DDS = (DATA / 2 ⁿ ) · f _C (2) where f _DDS : clock frequency of DDS output n: size (bit) of a phase addition setting register f _C : frequency of reference clock DATA: Phase addition data

Next, equation (2) is applied to the PLL circuit 6 shown in FIG.
When applied to 0, since f _C = f _VCO f _DDS = f _b DATA = DATAP, the following equation (3) is obtained. f _b = (DATAP / 2 ⁿ ) · f _VCO (3) Expression (4) is obtained from Expression (1) and Expression (3). f _VCO = (2 ⁿ / DATAP) · f _a ··· (4)

The expression (2) is shown in FIG.
When applied to, since f _C = f _VCO f _DDS = f _DDS1 DATA = DATA1, the following equation (5) is obtained. ^{_{f DDS1 = (DATA1 / 2 n}} ) · f VCO ···· (5) where, f _DDS1: DDS71 output clock frequency n: Size (bits) f _c of the phase addition setting register: frequency of the reference clock DATA1: Phase addition data

Accordingly, the following equation (6) is obtained from the equations (4) and (5). ^{_{f DDS1 = (DATA1 / 2 n}} ) · f VCO = (DATA1 / 2 n) · (2 n / DATAP) · f a = (DATA1 / DATAP) · f a ···· (6)

Similarly, the output 2 of the DDS 72 and the DDS 7
m and the output frequency of the output m are given by Equation (7),
Equation (8) is obtained. _{f DDS2 = (DATA2 / DATAP)} · f a ···· (7) f DDSm = (DATAm / DATAP) · f a ···· (8)

For example, when set under the following conditions, f _a = 1 MHz DATAP = 64 × 10 ⁶ DATA1 = 64 × 10 ⁴ DATA2 = 64 × 10 ⁴ × 2 DATAm = 64 × 10 ⁴ × 3 Equation (6) From (7) and (8), DDS71, 72, 7
The outputs 1, 2, and m of m are f _DDS1 = 10 kHz f _DDS2 = 20 kHz f _DDSm = 30 kHz, and have frequencies of an exact integer ratio of 1: 2: 3.

After all, as can be seen from the right side of the equations (6), (7) and (8), one PLL circuit having a DDS as a feedback system is provided.
By adding a stage, the power-of-two term is eliminated and eliminated, so that an output having a fractional frequency with respect to the frequency of the reference clock is obtained. Also, DATA1 and DATA2
, And the phase addition data with DATAm are set to have an integer ratio, and the output has a frequency of an accurate integer ratio.

In the present embodiment, an example is shown in which a plurality of DDSs are connected to the output of a PPL circuit having a DDS as a feedback system. However, the present invention can be implemented even when one DDS is connected.
There is an effect that an output having a fractional frequency with respect to the frequency of the reference clock can be obtained. .

[0028]

The present invention is embodied in the form described above and has the following effects. That is,
In the present invention, even if the clock frequency of the reference clock generator is not a power of two, the frequency of the DDS output can be easily set to a fractional frequency.
In addition, when a plurality of DDSs are connected, a DDS output frequency having an accurate integer ratio can be obtained, so that the effect as a signal generator for measurement requiring accuracy is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal generator according to the present invention.

FIG. 2 is a block diagram of a conventional signal generator.

FIG. 3 is a block diagram of a DDS.

FIG. 4 is a waveform of a DDS output.

[Explanation of symbols]

 Reference Signs List 10 reference clock generator 20 phase comparator 30 PLL-DDS 33 phase addition setting register 34 adder 35 address counter 36 ROM table / memory 37 DA converter 38 LPF 40 loop filter 50 VCO 60 PLL circuit 71, 72 to 7m DDS

Claims (3)

[Claims] A first D clock receiving means for receiving an output signal of the reference clock generating means;
A PLL circuit that oscillates using DS as a phase feedback means, and a second circuit that receives an output of the PLL circuit and generates a desired signal.
A signal generator comprising: a DDS according to claim 1, wherein a fractional frequency can be generated by setting an integer value of phase addition data. 2. A reference clock generation means, and an output signal of the reference clock generation means is supplied to one phase comparison input terminal of a PLL circuit, an output of a VCO is received by a DDS, and an output of the DDS is received by the PLL circuit. And a plurality of DDSs that generate the desired frequency by receiving the output of the PLL circuit and generate a desired integer ratio frequency. And a signal generator. 3. A reference clock generator (10) for generating a reference clock; a phase comparator (20) receiving a signal of the reference clock generator (10) at one end of a phase comparison input; A loop filter (40) for removing output noise of the loop filter (20); a VCO (50) of an oscillator controlled by an output voltage of the loop filter (40); and an output of the VCO (50) to the phase comparator (20). ) PLL-DDS (30) that feeds back to the other end of the phase comparison input
And a plurality of DDSs (71, 72 to 7m) which receive an output of the VCO (50) of the oscillator and generate a desired frequency, comprising: the DDSs (71, 72 to 7m) and the PLL.
A signal generator characterized in that a frequency having a desired integer ratio can be generated by giving phase addition data to the DDS (30).