JP3411817B2 - Frequency synthesizer - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a frequency synthesizer for generating an arbitrary frequency. In particular, the present invention relates to a frequency synthesizer that consumes less power, has good spurious characteristics, and can easily obtain high frequencies.

[0002]

2. Description of the Related Art FIG. 9 shows an example of the configuration of a conventional sine wave output type direct digital synthesizer (DDS) (reference: V. Reinhardt et al., "A short survey o.
f frequency synthesizer techniques ", in Proc. 40th
Annual Frequency Control symp., Pp.355-365, May 19
86).

In FIG. 9, reference numeral 31 is an accumulator, reference numeral 32 is a ROM, reference numeral 33 is a D / A converter, reference numeral 34 is a low pass filter (LPF), reference numeral 35 is a data input terminal to which frequency setting data K is input, Reference numeral 36 indicates a clock input terminal, and reference numeral 37 indicates an output terminal.

The accumulator 31 cumulatively adds the frequency setting data K for each input of the clock signal. If the number of bits of the accumulator 31 is n, the accumulator 3
When the output of 1 exceeds 2 ⁿ , the cumulative operation is continued with the excess amount as an initial value. The output of this accumulator 31 is used for addressing the ROM 32. ROM 32
The amplitude data of the sine wave is written in, and the sine wave data corresponding to the designated address is output. This sine wave data is converted into an analog signal by the D / A converter 33. This analog signal has a staircase waveform that changes with the clock frequency, and a smoother output is obtained by smoothing with the LPF 34.

When the clock frequency is f _CLK and the frequency setting data is K, the output frequency f _OUT is f _OUT = (K / 2 ⁿ ) f _CLK (1)

Since such a direct digital synthesizer does not use a feedback loop unlike a PLL (Phase Locked Loop), the frequency resolution can be increased and the output frequency can be switched at high speed.
However, since a large-scale ROM is required, the circuit scale is large, and there is a problem that the power consumption increases when the clock frequency is increased. Further, there is a problem that the clock frequency is limited to the ROM address time.

In order to solve these problems, as shown in FIG. 10, a direct digital type which does not use a ROM is used.
A synthesizer has been devised (Japanese Patent Laid-Open No. 9-83250).
Issue).

In FIG. 10, reference numeral 1 is an accumulator, reference numeral 2 is a D / A converter, reference numeral 3 is a delay circuit, and reference numeral 4 is shown.
Is a differential amplifier, reference numeral 55 is an integrator, reference numeral 6 is a comparator, reference numeral 7 is a toggle flip-flop (T-FF) used as a pulse generator, reference numeral 9 is a data input terminal to which the frequency setting data K is input, Reference numeral 10 is a clock input terminal, reference numeral 11 is a reference voltage input terminal to which the reference voltage Vr is input, and reference numeral 12 is an output terminal. The D / A converter 2, the delay circuit 3 and the differential amplifier 4 form a differential signal generation circuit 8.

The operation of the direct digital synthesizer shown in FIG. 10 will be described below with reference to the time chart shown in FIG. In addition, accumulator 1
The number of bits n is 3, and the frequency setting data K is 3. (a) is a clock, (b) is the output of the D / A converter 2 (solid line), (c) is the output of the delay circuit 3 (broken line), and (d) is the differential signal generation circuit 8 (differential amplifier 4). Output, (e) is integrator 5
5 output, (f) output of comparator 6, (g) TF
The output of F7 is shown.

Since n = 3 and K = 3, the operating cycle of the accumulator 1 is (2 ⁿ / (the greatest common divisor of K and 2 ⁿ )) = 8.
It becomes a clock cycle, and the output (b) of the D / A converter 2 and the output (c) of the delay circuit 3 obtained by delaying this by 8 clock cycles are also 8
It operates in the clock cycle. The differential signal generation circuit 8 has a D
A voltage (d) obtained by subtracting the output (c) of the delay circuit 3 from the output (b) of the A / A converter 2 is output. This is in 2 ⁿ clock cycles of time, a voltage proportional to K is - (K-2 ⁿ⁾ clock cycles periods appears voltage K clock period duration proportional to (K-2 ^n). Since n = 3 and K = 3 here, a voltage proportional to 3 appears for 5 clock cycle periods and a voltage proportional to −5 appears for 3 clock cycle periods within the time of 8 clock cycles.

The integrator 55 outputs the difference signal generating circuit 8.
Integrate (d) with time and output the voltage waveform shown in (e). Here, in the waveform (e), the period in which the voltage decreases with time (the straight line falling to the right) is always one clock cycle.
Therefore, straight lines in which the voltage increases with time (straight lines rising to the right) are arranged at equal intervals. Comparator 6
Outputs "1" when the output (e) of the integrator 55 exceeds the reference voltage Vr, the output (f) rises at regular intervals. Since the T-FF 7 uses the rising edge of the output (f) of the comparator 6 as a trigger, it outputs a rectangular wave (g) with a duty ratio of 50%.

Here, the fundamental wave of the output (g) of the T-FF 7 is given at a frequency of 1/2 of the equation (1). Also, T-
The FF7 can be replaced with a one-shot multivibrator, but the fundamental wave of the output in this case is given by the frequency of equation (1).

[0013]

Problems to be Solved by the Invention As shown in FIG.
Although a direct digital synthesizer that does not use an OM can operate at low power consumption and high frequency, a problem remains in how to provide the reference voltage Vr in order to realize this with hardware. That is, the integrator 55 is provided with information on the relative voltage change amount (the difference signal generation circuit 8
Output (d)) of the above, the output voltage level is affected by the initial voltage (unknown) that starts the integration. Furthermore, if the output voltage of the differential signal generating circuit 8 deviates from the ideal value, the output (e) of the integrator 55 will drift within the range of the power supply voltage.

Therefore, it is necessary to adjust the reference voltage Vr from the outside in accordance with the unpredictable output voltage level of the integrator 55. The reference voltage Vr is
It is necessary to adjust so that all linear waveforms of the output (e) of the integrator 55 intersect, but when the number of bits n of the accumulator 1 is large, the allowable range of Vr becomes narrow, so
The adjustment becomes difficult.

The present invention is a direct
In the digital synthesizer, the problem that the output voltage level of the integrator is not uniquely determined is solved, and the reference voltage Vr
It is an object of the present invention to provide a frequency synthesizer that does not require adjustment of.

[0016]

The frequency synthesizer of the present invention is characterized in that the output voltage of the integrator of the conventional direct digital synthesizer which does not use a ROM is periodically reset. Here, the reset cycle is the operation cycle of the accumulator or a cycle of an integral multiple thereof.

With such periodic resetting of the integrator, integration is always started from the same initial voltage (known), so that the voltage level of the integrator output is uniquely determined. Even if the output voltage of the differential signal generation circuit deviates from the ideal value, the drift of the integrator output due to this is corrected each time the integrator is reset. Never accumulated.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment: Claim 1,
2) FIG. 1 shows a first embodiment of the frequency synthesizer of the present invention.

In FIG. 1, the accumulator 1, D / A
The converter 2, the delay circuit 3, the differential amplifier 4, the comparator 6, the T-FF 7, the differential signal generation circuit 8, the data input terminal 9, the clock input terminal 10, the reference voltage input terminal 11, and the output terminal 12 are shown in FIG. This is similar to the conventional configuration shown. The feature of the present embodiment is that the integrator 5 with a reset circuit is used in place of the integrator 55, and the frequency dividing circuit 20 for dividing the frequency of the clock is used.
The output of A resets the integrator 5.

The operation of this embodiment will be described below with reference to the time chart shown in FIG. The number of bits n of the accumulator 1 is 3 and the frequency setting data K is 3
I am trying. (a) is a clock, (b) is the output of the D / A converter 2 (solid line), (c) is the output of the delay circuit 3 (dashed line), (d)
Is the output of the differential signal generating circuit 8 (differential amplifier 4), (e) is the output of the frequency dividing circuit 20A, (f) is the output of the integrator 5, (g) is the output of the comparator 6, and (h) is T. -Indicates the output of FF7.

Since n = 3 and K = 3, the operating cycle of the accumulator 1 is (2 ⁿ / (the greatest common divisor of K and 2 ⁿ )) = 8.
It becomes a clock cycle, and the output (b) of the D / A converter 2 and the output (c) of the delay circuit 3 obtained by delaying this by 8 clock cycles are also 8
It operates in the clock cycle. The differential signal generation circuit 8 has a D
A voltage (d) obtained by subtracting the output (c) of the delay circuit 3 from the output (b) of the A / A converter 2 is output. The integrator 5 time-integrates the output (d) of the difference signal generating circuit 8 and outputs the voltage waveform shown in (f). The output waveform (e) of the frequency dividing circuit 20A is, for example, when the frequency dividing ratio 8 is set. Divider circuit 20A
Outputs a pulse, the integrator 5 resets in synchronization with this and corrects the output (f) of the integrator 5 to the initial voltage V ₀ .

The frequency dividing ratio of the frequency dividing circuit 20A is determined in consideration of the operation cycle of the accumulator 1. That is, the operating cycle (condition of the dividing ratio) of the frequency dividing circuit 20A needs to be set to be the same as the operating cycle of the accumulator 1 or an integral multiple thereof. This is a condition that the reset operation does not disturb the periodicity of the output waveform of the integrator 5. Focusing on the voltage of the integrator 5 at the moment when each clock rises, the accumulator 1
After the operation cycle of, the same voltage is passed. For example, the output (f) of the integrator 5 after receiving the reset is the initial voltage V ₀
However, it does not return to the initial voltage V ₀ until the operation cycle (8 clock cycles) of the accumulator 1 elapses. Here, when the reset is performed in the operation cycle of the accumulator 1, the waveform shown by the solid line in FIG. 2 (f) is obtained, and when the reset is not performed, the waveform shown by the broken line in FIG. 2 (f) is obtained. In any case, the initial voltage V ₀ is restored. As described above, the reset does not disturb the periodicity of the output waveform of the integrator 5 only when the reset period coincides with an integral multiple of the operation period of the accumulator 1.

In FIG. 2, the output of the frequency dividing circuit 20A
The operation cycle (8 clock cycles) in (e) is set to match the operation cycle of the accumulator 1. When the frequency dividing ratio is set to infinity, that is, when the frequency dividing circuit 20A does not output a pulse, this frequency synthesizer becomes the same as a conventional direct digital synthesizer that does not use a ROM.
On the contrary, if the frequency division ratio is selected to be small, the reset will be performed more frequently, so that the drift of the integrator output due to the voltage error of the output of the differential signal generating circuit 8 can be suppressed to a smaller value, which is more ideal. Enables synthesizer operation. However, since the operation cycle of the accumulator 1 depends on the setting data K, in order to set the dividing ratio as small as possible, a mechanism for changing the dividing ratio of the dividing circuit 13 according to the setting data K is necessary. (This will be described in the second and subsequent embodiments).

Since the comparator 6 outputs "1" when the output (f) of the integrator 5 exceeds the reference voltage Vr, the output (g) rises at regular intervals. T
Since the -FF7 triggers the rising edge of the output (g) of the comparator 6, it outputs a rectangular wave (h) with a duty ratio of 50%. The fundamental frequency of the output (h) of the T-FF 7 is given by 1/2 the frequency of the equation (1). Further, the T-FF 7 can be replaced with a one-shot multivibrator, and the fundamental frequency of the output in this case is given by the frequency of the expression (1).

FIG. 3 shows a configuration example of the frequency dividing circuit 20A.
In FIG. 3, reference numerals 21-1 to 21-n are T-FFs, reference numeral 22 is a clock input terminal, and reference numeral 23 is an output terminal. The same number of bits as the number of bits n of the accumulator 1 is used for the T-FF, and constitutes an n-bit binary counter. Since the operation cycle of the accumulator 1 is 2 ⁿ / (the greatest common divisor of K and 2 ⁿ ), it does not become longer than 2 ⁿ clock cycles. Therefore, if an n-bit binary counter is applied as the frequency dividing circuit 20A, the operating period of the frequency dividing circuit 20A can be set to be the same as the operating period of the accumulator 1 or an integral multiple thereof. The condition of the frequency division ratio of the frequency circuit 20A is satisfied. By implementing the frequency dividing circuit 20A with a binary counter with a fixed frequency dividing ratio, it is possible to reduce the circuit scale of the frequency dividing circuit 20A and reduce power consumption.

(Second Embodiment: Claims 1 and 3) FIG.
2 shows a second embodiment of the frequency synthesizer of the present invention. The feature of the present embodiment is that the frequency dividing circuit 20B of the first embodiment shown in FIG. 1 is used instead of the frequency dividing circuit 20B in which the frequency dividing ratio is set according to the frequency setting data K. Other configurations are similar to those of the first embodiment.

FIG. 5 shows a configuration example of the frequency dividing circuit 20B.
In FIG. 5, reference numerals 21-1 to 21-8 are T-FFs, reference numerals 24-1 to 24-13 are OR gates, and reference numerals 25-1 to 25-1.
Reference numeral 25-14 is an AND gate, reference numerals 26-1 to 26-7 are inverters, reference numerals 27-1 to 27-7 are data input terminals, reference numeral 22 is a clock input terminal, and reference numeral 23 is an output terminal.

The same number of T-FFs as the number of bits n of the accumulator 1 are used to form an n-bit binary counter. Here, the case where n = 8 is shown. The setting data is 7 bits, and the data input terminals 27-1 to 27-7
To K6 to K0 are input. K6 is the most significant bit, K
0 is the least significant bit. OR gate, AND gate,
The inverter functions as a control gate for setting the division ratio according to the 7-bit setting data. For example, K6
When = 1, "0" is input to the AND gate 25-1 and "1" is input to the AND gate 25-2 via the OR gate 24-1, so that the T-FFs 21-1 and 21-2 are used. The clock divided by four is AND gate 25-2 and O.
It is output via the R gate 24-7. Similarly, K5 =
When it is 1, the clock divided by 8 through the T-FFs 21-1, 21-2 and 21-3 is output through the AND gate 25-4 and the OR gate 24-8.

Like the accumulator 1, the frequency ^dividing circuit 20B operates in a clock cycle of 2 ⁿ / (the greatest common divisor of K and 2 ⁿ ). Here, a case where n = 8 and K = 96 (1100000) will be described. The greatest common divisor of K = 96 and 2 ⁸ = 256 is
Since it is 32, the accumulator 1 operates at 256/32 = 8 clock cycles. On the other hand, the data input to the frequency divider circuit 20B shown in FIG. 5 is K6 = K5 = 1, K4 to K0 = 0.
Therefore, the output of the T-FF 21-3 is the frequency divider circuit 20B.
, And the division ratio becomes 8. That is,
The operation cycle of the frequency dividing circuit 20B coincides with the operation cycle of the accumulator 1 which is 8 clock cycles. In this way, since the frequency division ratio of the frequency divider circuit 20B can be set to the minimum value in accordance with the frequency setting data K, the integrator 5 can be effectively reset. The waveform of each part of the frequency synthesizer of this embodiment matches the waveform of FIG.

(Third Embodiment: Claim 4) FIG. 6 shows a third embodiment of the frequency synthesizer of the present invention. The feature of this embodiment is that, in place of the frequency divider circuit 20B of the second embodiment shown in FIG. 4, the most significant bit of the count value of the accumulator 1 or the overflow signal is divided by the division ratio of the frequency setting data K. The frequency dividing circuit 20C is used. Other configurations are similar to those of the first and second embodiments.

A case where n = 8 and K = 96 will be described.
The most significant bit of the count value of the accumulator 1 or the overflow signal outputs K = 96 pulses within 2 ⁿ = 256 clock periods. Therefore, the output of the frequency ^dividing circuit 20C with the frequency ^dividing ratio K = 96 includes one pulse within 2 ⁿ = 256 clock periods. That is, the frequency dividing circuit 20C
Is a signal obtained by ^dividing the clock by 2 ⁿ (in the first embodiment,
A signal having the same number of pulses as the output signal of the frequency dividing circuit 20A ) is output. The frequency dividing circuit 2 of the present embodiment
A low frequency of 1/2 or less of the clock is input to 0C, so that power consumption can be reduced.

(Fourth Embodiment: Claim 5) FIG. 7 shows a fourth embodiment of the frequency synthesizer of the present invention. The feature of this embodiment is that the frequency dividing circuits 20A to 20C described above are used.
Instead of this, a digital comparator 28 that outputs a pulse when each bit of the count value of the accumulator 1 matches predetermined data is used. Other configurations are similar to those of the above-described embodiments.

The n-bit comparison data set in the digital comparator 28 must be selected as a value that the accumulator 1 can take. On the contrary, if the comparison data is set as the initial value of the accumulator 1, the count value of the accumulator 1 always matches the comparison data after a certain time has elapsed. For example, if the comparison data is set to “0” and the initial value of the accumulator 1 is set to “0”, no matter what setting data K is set, the count value of the accumulator 1 will be “2” after the elapse of 2 ⁿ clock cycles. It becomes "0". When the comparison data is “0”, the digital comparator 28
Can be implemented simply with an n-input NOR gate. That is, the output of the n-input NOR gate becomes "1" only when all the bits of the count value of the accumulator 1 become "0".

Since the digital comparator 28 outputs one pulse in the 2 ⁿ / (K and 2 ⁿ greatest common divisors) clock cycles, which are the operation cycles of the accumulator 1, FIG.
A signal having the same pulse number as that of the frequency dividing circuit 20B in the second embodiment shown in FIG . Since the digital comparator 28 does not require a T-FF having a relatively large circuit scale, it is possible to reduce the circuit scale and power consumption.

(Fifth Embodiment: Claims 1 and 6) FIG.
Shows a fifth embodiment of the frequency synthesizer of the present invention. The feature of this embodiment resides in that, in the configuration of the first embodiment shown in FIG. 1, a pulse width adjusting circuit 29 for correcting the output pulse width of the frequency dividing circuit 20A to one clock cycle is provided. The output pulse width of the frequency dividing circuit 20A shown in FIG. 2 (e) is set to one clock cycle. Note that the pulse width adjustment circuit 29 can be similarly applied to the second to fourth embodiments, but here, an example applied to the first embodiment will be described.

The normal frequency divider circuit has the same pulse width as the input clock unless the output pulse width is adjusted.
Even if the integrator 5 is reset with the pulse width as it is, there is no problem in the operation of the frequency synthesizer. However, when the output pulse width of the frequency dividing circuit 20A is less than 1 clock, the time when the output of the integrator 5 becomes V ₀ is less than 1 clock cycle, and the integrator 5 starts the integrating operation in the remaining time. Resulting in. Therefore, the reference voltage Vr to be set depends on the output pulse width of the frequency dividing circuit 20A. Therefore, if the output pulse width of the frequency dividing circuit 20A is corrected to one clock cycle and then input to the integrator 5, the integration after reset always starts from V ₀ . As a result, the reference voltage Vr is not influenced by the output pulse width of the frequency divider circuit 20A, and the setting thereof becomes easy.

The pulse width adjusting circuit 29 is, for example, a D-FF.
(Delay flip-flop). If the output pulse of the frequency dividing circuit 20A is connected to the D input of the D-FF and the external clock is connected to the clock input of the D-FF, the output pulse of the frequency dividing circuit 20A is delayed by one clock period and at the same time The width is modified to one clock period.

[0038]

As described above, in the frequency synthesizer of the present invention, the output voltage of the integrator of the conventional direct digital synthesizer which does not use the ROM is periodically reset so that the integration always has the same initial value. It can be started from (known). This allows the output voltage level of the integrator to be uniquely determined. Also,
No voltage error due to drift of the integrator output is accumulated in the voltage level of the integrator output.

The fact that the output voltage level of the integrator is uniquely determined in this way means that it is not necessary to adjust the reference voltage Vr input from the outside. That is, according to the present invention, it is possible to realize a frequency synthesizer capable of high-speed frequency switching with low power consumption and not requiring adjustment of a reference voltage.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a frequency synthesizer of the present invention.

FIG. 2 is a time chart showing an operation example of the first embodiment.

FIG. 3 is a block diagram showing a configuration example of a frequency dividing circuit 20A.

FIG. 4 is a block diagram showing a second embodiment of the frequency synthesizer of the present invention.

FIG. 5 is a block diagram showing a configuration example of a frequency dividing circuit 20B.

FIG. 6 is a block diagram showing a third embodiment of the frequency synthesizer of the present invention.

FIG. 7 is a block diagram showing a fourth embodiment of the frequency synthesizer of the present invention.

FIG. 8 is a block diagram showing a fifth embodiment of the frequency synthesizer of the present invention.

FIG. 9 is a block diagram showing a configuration example of a conventional direct digital synthesizer.

FIG. 10 is a block diagram showing a configuration example of a conventional direct digital synthesizer that does not use a ROM.

11 is a time chart showing an operation example of the configuration shown in FIG.

[Explanation of symbols]

1 accumulator 2 D / A converter 3 delay circuit 4 differential amplifier 5 integrator 6 comparator 7 Toggle flip-flop (T-FF) 8 Differential signal generation circuit 9 Data input terminal 10 Clock input terminal 11 Reference voltage input terminal 12 output terminals 20A, 20B, 20C divider circuit 21 Toggle flip-flop (T-FF) 22 Clock input terminal 23 output terminals 24 OR gate 25 AND gate 26 Inverter 27 Data input terminal 28 Digital comparator 29 Pulse width adjustment circuit 31 Accumulator 32 ROM 33 D / A converter 34 Low-pass filter (LPF) 35 data input terminal 36 clock input terminal 37 output terminals 55 integrator

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03B 28/00 H03K 3/02 H03M 1/60

Claims (6)

(57) [Claims] 1. The frequency setting data K is accumulated every time a clock is input, and when the accumulated value overflows, the excess is used as an initial value for the frequency setting data K.
An n-bit accumulator for continuing the accumulation of the difference, a difference signal generating circuit for outputting a signal corresponding to the difference between the current count value of the accumulator and the count value one clock before, and an output of the difference signal generating circuit. A frequency provided with an integrator that performs time integration, a comparator that compares the output voltage of the integrator with a predetermined reference voltage, and a pulse generator that generates a pulse that is synchronized with the output pulse of the comparator and that serves as a synthesizer output. In the synthesizer, a frequency divider circuit for dividing the clock at a frequency division ratio corresponding to the operating period of the accumulator or an integer multiple thereof, the integrator, when the output pulse of the frequency divider circuit is input, A frequency synthesizer comprising means for resetting its output voltage to a predetermined value. 2. The frequency synthesizer according to claim 1, wherein the frequency dividing circuit is a binary counter having a number of stages equal to the number of bits n of the accumulator. 3. The frequency synthesizer according to claim 1, wherein the frequency division circuit has a frequency division ratio (2 ⁿ / (K and 2 ⁿ greatest common divisor)).
A frequency synthesizer characterized by being a programmable counter set to. 4. The frequency setting data K is accumulated each time a clock is input, and when the accumulated value overflows, the excess is used as an initial value for the frequency setting data K.
An n-bit accumulator for continuing the accumulation of the difference, a difference signal generating circuit for outputting a signal corresponding to the difference between the current count value of the accumulator and the count value one clock before, and an output of the difference signal generating circuit. A frequency provided with an integrator that performs time integration, a comparator that compares the output voltage of the integrator with a predetermined reference voltage, and a pulse generator that generates a pulse that is synchronized with the output pulse of the comparator and that serves as a synthesizer output. In the synthesizer, a frequency divider circuit for dividing the most significant bit of the count value of the accumulator or an overflow signal at a frequency division ratio of the frequency setting data K is provided, and the integrator receives the output pulse of the frequency divider circuit. A frequency synthesizer including means for resetting its output voltage to a predetermined value when the frequency synthesizer is turned on. 5. The frequency setting data K is accumulated every time a clock is input, and when the accumulated value overflows, the excess is used as an initial value for the frequency setting data K.
An n-bit accumulator for continuing the accumulation of the difference, a difference signal generating circuit for outputting a signal corresponding to the difference between the current count value of the accumulator and the count value one clock before, and an output of the difference signal generating circuit. A frequency provided with an integrator that performs time integration, a comparator that compares the output voltage of the integrator with a predetermined reference voltage, and a pulse generator that generates a pulse that is synchronized with the output pulse of the comparator and that serves as a synthesizer output. In the synthesizer, a digital comparator that outputs a pulse when each bit of the count value of the accumulator matches predetermined data, the integrator, when the output pulse of the digital comparator is input, its output voltage A frequency synthesizer characterized by including means for resetting to a predetermined value. 6. The frequency synthesizer according to claim 1, further comprising a pulse width adjusting circuit that corrects a pulse width of a pulse that resets the integrator to a clock cycle.