JP2916943B2 - Frequency multiplier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency doubler which is phase-synchronized with an input pulse and generates an output pulse obtained by multiplying the input pulse by N times.

<Prior Art> Generally, in various fields such as a navigation transceiver, an FM demodulator, and a PCM transceiver, it is required to generate an output pulse that is phase-synchronized with an input pulse and N times the input pulse. Is done. As a circuit for obtaining an output pulse obtained by multiplying the input pulse by N times, a frequency doubler as shown in FIG. 5 has been conventionally provided.

This frequency doubler is a so-called PLL circuit, and the phase comparator a converts the input pulse si and the output pulse so into N
The pulse is frequency-divided into 1 / N by the frequency divider d, and a phase difference pulse corresponding to the phase difference between the two pulse signals is converted into a DC voltage by a low-pass filter b. By controlling the oscillation frequency, an output pulse so obtained by multiplying the frequency of the input pulse si by N is obtained.

However, the frequency multiplier using such a PLL circuit has the following problem. That is, the phase difference pulse output from the phase comparator a contains many frequency components, and by passing this phase difference pulse through the low-pass filter b, the noise component and the high frequency component are removed and the system is locked. Even when the state deviates from the state, the voltage fluctuation is suppressed and stabilized. If the time constant of the low-pass filter b is set to be large, the transient response characteristic becomes slow and the fluctuation of the output voltage can be suppressed. The width becomes narrow and the lock is easily released. Conversely, if the time constant of the low-pass filter b is set low to avoid this, the output voltage of the low-pass filter will include ripples, although the transient response characteristics will be slow and the loss of lock will be reduced. , The frequency of the output pulse so from the voltage controlled oscillator fluctuates. As described above, since the low-pass filters have an opposite relationship to each other, it is difficult to design the low-pass filters to exhibit required characteristics. Further, since the phase comparator, the low-pass filter, and the voltage-controlled oscillator are all analog circuits, they are easily affected by temperature drift, and it is difficult to obtain an output pulse having a stable frequency.

Therefore, in order to solve the above-mentioned problem, in the related art, a frequency doubler that generates an output pulse having a frequency N times the input pulse by digitally processing the input pulse has been proposed (for example, see, for example, Japanese Patent Application Laid-Open No. H11-157556). JP-A-51-4306
No. 0). In this conventional technique, the number K of clock pulses included in one cycle of an input pulse is counted using a clock pulse having a frequency sufficiently higher than the input pulse, and [K / N] (where, [] Is the value of Gaussian symbol), and the count value obtained by counting clock pulses and n · [K / N] (n = 1, 2,..., N)
The output pulse is generated by comparing the value of -1) with each other and generating an output pulse each time the two coincide with each other.

<Problem to be Solved by the Invention> In the above-described prior art, since the frequency multiplier is constituted by a digital circuit, a low-pass filter,
Since a voltage controlled oscillator or the like is not required, there is an advantage that a circuit design is relatively easy, and an output pulse having a stable frequency with little influence of a temperature drift or the like can be obtained.

However, in the related art, the count value K corresponding to the length of one cycle of the input pulse may not be divisible by the multiplication factor N, and a surplus occurs at that time. By ignoring the effect of the remainder, n · [K / N] (n = 1, 2,..., N−
When an output pulse is generated every 1), the last (N-
1) At the pulse, the period of the output pulse becomes longer by the remainder, causing jitter. In order to avoid this, the comparison value for generating the output pulse is set such that the remainder is distributed as evenly as possible within one period of the input pulse.
In addition to n · [K / N], it is necessary to separately add a control circuit for appropriately changing to n · ([K / N] +1), which causes a problem that the circuit configuration is complicated.

<Means for Solving the Problems> The present invention has been made in view of such circumstances, and does not require a low-pass filter such as a PLL circuit, a voltage-controlled oscillator, and the like, and the circuit design is relatively small. It is intended to obtain an output pulse which is easy, has a stable frequency with little influence of temperature drift and the like, and has very little jitter.

For this reason, the present invention employs the following configuration in a frequency doubler that generates an output pulse that is phase-synchronized with an input pulse and N times the input pulse.

That is, the frequency times divider 1 ₁ according to the first invention, an oscillator 2 that outputs a high clock pulse sufficiently frequency than the input pulse, the clock pulse from the oscillator 2 as a clock, the input pulse as a reset pulse ,
A counter 4 that counts and outputs the number K of clock pulses for each cycle of the input pulse, and divides a multiplication factor N preset by the count value K of the counter 4 for each cycle of the input pulse Divider 6 to output
And the output value (= N / K) of the divider 6 is cumulatively added for each period of the input pulse in synchronism with the clock pulse from the oscillator 2 during the period, and a parallel binary data output terminal and an accumulator 10 for the signals of the 2 ^-1 digit output terminal of one digit of a 2 ⁰ digit outputs as N times the circumferential pulses of the input pulse of the.

In the frequency times divider 1 ₂ according to the second invention, the oscillator 2 that outputs a high clock pulse sufficiently frequency than the input pulse
A counter 5 that counts and outputs the number of output pulses for each cycle of the input pulse, using the output pulse as a clock, the input pulse as a reset pulse,
The preset multiplication factor N is compared with the count value N 'of the counter 5, and if the latter is larger than the former (N <
N ') counts down, and in the opposite case (N>N'), a comparator 7 which outputs each permitted signal of counting up, and counts the input pulses according to each permitted signal from the comparator 7. An up / down counter 9 that counts up or down, and the output value of the up / down counter 9 is cumulatively added for each period of the input pulse during that period in synchronization with a clock pulse from the oscillator 2, and a parallel and an accumulator 10 for outputting a signal 2 ^-1 digit output terminal of one digit of a 2 ⁰ digit of the binary data output terminal as an N-fold division pulse of the input pulse.

In the frequency times divider 1 ₃ according to the third invention, the counter 5, a comparator 7 provided with a up / down counter 9,
A D / A converter 12 for D / A converting the output value of the up / down counter 9 in place of the accumulator 10 of the second invention, and a D / A
A voltage-controlled oscillator 14 that outputs a pulse having a frequency corresponding to the output voltage of the converter 12 is provided.

In the frequency times divider 1 ₁ according to the <action> first invention, the counter 4,
It is reset by the rising (or falling) of the input pulse, and the clock pulse from the oscillator 2 is counted from that point. Then, the count value K is taken into the divider 6 at the timing of the rising (or falling) of the next input pulse. Therefore, the divider 6
Is equivalent to the number of clock pulses included in one cycle of the input pulse. The divider 6 divides a preset multiplication factor N by the count value K. Then, the divided value (= N / K) is given to the accumulator 10. After being reset by the rising (or falling) of the input pulse, the cumulative adder 10 cumulatively adds the division value (= N / K) in synchronization with the clock pulse from the oscillator 2. Therefore, since K clock pulses are added before the accumulator 10 is reset by the next input pulse, (N / K) · K = N. That is, the output of the accumulator changes from 0 to N during one cycle of the input pulse.
If you select 2 ^-1-digit terminal of one digit of a 2 ⁰ digits, from the terminal 0～1,1～2, ..., and each one cycle each interval (N-1) to N pulses An output is obtained, which is an output pulse obtained by multiplying the input pulse by N times.

In the frequency times divider 1 ₂ according to the second invention, the counter 5,
It is reset by the rise (or fall) of the input pulse, and the output pulse is counted from that point.
Then, the count value N ′ is taken into the comparator 7 at the timing of the rising (or falling) of the next input pulse. The comparator 7 compares the preset frequency multiplication factor N with the count value N 'of the counter 5, and if the latter is larger than the former (N <N'), the countdown is performed; N '), each of the count-up allowable signals is output. The up / down counter 9 counts up or down the input pulse according to each allowable signal from the comparator 7. When N 'and N are equal (N' = N) in the comparator 7, the up / down counter stops its operation. Then, the count value M of the up / down counter 9 is given to the accumulator 10. After being reset by the rising (or falling) of the input pulse, the accumulator 10 cumulatively adds the count value M of the up / down counter 9 in synchronization with the clock pulse from the oscillator 2. Since K clock pulses are added to the accumulator 10 until it is reset by the next input pulse, M · K = N ′, but N ′ ≠ N
In the case of (1), since the up / down counter 9 counts up or down, the count value M is changed, so that the count value of the up / down counter 9 gradually converges, and when N ′ = N, M = N / K. Thus, by selecting the 2 ^-1-digit terminal of one digit of a 2 ⁰ digit of the parallel binary data output terminal of the accumulator 10, as in the first invention, from the terminal input pulse Is obtained by multiplying N by N.

In the frequency times divider 1 ₃ according to the third invention, the counter 5, the operation of the comparator 7 and the up / down counter 9 is the same as in the second invention, the count value of the up / down counter 9 M Is supplied to the D / A converter 12. D
Since the / A converter 12 converts the count value M into an analog signal, a voltage corresponding to the count value M is applied to the voltage control oscillator 14. The voltage controlled oscillator 14 generates an output pulse having a frequency according to the input voltage. If the multiplication rate N 'of the output pulse of the voltage-controlled oscillator 14 does not match the preset multiplication rate N (N' ≠ N) with respect to the input pulse, the up pulse is increased as in the second invention. Since the count value M of the up / down counter 9 is changed, the count value of the up / down counter 9 gradually converges, and when N ′ = N, M = N /
It becomes K. Therefore, since the voltage applied to the voltage controlled oscillator 14 has a value corresponding to N / K, the voltage controlled oscillator 14 generates an output pulse obtained by multiplying the input pulse by N times.

Embodiment 1 Embodiment 1 FIG. 1 is a block diagram of a frequency doubler according to an embodiment of the first invention. In the figure, reference numeral 1 ₁ shows the overall frequency times divider, 2 an oscillator for outputting a high clock pulse sc enough frequency than the input pulse si, 4 the oscillator 2
Counter that counts the clock pulse sc from the controller and inputs the input pulse si as a reset pulse.
Is a divider that divides a multiplication factor N set in advance by the count value K of the counter 4, and 8 is an output value of the divider 6 (=
A latch circuit 10 for latching N / K) is a cumulative adder for cumulatively adding the output of the latch circuit 8 in synchronization with the clock pulse sc from the oscillator 2 and inputting the input pulse si as a reset pulse.

Next, the operation of the frequency times divider 1 ₁ having the above-described configuration will be described with reference to the timing chart shown in Figure 2.

The counter 4 is reset by the rising edge of the input pulse si.
Count sc. Then, the count value K of the counter 4 is taken into the divider 6 at the timing of the next rising of the input pulse si. Accordingly, the count value K applied to divider 6 corresponds to the number of clock pulses sc contained within one period T ₀ of the input pulse si.

The divider 6 divides a preset multiplication factor N by the count value K. Input pulse compared to multiplication factor N
Since the number K of clock pulses sc included in one period T ₀ of the si is sufficiently large, the output of the divider 6 (= N / K) has a value of decimal (<1). Then, the divided value (= N / K) is given to the accumulator 10.

After being reset by the rise of the input pulse si, the accumulator 10 accumulates a division value (= N / K) in synchronization with the clock pulse from the oscillator 2. Therefore, since K clock pulses sc are added before the accumulator 10 is reset by the next input pulse si, (N /
K) K = N. That is, the output of the accumulator changes from 0 to N with a step size of N / K (<1) every time the clock pulse sc is applied during one cycle of the input pulse. Therefore, 0, 1, 1-2, ..., (N-1) -N
If a pulse output having each period of one period can be taken out, this is an output pulse obtained by multiplying the input pulse by N times. Here, the output data of the accumulator 10 is 2
Since a binary number, now paying attention to 2 ^-1-digit terminal Qa of one digit of a 2 ⁰ digit of the parallel binary data output terminal, from the terminal Qa, if the decimal point is less than 0 to 0.5 Outputs an "L" level signal and an "H" level signal when it is less than 0.5 to 1.0.
2,..., (N−1) to N can be extracted as pulse outputs each having one cycle.

For example, the multiplication factor N = 3, the count value K of the counter 4
= 20, the output of the divider 6 is N = 3/20 = 0.15, so the output of the accumulator 10 is one cycle T _{0 of the} input pulse si.
Between 0 and 3 with a step size of 0.15. Here, 2 from ^-1 digit output terminals Qa, when decimal values are decimal is less than 0 to 0.5 is "L" level, 0.5-1.0
In this case, a "H" level signal is output, so that a pulse output having one cycle of each of the sections 0 to 1, 1-2, and 2-3 is obtained from this terminal Qa. pulse
This is an output pulse so that si is tripled.

If the value of N / K is not divisible, there is a remainder, but the remainder takes a value after the decimal point,
Each section of 1, 1, 2, ..., (N-1) to N (section width 1)
In this example, the input pulse
An output pulse so obtained by multiplying si by N times is obtained. In this case, in the example shown in FIG. 2, since K = 20, which is a relatively small value, the influence of one cycle t ₀ of the clock pulse sc increases, and each cycle t _{0 of the} multiplied output pulse so The duty ratio for each of ₁ , t ₂ , and t ₃ fluctuates. However, if the frequency fc of the clock pulse sc is increased, the count value K increases.
The duty ratio is approximately one to one. In addition, if the frequency fc of the clock pulse sc is set to a relatively high value, the value of N / K decreases, and accordingly, the jitter of the output pulse so multiplied decreases.

Embodiment 2 FIG. 3 is a block diagram of a frequency doubler according to an embodiment of the second invention, and portions corresponding to FIG. 1 are denoted by the same reference numerals.

In Figure 3, reference numeral 1 ₂ denotes the entire frequency times divider, 2 an oscillator for outputting a high clock pulse sc enough frequency than the input pulse si, with 5 counts the output pulses so, the input pulse si Is input as a reset pulse. The counter 7 compares the preset multiplication factor N with the count value N 'of the counter 5 and counts down if the latter is larger than the former (N <N'). In the opposite case (N> N '), the comparator 9 outputs each count-up allowable signal, and the up / down 9 counts up or down the input pulse si according to each allowance signal from the comparator 7. The counter 10 accumulatively adds the output value of the up / down counter 9 in synchronization with the clock pulse from the oscillator 2 and sets the input pulse si as a reset pulse. A cumulative adder which inputs Te.

Next, the operation of the frequency times divider 1 ₂ of the above configuration.

In the frequency multiplier ₁₂ , the counter 54 sets the input pulse si
And the output pulse so is counted from that point. Then, the count value N 'of the counter 5 is taken into the comparator 7 at the timing of the next rising of the input pulse si. The comparator 7 compares the preset frequency multiplication factor N with the count value N 'obtained by the counter 5, and if the latter is larger than the former (N <N'), counts the "L" level. In the opposite case (N>
N '), an "H" level count allowable signal is output.

The up / down counter 9 receives an input pulse when an “L” level count allowable signal is applied from the comparator 7.
Each time si is added, it is counted down, and conversely, when an "H" level count allowable signal is added, it is counted up each time an input pulse si is added. When N 'and N are equal in the comparator 7, (N' =
N), the up / down counter 9 stops operating. Then, the count value M of the up / down counter 9 is given to the accumulator 10.

After being reset by the rise of the input pulse si, the cumulative adder 10 cumulatively adds the count value M from the up / down counter 9 in synchronization with the clock pulse sc from the oscillator 2. The cumulative adder 10, during one period T ₀ is reset at the next input pulse si, clock pulses sc is K
Since the number is added, M · K = N ′. However, if N ′ ≠ N, the up / down counter 9 counts up or down as described above, so the count value M is changed. Therefore, as time elapses, the count value M of the up / down counter 9 gradually converges, and when it converges to N '= N, M = N / K.

Again, by selecting the 2 ^-1-digit terminal Qa of one digit of a 2 ⁰ digit of the parallel binary data output terminal of the accumulator 10, as in the embodiment 1, the terminal Qa From this, an output pulse so obtained by multiplying the input pulse si by N times is obtained.

Third Embodiment FIG. 4 is a block diagram of a frequency multiplier according to a third embodiment of the present invention, and portions corresponding to FIGS. 1 and 3 are denoted by the same reference numerals.

In Figure 4, reference numeral 1 ₃ shows the overall frequency times divider, the counter 5, 7 comparator, 9 is an up / down counter, since these structures are the same as in Example 2 Description is omitted.

The feature of the third embodiment is that the accumulator in the second embodiment is used.
Instead of 10, the output value M of the up / down counter 9 is changed to D /
A D / A converter 12 for A-conversion and a voltage-controlled oscillator (VC) for outputting a pulse having a frequency corresponding to the output voltage of the D / A converter 12
O) 14 is provided.

Next, the operation of the frequency times divider 1 ₃ of the above configuration.

In the frequency times divider 1 _3, counter 5, the operation of the comparator 7 and the up / down counter 9 is a same manner as in Example 2, the count value M of the up / down counter 9 is D / A It is provided to the converter 12. Since the D / A converter 12 converts the count value M into an analog signal, a voltage corresponding to the count value M is applied to the voltage controlled oscillator 14. The voltage controlled oscillator 14 generates an output pulse having a frequency according to the input voltage. Voltage controlled oscillator for input pulse si
If the multiplication factor N 'of the 14 output pulse so does not match the multiplication factor N preset for the comparator 7 (N' ≠ N), the up / down operation is performed as in the second invention. Since the count value M of the counter 9 is changed, the count value of the up / down counter 9 gradually converges, and when N ′ = N, M = N / K. Therefore, if the oscillation frequency of the voltage-controlled oscillator 14 is set in advance such that when a voltage having a value corresponding to N / K is applied, an output pulse so having a frequency N times the input pulse si is generated, With the count value M of the up / down counter 9 converging, the voltage-controlled oscillator
From 14, an output pulse so obtained by multiplying the input pulse si by N times is generated.

<Effects of the Invention> According to the present invention, the following effects can be obtained.

(I) In any of the first to third inventions, a phase comparator such as a PLL circuit and a low-pass filter are unnecessary,
The circuit design is relatively easy, and an output pulse having a stable frequency with little influence of temperature drift or the like can be obtained.

(Ii) In particular, in the first and second aspects of the present invention, if the clock pulse output from the oscillator of another circuit (for example, CPU) is shared, the output pulse multiplied with the operation of the other circuit can be used. Can be completely synchronized.

(Iii) In the first aspect, the jitter of the output pulse multiplied by the frequency can be obtained by setting the frequency of the clock pulse to fc.
1 / fc, and the jitter can be extremely reduced by setting the frequency of the clock pulse high.

(Iv) Further, in the second invention, since it is a feedback type in which the output pulse is fed back to the counter,
Although it takes some time for the down counter to converge to a fixed value, there is an advantage that the circuit configuration is simplified because the divider as in the first invention is unnecessary.

[Brief description of the drawings]

1 to 4 show an embodiment of the present invention. FIG. 1 is a block diagram of a frequency multiplier according to Embodiment 1 of the first invention.
FIG. 2 is a timing chart for explaining the operation of the frequency multiplier of FIG. 1, FIG. 3 is a block diagram of the frequency multiplier according to the second embodiment of the second invention, and FIG. 4 is an embodiment of the third invention. Example 3
FIG. 3 is a block diagram of the frequency multiplier according to FIG. FIG. 5 is a block diagram of a frequency doubler using a conventional PLL circuit. 1 ₁ , 1 ₂ , 1 ₃ ... frequency multiplier, 2 ... oscillator, 4 5 ... counter, 6 ... divider, 7 ... comparator, 9 ... up / down counter, 10 ... accumulator, 12 ... D / A converter, 14 ... voltage controlled oscillator (VCO).

Claims (3)

(57) [Claims] An oscillator (2) for outputting a clock pulse having a frequency sufficiently higher than an input pulse in a frequency doubler for synchronizing the input pulse and generating an output pulse obtained by multiplying the input pulse by N times; A counter (4) that uses the clock pulse from the oscillator (2) as a clock, uses the input pulse as a reset pulse, counts and outputs the number K of clock pulses for each cycle of the input pulse, and ), A divider (6) that divides a preset multiplication factor N by one cycle of the input pulse and outputs the divided value, and an output value (= N) of the divider (6). / a K) in synchronism with the clock pulses from the oscillator (2) by accumulating during the period for each cycle of the input pulse, one digit of a 2 ⁰ digit of the parallel binary data output terminal And a cumulative adder (10) that outputs the signal of the ^2-1 digit output terminal as an N-fold pulse of the input pulse. 2. An oscillator (2) for outputting a clock pulse having a frequency sufficiently higher than the input pulse in a frequency doubler which is phase-synchronized with the input pulse and generates an output pulse obtained by multiplying the input pulse by N times. A counter (5) that counts and outputs the number of output pulses for each cycle of the input pulse, using the output pulse as a clock and the input pulse as a reset pulse, a preset multiplication factor N and the counter Compared with the count value N 'in (5), if the latter is larger than the former (N
<N ′), a comparator (7) that outputs a countdown allowable signal in the opposite case (N> N ′), and a comparator (7) that outputs a countup enable signal according to each allowable signal from the comparator (7). An up / down counter (9) for counting up or down the input pulse; and outputting an output value of the up / down counter (9) in synchronism with a clock pulse from the oscillator (2) for each cycle of the input pulse. the cumulatively added during the period, the cumulative adder that outputs a signal of 2 ^-1 digit output terminal of one digit of a 2 ⁰ digit of the parallel binary data output terminal as an N-fold division pulse of the input pulse (10) A frequency multiplier comprising: 3. A frequency doubler for generating an output pulse which is phase-synchronized with an input pulse and which is obtained by multiplying the input pulse by N times, wherein said output pulse is used as a clock, said input pulse is used as a reset pulse, and said input pulse is used as a reset pulse. A counter (5) that counts and outputs the number of output pulses for each cycle, and compares a preset multiplication factor N with a count value N 'of the counter (5), and the latter is larger than the former. Case (N
<N ′), a comparator (7) that outputs a countdown allowable signal in the opposite case (N> N ′), and a comparator (7) that outputs a countup enable signal according to each allowable signal from the comparator (7). An up / down counter (9) for counting up or down the input pulse; a D / A converter (12) for D / A converting the output value of the up / down counter (9); A frequency controlled oscillator (14) that outputs a pulse having a frequency corresponding to the output voltage of the device (12).