JPH04144416A - Frequency multiplier - Google Patents

Abstract

PURPOSE:To obtain an output pulse with reduced jitter by dividing a set frequency multiplication ratio by a count value of a counter, accumulatively adding respective divided values synchronously with a clock pulse outputted from an oscillator and inputting an input pulse as a reset pulse. CONSTITUTION:The counter 4 is reset by the leading edge (or trailing edge) of an input pulse and starts the counting of clock pulses from the oscillator 2. At the leading edge (or trailing edge) timing of the succeeding input pulse, the count value K of the counter 4 is inputted to a divider 6. The divider 6 divides the previously set frequency multiplication ratio by the count value K and applies its divided value (= N/K) to an accumulative adder 10. After being reset by the leading edge (or trailing edge) of the input pulse, the adder 10 accumulatively adds the divided value (= N/K) synchronously with the clock pulse outputted from the oscillator 2. Thus, the generation of jitter can be reduced by setting up the frequency of each clock pulse to a high value.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a frequency doubler that generates an output pulse that is phase-locked to an input pulse and is N times the frequency of the input pulse.

<Prior Art> Generally, in various fields such as navigation transceivers, FM demodulators, PCM transceivers, etc., it is required to generate an output pulse that is phase-locked to the input pulse and is N times the frequency of the input pulse. Ru. As a circuit for obtaining an output pulse obtained by multiplying the frequency of such an input pulse by N, a frequency doubler as shown in FIG. 5 has conventionally been provided.

This frequency multiplier is a so-called P L 1. , a circuit in which a phase comparator a compares an input pulse si and a pulse obtained by dividing an output pulse sO into I/N by an N frequency divider d, and calculates a position according to the phase difference between the two pulse signals. The phase difference pulse is converted into a DC type T by a low-pass filter b, and the oscillation frequency of the voltage controlled oscillator C is controlled by this DC voltage, thereby obtaining an output pulse SO that is N times the frequency of the input pulse si.

However, a frequency doubler using such a PL, L circuit has the following problems. That is, the phase difference pulse output from the phase comparator a contains many frequency components, and this phase difference pulse is passed through the low-pass filter b.
By passing the low-pass filter b, noise components and high-frequency components are removed, and even if the system goes out of lock, voltage fluctuations are suppressed and stabilized. However, if the time constant of this low-pass filter b is set to a large value, Although the transient response characteristics become slower and fluctuations in the output voltage are suppressed, the lock range becomes narrower and the lock becomes more likely to come off. To avoid this, conversely, if the time constant of low-pass filter b is set low, the transient response characteristics will become faster and lock loss will be reduced, but the output voltage of the low-pass filter will include ripples, and this The frequency of the output pulse SO from the voltage controlled oscillator varies accordingly. As described above, since low-pass filters have mutually contradictory relationships, it is difficult to design them to exhibit desired characteristics. Also,
Since the phase comparator, low-pass filter, and voltage-controlled oscillator are all analog circuits, they are easily affected by temperature drift, making it difficult to obtain output pulses with a stable frequency.

Therefore, in order to solve the problems mentioned in 2., conventional technology has proposed a frequency doubler that generates an output pulse with a frequency N times that of the input pulse by digitally processing the input pulse. (For example, JP-A-51-43
(See Publication No. 060).

In this conventional technology, the number of clock pulses included in one period of the input pulse is counted using a clock pulse having a frequency sufficiently higher than that of the input pulse, and the count value K is calculated from [K/N] (where , [] is a Gauss symbol)
While finding the value of , calculate the count value of clock pulses and n・[: K/N1(n= ], 2,...,
N-1) and each time they match, an output pulse is generated, thereby obtaining an output pulse whose frequency is N times the frequency of the input pulse.

<Problems to be Solved by the Invention> In the above-mentioned conventional technology, the frequency doubler is configured by a digital circuit, so a low-pass filter, a voltage-controlled oscillator, etc. are not required, and therefore the circuit design is relatively simple. It has the advantage of being easy to use, less affected by temperature drift, etc., and output pulses with a stable frequency can be obtained.

However, in the prior art, the count value ■ (corresponding to the length of one cycle of the input pulse) may not be divisible by the multiplication factor N, and in that case, a remainder occurs. Ignoring the influence of this remainder, n・[K/N] (n=32,=N-1
), the last (N-1)
At the pulse point, the period of the output pulse becomes longer by the remainder, causing jitter. To avoid this, the comparison values for generating the output pulses should be adjusted so that the remainder is distributed as evenly as possible within one cycle of the input pulses.
It is necessary to separately add a control circuit to appropriately change n·([K/Nl + 1) in addition to [K/N], which causes a problem that the circuit configuration becomes complicated.

<Means for Solving the Problems> The present invention has been made in view of the above circumstances, and eliminates the need for a low-pass filter such as a PLL circuit, a voltage-controlled oscillator, etc., and requires a relatively simple circuit design. It is possible to easily obtain an output pulse having a stable frequency with little influence from temperature drift, etc., and extremely low jitter.

Therefore, the present invention employs the following configuration in a frequency doubler that generates an output pulse that is phase synchronized with an input pulse and whose frequency is N times the input pulse.

That is, the frequency doubler 11 according to the first invention includes an oscillator 2 that outputs a clock pulse having a sufficiently higher frequency than an input pulse, and counts clock pulses from the oscillator 2, and also uses the input pulse as a reset pulse. A counter 4 is inputted, a divider 6 divides a preset frequency multiplication factor N by the count value of this counter 4, and an output value (=N/K) of this divider 6 is inputted from an oscillator 2. The accumulative adder IO performs cumulative addition in synchronization with the clock pulse of , and inputs an input pulse as a reset pulse.

In the frequency doubler 12 according to the second invention, the oscillator 2 outputs a clock pulse having a sufficiently higher frequency than the input pulse.
Then, a counter 5 that counts output pulses and inputs input pulses as a reset pulse compares a preset frequency multiplication factor N with the count value N' of this counter 5, and if the latter is larger than the former. A comparator 7 outputs each allowable signal for counting down when (N<N'') and counting up when vice versa (N>N'), and the input signal is inputted according to each allowable signal from this comparator 7. An up/down counter 9 that counts up or down pulses, and a cumulative addition that cumulatively adds the output value of the up/down counter 9 in synchronization with the clock pulse from the oscillator 2, and inputs the input pulse as a reset pulse. It is equipped with a device IO.

The frequency doubler 13 according to the third invention includes a counter 5, a comparator 7, an up/down counter 9, and
In place of the cumulative adder IO of the second invention, there is provided a D/A converter 12 for D/A converting the output value of the up/down counter 9, and a pulse having a frequency corresponding to the output voltage of the D/A converter 12. The configuration includes a voltage controlled oscillator 14 that outputs .

<Operation> Frequency doubler according to the first invention 1. Then, counter 4 is
It is reset by the rising edge (or falling edge) of the input pulse, and the clock pulses from the oscillator 2 are counted from that point on. Then, the count value K is taken into the divider 6 at the timing of the rise (or fall) of the next input pulse. Therefore, divider 6
The count value added to corresponds to the number of clock pulses included in one cycle of the input pulse. The divider 6 divides a preset frequency multiplying factor N by the count value. Then, the division value (=N/K) is added to the cumulative adder I
Give to O. After being reset by the rising edge (or falling edge) of the input pulse, the cumulative adder 10 calculates the division value (=N/K) in synchronization with the clock pulse from the oscillator 2.
) are cumulatively added.

Therefore, until the cumulative adder 10 is reset by the next input pulse, K clock pulses are added, so (N/K)·K=N. In other words, the output of the cumulative adder ('' changes from 0 to N during one cycle of the input pulse, so if you select the 2-1 digit terminal among the data output terminals, this terminal From 0 to 1.1 to 2, , (N
A pulse output is obtained in which each interval from -1) to N is one period, and this becomes an output pulse obtained by multiplying the frequency of the input pulse by N.

In the frequency doubler 12 according to the second invention, the counter 54 is reset by the rising edge (or falling edge) of the input pulse, and counts the output pulses from that point on. Then, at the timing of the rising (or falling) of the next input pulse, the count value N' is transferred to the comparator 7.
be taken in.

The comparator 7 uses a preset frequency multiplication factor N and this counter 5.
When the latter is larger than the face (N<N'), the count is down, and vice versa (N>
Each count-up permission signal is output to N'). The up/town counter 9 counts up or down the input pulses depending on each allow signal from the comparator 7. Further, when both N° and N are equal in the comparator 7 (N”=N), the up/down counter stops operating.Then, the up/down counter 9
The count value M of is given to the cumulative adder 10.

The cumulative adder IO cumulatively adds the count value M of the up/down counter 9 in synchronization with the clock pulse from the oscillator 2 after being reset by the rising (or falling) of the input pulse.

Since K clock pulses are added to the cumulative adder 10 until it is reset by the next input pulse, M-=N, but if N°≠N, the up/down counter Since 9 counts up or down, the count value M changes, so
The count value of the down counter 9 gradually converges and becomes N'
=N, and M=N/. Therefore, cumulative adder 1
If the 2-1 digit terminal is selected among the 0 data output terminals, an output pulse obtained by multiplying the frequency of the input pulse by N times is obtained from this terminal, as in the case of the first invention.

In the frequency doubler 13 according to the third invention, the counter 5
, the comparator 7 and the up/down counter 9 are similar to those in the second invention, except that the count value M of the up/down counter 9 is applied to the D/A converter 12. Since the D/A converter 12 converts this count value M into an analog signal, a voltage corresponding to the count value M is applied to the voltage controlled oscillator I4. Voltage controlled oscillator I4 generates an output pulse with a frequency depending on this input voltage. When the frequency multiplication factor N'' of the output pulse of the F-controlled oscillator 14 does not match the preset frequency multiplication factor N (N7N) with respect to the input pulse, as in the case of the second invention, the /Since the count value M of the down counter 9 is changed, the count value of the up/down counter 9 gradually converges, and N'=N
Then, M=N/. Therefore, the voltage controlled oscillator 1
The voltage applied to 4 (the value corresponds to J, N/K, so
The voltage controlled oscillator 14 generates an output pulse whose frequency is N times the input pulse.

<Embodiment> Actual Contribution 1- FIG. 1 is a block diagram of a frequency doubler according to an embodiment of the first invention. In the same figure, reference numeral d indicates the entire frequency multiplier, 2 is an oscillator that outputs a clock pulse SC having a sufficiently higher frequency than the input pulse si, and 4 is a clock pulse oscillator that outputs a clock pulse SC from the oscillator 2. ,
A counter that inputs the input pulse si as a reset pulse, 6 a divider that divides the preset frequency multiplication factor N by the count value of the counter 4, and 8 the output value of the divider 6 (=N/K ), and io is a cumulative adder that cumulatively adds the output of the latch circuit 8 in synchronization with the clock pulse SC from the oscillator 2, and inputs the input pulse si as a reset pulse.

Next, frequency doubler 1 with the above configuration. The operation will be explained with reference to the timing chart shown in FIG.

The counter 4 is reset at the rising edge of the input pulse si, and counts the clock pulse SC from the oscillator 2 from that point on. Then, the count value K of the counter 4 is taken into the divider 6 at the timing of the next rise of the on-off pulse s1. Therefore, the count value applied to the divider 6 includes one period T of the input pulse si. corresponds to the number of clock pulses SC contained within.

The divider 6 divides a preset frequency multiplying factor N by the count value. Input pulse s compared to frequency multiplier N
One period T of i. Since the number of clock pulses SC included in is sufficiently large, the output (=N/K) of the divider 6 takes a value below the decimal point (<1). Then, the division value (=N/
K) is applied to the cumulative adder 10.

The cumulative adder IO cumulatively adds the division value (=N/K) in synchronization with the clock pulse from the oscillator 2 after being reset by the rising edge of the input pulse si. Therefore, until the cumulative adder IO is reset by the next input pulse si, each clock pulse sc is applied, so that (N/K)·K=N. That is, the output of the cumulative adder changes from θ to N during one period of the input pulse with a step size of N/K (<1) every time the clock pulse SC is applied. Therefore, 0-1, 1-2,
If it is possible to extract a pulse output in which each interval from (N1) to N constitutes one period, this becomes an output pulse obtained by multiplying the frequency of the in-off pulse by N times. Here, since the output data of the cumulative adder 10 is a binary number, if we pay attention to the 2-1 digit terminal Qa among the data output terminals, from this terminal Qa, the decimal places are 0 to 0. “L” level if less than 5, “H” if less than 0.5 to 1.0
Since a level signal is output, 0 to I
, 1 to 2, ... (N-1) to N, each section is 1
A periodic pulse output can be extracted.

For example, if the frequency multiplier is N23 and the count value of counter 4 is -
20, the output of divider 6 N=3/20=0.1
5, the output of the cumulative adder 10 is the input pulse s
One period T of i. O~3 with step size of 0.15 between
changes up to. Here, from the 2-1 digit output terminal Qa, if the value below the decimal point is from 0 to less than 0.5, the level is "L", and when it is from 0.5 to less than 1.0, the level is "H". ”
Since a level signal is output, this terminal Qa outputs 0
A pulse output is obtained in which each period of ~1.1~2.2~3 is one period, and this becomes an output pulse SO having three times the frequency of the input pulse si.

Note that if the value of N/ is not divisible, either a remainder will occur or the remainder will take a value below the decimal point, which is between 0 and 1.
, 1 to 2, ..., each section from (N-1) to N (section width 1)
In this example, the output pulse SO is obtained by multiplying the frequency of the input pulse si by N times. In this case, in the example shown in FIG. 2, one period t of the clock pulse SC is set to a relatively small value of N20. Each period t1 of the frequency-doubled output pulse SO increases as the influence of
, t2, and t3, but if the frequency fc of the clock pulse SC is increased, the count value K becomes larger, so the duty ratio becomes approximately 1:1.

Moreover, if the frequency fc of the clock pulse SC is set to a certain high value, the value of N/ will be reduced, and accordingly, the jitter of the frequency-multiplied output pulse sO will be reduced.

Embodiment 2 FIG. 3 is a block diagram of a frequency doubler according to an embodiment of the second invention, and parts corresponding to those in FIG. 1 are given the same reference numerals.

In FIG. 3, symbol I indicates the entire frequency doubler, 2 is an oscillator that outputs a clock pulse SC having a sufficiently higher frequency than the input pulse si, and 5 is an oscillator that counts the output pulse SO and also counts the input pulse si. is input as a reset pulse, and 7 is a preset frequency multiplication factor N.
is compared with the count value N' of the counter 5, and if the latter is larger than the former (N<N'), a countdown is performed, and in the opposite case (N>N'), a countup is activated. an up/down counter 9 that counts up or down the input pulse si according to each allowable signal from the comparator 7;
Reference numeral 10 denotes a cumulative adder which receives the output value of the up/down counter 9 by the same value as the clock pulse from the oscillator 2 and cumulatively adds it, and inputs the input pulse si as a reset pulse.

Next, the operation of the frequency doubler 12 having the above configuration will be explained.

In this frequency multiplier I2, the counter 54 is reset by the rising edge of the input pulse s1, and counts the output pulses sO from that point on. Then, at the timing when the next input pulse si rises, the count value N'' of the counter 5 is taken into the comparator 7. After comparing the counted value N', if each is larger than 1iij (N<N'), a count permission signal of "I7" level is output, and in the opposite case (N>N'), an "I7" level count permission signal is output. -, 1" level count permission signal is output.

The up/down counter 9 is output from the comparator 7.

I, if a level count permission signal is applied (
'' Every time an input pulse s1 is added, this is counted down, and conversely, if a count permission signal of ``I-T'' is added, this is counted down every time an input pulse si is added. Also, in the comparator 7, both N゛, N
When they are equal (N'=N), the up/down counter 9 stops operating. Then, the count value M of the up/down counter 9 is given to the cumulative adder 10.

The cumulative adder 10 is reset by the rising edge of the input pulse s1, and then receives the clock pulse S from the oscillator 2.
The count value M from the up/down counter 9 is cumulatively added in synchronization with C. Since the cumulative adder IO is added to the clock pulse SC during one cycle 'ro which is reset by the next input pulse si, M-=N, but since N゛≠N. If the up/down counter 9
Since σ counts up or down as described above, its force σ count value M is changed. therefore,
As time passes, the count value M of the up/town counter 9 gradually converges, and when it converges to N'=N, M
==N/K.

In this case as well, two of the data output terminals of the cumulative adder 10
If the -1 digit terminal Qa is selected, as in the case of Embodiment I, an output pulse SO obtained by multiplying the frequency of the input pulse Si by N is obtained from this terminal r-Qa.

Embodiment 3 FIG. 4 is a block diagram of a frequency doubler according to an embodiment of the third invention, and parts corresponding to FIGS. 1 and 3 are designated by the same reference numerals (=I).

In FIG. 4, the symbol I indicates the entire frequency doubler, 5 is a counter, 7 is a comparator, and 9 is an up/town counter, and these configurations are the same as in the second embodiment. The explanation will be omitted.

The feature of this third embodiment is that the cumulative adder 1 in the second embodiment
Instead of 0, the output value M of the up/down counter 9 is set to D
A D/A converter 12 with 4/A conversion and a voltage controlled oscillator (VC○) 14 that outputs a pulse with a frequency corresponding to the output voltage of each D/A converter 12 are installed. It is that you are.

Next, the operation of the frequency doubler 13 having the above configuration will be explained from 4 to 4.

This frequency doubler1. In other words, the operations of the counter 5, the comparator 7, and the up/down counter 9 are the same as in the second embodiment, and the count value of the up/down counter 9 (M months)/A converter 12 is Ru. Since the D/A converter I2 converts this count value M into an analog signal, a voltage corresponding to the count value M is applied to the voltage controlled oscillator 14. Voltage controlled oscillator 14 generates an output pulse having a frequency according to this input voltage. With respect to the input pulse si, the frequency multiplication factor N of the output pulse SO of the voltage controlled oscillator I4 does not match the frequency multiplication factor N set in advance for the comparator 7 (N"
≠N), as in the case of the second invention, up/
Since the count value M of the down counter 9 is changed, the count value of the up/down counter 9 gradually converges, and when N'=N, M=N/. Therefore, if the oscillation frequency of the voltage controlled oscillator 14 is set in advance so that when a voltage corresponding to N/K is applied, an output pulse sO having a frequency N times that of the input pulse si is generated, Count value M of up/down counter 9
In a state in which the input pulse si has converged, the voltage controlled oscillator 14 generates an output pulse SO whose frequency is N times the input pulse si.

<Effect of the invention> According to the present invention, the following effects can be obtained.

(i) In any of the first to third inventions, P L L
There is no need for a phase comparator or a low-pass filter such as a circuit, so the circuit design is relatively easy, and output pulses with a stable frequency can be obtained with little influence from temperature drift and the like.

(11) In particular, in the first and second inventions, if the tallock pulses output from the oscillators of other circuits (for example, CI, U) are shared, the frequency-doubled output horn pulses can be used to operate the other circuits. can be perfectly synchronized.

(iii) In addition, in the first invention, the knock of the frequency-multiplied output pulse is 1/fc, where fc is the frequency of the clock pulse, and by setting the frequency of the clock pulse high, the knock is extremely reduced. I can do it 1
(iv) Furthermore, in the second invention, since it is a feedback type in which the output pulse is fed back to the counter, it takes a certain amount of time for the up/down counter to converge to a constant value, but unlike the first invention, Since no divider is required, there is an advantage that the circuit configuration is simplified.

[Brief explanation of the drawing]

1 to 4 show embodiments of the present invention, and FIG. 1 is a block diagram of a frequency doubler according to embodiment 1 of the first invention,
2 is a timing chart for explaining the operation of the frequency doubler in FIG. 1, FIG. 3 is a block diagram of the frequency doubler according to the second embodiment of the second invention, and FIG. 4 is an implementation of the third invention. Example 3
FIG. 2 is a block diagram of a frequency doubler according to the present invention. FIG. 5 is a block diagram of a frequency doubler using a conventional PLL circuit. ■+, 13.13... Frequency doubler, 2... Oscillator, 4.5... Counter, 6... Divider, 7... Comparator,
9... Up/down counter, IO... Cumulative adder, 12... I)/Δ converter, 14... Voltage controlled oscillator (VCo).

Claims (3)

[Claims] (1) Phase synchronize with the input pulse and convert this input pulse to N
A frequency multiplier that generates a frequency-multiplied output pulse includes an oscillator (2) that outputs a clock pulse with a frequency sufficiently higher than that of the input pulse, and a clock pulse from this oscillator (2) that is counted, and the input pulse A counter (4) that inputs the value K as a reset pulse, a divider (6) that divides a preset frequency multiplication factor N by the count value K of this counter (4), and A cumulative adder (10) that cumulatively adds an output value (=N/K) in synchronization with a clock pulse from the oscillator (2) and inputs the input pulse as a reset pulse. Frequency doubler. (2) Phase synchronize with the input pulse and convert this input pulse to N
A frequency multiplier that generates a frequency-multiplied output pulse includes an oscillator (2) that outputs a clock pulse with a sufficiently higher frequency than the input pulse, and an oscillator (2) that counts the output pulse and inputs the input pulse as a reset pulse. The counter (5) compares the preset multiplication rate N with the count value N' of this counter (5), and if the latter is larger than the former (N
<N'), a comparator (7) outputs each allowable signal for countdown, and vice versa (N>N'), outputs each allowable signal for countdown, and in response to each allowable signal from this comparator (7). An up/down counter (9) that counts up or down the input pulse; and an up/down counter (9) that cumulatively adds the output value of the up/down counter (9) in synchronization with the clock pulse from the oscillator (2); Accumulation adder (10) that inputs the pulse as a reset pulse
A frequency multiplier comprising: (3) Phase synchronize with the input pulse and convert this input pulse to N
A frequency multiplier that generates a frequency-multiplied output pulse includes a counter (5) that counts the output pulse and inputs the input pulse as a reset pulse, and a preset frequency multiplication factor N and this counter (5). ) with the count value N', and if the latter is larger than the former, then (N
<N'), a comparator (7) outputs each allowable signal for countdown, and vice versa (N>N'), outputs each allowable signal for countdown, and in response to each allowable signal from this comparator (7). An up/down counter (9) that counts up or down the input pulse, and a D/A converter (1) that converts the output value of the up/down counter (9) into a D/A.
2); and a voltage controlled oscillator (14) that outputs pulses with a frequency corresponding to the output voltage of the D/A converter (12).