JP2963552B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer having a function of arbitrarily setting an output frequency and using a phase locked loop (PLL) structure capable of shortening the frequency switching time. It is related to the improvement of.

[0002]

2. Description of the Related Art Conventionally, as a frequency synthesizer using a phase locked loop (PLL) configuration capable of arbitrarily setting an output frequency, a voltage controlled oscillator (VCO:
A feedback signal obtained by dividing the output of a Voltage Controlled Oscillator) using a variable frequency divider and a reference signal having a constant frequency are input to a phase comparator, and the output of the phase comparator is output to a VCO via a loop filter. The configuration of returning is widely applied. FIG. 7 is a diagram showing an example of such a conventional configuration. In the figure, 201 is a VCO, 202 is a frequency divider, 203 is a reference oscillator (OSC), 204 is a phase comparator, and 205 is a loop filter.

[0003]

However, in the above-described conventional configuration, the phase comparator 204 is generally configured to perform a multiplication process of the reference signal and the feedback signal. Since the component contains phase error information, the loop filter 205 for sufficiently suppressing and removing unnecessary harmonics is indispensable. However, the frequency switching time of the frequency synthesizer depends on the time constant of the loop filter 205, and in order to secure the S / N (signal-to-noise power ratio) of the frequency synthesizer output to a certain value or more, the loop filter 205 is required. It is necessary to set a large time constant.

As described above, in the conventional configuration, the improvement of the S / N ratio by removing unnecessary harmonics and the shortening of the frequency switching time are in a reciprocal relationship to each other. There is a problem that it cannot be performed. To remedy this problem, in the configuration of FIG. 7, the time constant of the loop filter 205 is changed from a small value (high-speed pull-in) to a large value (high S / N) in the pull-in operation at the time of frequency switching and the steady operation after the pull-in. A method of switching to has been devised. However, in this method, the output value of the phase comparator 204 fluctuates due to the frequency fluctuation caused by the fluctuation of the input voltage of the VCO 201 generated when the loop filter 205 is switched,
Eventually, a long time transient response occurs. For this reason,
There is a need for additional measures such as suppression of output fluctuations of the loop filter at the time of frequency switching and temporary storage and holding of the output value of the phase comparator, resulting in a problem that the circuit scale becomes large. SUMMARY OF THE INVENTION It is an object of the present invention to provide a frequency synthesizer suitable for miniaturization and IC integration, while avoiding the problem of the reciprocal relationship between the high-speed frequency switching time and the high S / N ratio in the conventional configuration.

[0005]

SUMMARY OF THE INVENTION A frequency synthesizer according to the present invention is a phase-locked loop frequency synthesizer having a voltage-controlled oscillator capable of arbitrarily setting an output frequency according to a control voltage. A first input for receiving a reference clock from the reference oscillator as one input and outputting the reference clock during a closed loop operation and stopping the output of the reference clock during an open loop operation according to an open loop / closed loop switching signal supplied to the other input terminal; an aND gate circuit, said first aND gate times
It divides the reference clock output from the road to cumulative count
A counter for generating and outputting a reference phase signal のhaving a sawtooth waveform having a value range from 0 to 2π radians, and dividing the output frequency of the voltage controlled oscillator to 1 / P (P ≧ 1). A fixed frequency divider for outputting a frequency-divided clock; and an output of the frequency-divided clock during closed-loop operation in response to the open-loop / closed-loop switching signal supplied to the other input terminal. A second AND gate circuit for stopping the output of the divided clock from time to time;
2π of a phase integrated output obtained by integrating a predetermined phase increment step value according to the timing of the output clock of the ND gate circuit
A numerically controlled oscillator that outputs a value modulo radians as a feedback phase signal φ, and the reference phase signal ψ and the feedback phase signal φ are expressed by the equation ε = [｛(ψ−φ) + 3π｝ mod2π].
-Π (where ｛·｝ mod2π is the remainder when divided by 2π radians) and the output range is (-π to π)
A phase comparison circuit that outputs a radian phase error signal ε,
The closed loop operation is opened by the open loop / closed loop switching signal.
The averaging operation of the phase error signal ε in a predetermined time zone after the start
When the value 1 outside the average value of the phase error is obtained,
An averaging circuit that outputs the held value in a loop operation, and inputs the phase error signal ε and 1 outside the phase error average value to open the phase error signal ε during the closed loop operation by the open loop / closed loop switching signal. During the loop operation, a switch for switching and outputting 1 outside the average value of the phase error, a D / A converter for converting the output of the switch into an analog value, and a quantization noise included in the output of the D / A converter A low-pass filter for providing an output from which the component has been removed as the control voltage of the voltage-controlled oscillator.

[0006]

【Example】

[Configuration] FIG. 1 is a configuration example diagram showing a first embodiment of the present invention. In the figure, reference numeral 1 denotes a reference oscillator which outputs a reference clock. Reference numeral 1 denotes an AND gate circuit, which receives the reference clock as one input, outputs a reference clock during a closed loop operation, and outputs a reference clock during an open loop operation in response to an open loop / closed loop switching signal supplied to the other input terminal. To stop. Reference numeral 3 denotes a counter, which divides the frequency of the reference clock from the AND gate circuit 2 and performs a counting operation.
To generate and output a reference phase signal 有 す るhaving a value range from 0 to 2π .

[0007] Reference numeral 4 denotes a voltage controlled oscillator (VCO).
ntrolled oscillator), and outputs an oscillation frequency f ₀ according to a control voltage given from the outside. Reference numeral 5 denotes a fixed frequency divider, which sets the output frequency f ₀ of the VCO 4 to 1 / P (P
≧ 1) and outputs f _CLK (= f ₀ / P). 6 is similar to the AND gate circuit 2, the a f _CLK is the output of the fixed frequency divider 5 as one input, by the open-loop / closed-loop switching signal applied to the other input terminal, during closed-loop operation f _CLK is output, and the output of _fCLK is stopped during the open loop operation.

Reference numeral 7 denotes a numerically controlled oscillator (NCO: Numerical)
A phase-increasing step value (digital value) Δφ externally set according to the timing of the output f _CLK of the AND gate circuit 6, and a feedback phase signal φ (0 ≦ φ ≦ 2π, where φ is a digital value) ) Is output. This NCO 7 can be easily constituted by an adder and a register.

Reference numeral 8 denotes a phase comparison circuit, and the counter 3
Is used as one input (addition value), and the feedback phase signal φ from the NCO 7 is used as the other input (subtraction value) to perform an addition operation. The phase error calculated according to the following equation (1) The signal ε (−π ≦ ε ≦ π) is output.

１ = [｛(ψ−φ) + 3π｝ mod2π] -π (1) (where ｛· mod2π is a remainder when divided by 2π radians) This phase comparison circuit 8 It can be easily configured with an adder.

Reference numeral 9 denotes an averaging circuit, which has a predetermined function after the start of the closed-loop operation according to the open-loop / closed-loop switching signal .
Averages the phase error signal ε from the phase comparator circuit 8 hours, held open route at the time the phase error average value outside 1 was obtained
The held value is output in the step operation. This averaging circuit 9
Can be easily constituted by an adder and a register.

FIG. 3 is a diagram showing an example of the configuration of the averaging circuit 9. As shown in FIG. In the figure, reference numeral 101 denotes an adder which performs an addition operation using a phase error signal ε as one input, a value fed back from a register 102 described later as the other input, and outputs the result. A register 102 temporarily stores the output of the adder 101 and outputs the output in accordance with the timing supplied from the outside. The output of the register 102 is fed back to the adder 101. With the above configuration, ε by the adder 101
Is set to 2 ^m times, and the obtained integrated value is dropped by m bits, that is, a value of 2 ^−m times is set to 1 outside the average value (phase error average output) to obtain 2 ^m An average operation of the sample can be obtained.

Returning to FIG. 1, reference numeral 10 denotes a switch,
The phase error signal ε from the phase comparison circuit 8 and the phase error average value 1 from the averaging circuit 9 are input, and the phase error signal ε is output during the closed loop operation according to the open loop / closed loop switching signal. During the loop operation, 1 is output outside the average value of the phase error. A D / A converter 11 converts an output digital value of the switch 10 into an analog value. Reference numeral 12 denotes a low-pass filter (LPF: Low Pass Filter) which removes a quantization noise component included in the output of the D / A converter 11 and outputs the V / V.
This is a control voltage input of CO4.

FIG. 2 is a structural example showing a second embodiment of the present invention. All components in the configuration example of FIG. 2 are exactly the same as components 1 to 12 of FIG.
The only difference from the first embodiment of FIG. 1 is that the inputs of the AND gate circuits 2 and 6 are connected to the outputs of the fixed frequency divider 5 and the reference oscillator 1, respectively.

[Operation] The operation of the first embodiment of the present invention shown in FIGS. 1 and 3 will be described below with reference to FIGS. 4, 5 and 6. FIG.
(A), (B) and (C) are time charts showing operation examples of the feedback phase signal φ, the reference phase signal ψ, and the phase error signal ε during the closed loop operation. First, referring to FIG. 4, the operation of the synchronization pull-in during the closed loop operation will be described. At time 0, the output of the NCO 7 is set to φ = 0. NC
O7 is for each period ( _1/1/1) of the output signal fCLK of the fixed frequency divider 5.
f _CLK ), the phase increase step value Δφ is continuously accumulated, and the output of the NCO 7 by the accumulation rises stepwise in steps of Δφ as shown in FIG. Next, when the value of φ reaches 2π or more at time t ₁ , the value exceeds 2π and falls to a value obtained by subtracting 2π from the tentative integrated value indicated by the broken line,
It rises again in steps of Δφ. After time t ₁ is repeated time 0 after the same operation to obtain a feedback phase signal φ sawtooth waveform. On the other hand, the reference phase signal [psi, first AN
Since given by numerical values divides and cumulative count it's the output of the D gate circuit 2 in the counter 3, as shown in FIG. 4 (B), a sawtooth waveform having a value range like the φ from 0 to 2π Becomes

Now, consider the case where the feedback phase signal φ has a leading phase with respect to the reference phase signal ψ, as shown in FIG. At this time, a simple numerical difference (ψ−φ) between the reference phase signal ψ and the feedback phase signal φ shown by the broken line in FIG. 4C includes −2π every time the reference phase signal is converted from 2π to 0. Phase jump occurs. This phase jump is corrected by the calculation based on the equation (1), and a phase error signal ε as shown by a solid line in FIG. 4C is obtained.

As described above, in the configuration according to the present invention, the reference phase signal ψ
And the feedback phase signal φ are direct phase information, and a true phase error can be obtained in the phase error signal ε. Therefore, theoretically, the phase error signal ε does not contain harmonic components and is necessary for the conventional configuration. It can be seen that the loop filter for suppressing the harmonic component is essentially unnecessary. For this reason, the time constant of the loop filter, which caused the frequency switching time to be long in the conventional configuration, can be set to a small value in the present invention, and high-speed switching of the frequency becomes possible. The phase error signal ε is converted into an analog value by the D / A converter 11 and, after the quantization noise component is removed by the LPF 12, is fed back as a control voltage input of the VCO 4. With this negative feedback loop configuration, a desired output frequency f ₀ can be obtained.

Here, the relationship between the output frequency f ₀ and the phase increase step value Δφ of the NCO 7 will be derived. First, a reference clock is input of the counter 3 and f _c, the period in FIG. 4 (B) When the frequency division number of the counter 3 and N T _c
Is represented by the following equation (2).

(Equation 2) The period T _NCO of the _{NCO 7} is given by the following equation (3).

(Equation 3) Period T _c of reference phase signal and period T _{NCO of} feedback phase signal
Is T _c = T _NCO in the phase-locked state (2)
From the equations (3), the following equation (4) is obtained.

(Equation 4) The output clock f _CLK of the fixed frequency divider 5 is given by the following (5)
It is shown by the formula.

(Equation 5) Therefore, from the expressions (4) and (5), the output frequency f ₀ can be expressed by the following expression (6).

(Equation 6) (6) from the equation, P, N, When the f _c constant, the output frequency f ₀ is seen to be able to uniquely determine the relationship that is inversely proportional to [Delta] [phi.

Next, FIG. 5 is a flowchart of the frequency switching operation in the configuration of the present invention. In the figure, after the operation is started (START), first in step 1, (6)
The output frequency is set by setting Δφ based on the relationship of the expression, and the closed loop operation of step 2 is started. After the synchronization is pulled in at step 3 by the closed loop operation, the process goes to step 4 where the averaging circuit 9 performs the averaging operation of the phase error signal ε to obtain 1 outside the average value.
Enters an open-loop operation with a control voltage having a holding value of.

The above series of operations will be further described with reference to FIG. FIG. 6 is a time chart of the frequency switching operation based on the flowchart shown in FIG. The upper part in the figure is V
The output frequency of CO4, the middle part shows the open-loop / closed-loop switching signal input to the AND gate circuits 2 and 6, the averaging circuit 9 and the switch 10, and the lower part shows the integrated output of the averaging circuit 9, respectively. In the figure, the output frequency is f
Consider the case of switching to f ₂ from _1. At this time, in the process from step 1 to step 3 in FIG.
Changes from f ₁ to f ₂ by the closed loop operation. Next, from the time when the synchronization pull-in is completed, the output of the averaging circuit 9 is first reset in step 4 and the averaging (integration) process is started immediately. In step 5, the operation is switched to the open loop operation, and the D / A converter 11 and the LP
The output 1 outside the averaging circuit is supplied to F12. Since the outside 1 has a constant value during the open loop operation, a stable output frequency can be obtained. During the open loop operation, the AND gate circuit 2
And 6, the reference clock signal supplied to the counter 3 and the NCO 7 and the output f _CLK of the fixed frequency divider 5 are stopped, whereby the reference phase signal ψ and the feedback phase signal φ
And phase slip of の and φ is prevented. As a result, the phase error signal ε at the start of the next closed loop operation is held at the final value of the previous closed loop operation, and the synchronization pull-in by the next channel switching can be performed at high speed.

Next, the operation of the present invention based on the second embodiment shown in FIG. 2 will be described. 2, the reference phase signal ψ is obtained by the NCO 7 and the feedback phase signal φ is obtained by the counter 3, contrary to the case of the first embodiment of FIG. Thus, derived in the configuration of FIG. 1, (2), and f _c in (3) and (4) f
_{Since CLK} is exchanged with each other, the following equations are obtained.

(Equation 7) On the other hand, since the above-mentioned expression (5) also holds in the configuration of FIG. 2, the output frequency f ₀ eventually corresponds to the above-mentioned expression (6) according to the expressions (5) and (4) ′. Can be expressed by the following equation:

(Equation 8) From the above (6) 'formula, P, N, When the f _c constant,
The output frequency f ₀ is Δφ in the configuration of FIG.
Was inversely proportional to
It can be seen that it can be uniquely determined by a relationship proportional to ψ.

[0021]

As described in detail above, in the configuration of the frequency synthesizer of the present invention, since the feedback phase signal is directly extracted or the reference phase signal is generated by using the NCO, the digital synthesizer is used. Direct phase comparison by signal processing becomes possible. Therefore, the harmonic component generated in the conventional configuration is not generated, and the time constant of the loop filter can be set to a small value, so that the frequency pull-in time in the closed loop operation can be shortened. After the frequency is pulled in by the closed loop operation, the phase error component is averaged using an averaging circuit, and the average value is held and the open loop operation is performed to obtain a signal with high frequency stability. Furthermore, since most of the circuits are digital signal processing, there are advantages such as miniaturization of the circuits and suitability for IC.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of an averaging circuit in FIGS. 1 and 2;

FIG. 4 is a time chart of a feedback phase signal, a reference phase signal, and a phase error signal.

FIG. 5 is a flowchart of a frequency switching operation.

FIG. 6 is a time chart of frequency switching.

FIG. 7 is a block diagram of a frequency synthesizer having a conventional PLL configuration.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reference oscillator 2 AND gate circuit 3 counter 4 VCO 5 fixed frequency divider 6 AND gate circuit 7 NCO 8 phase comparison circuit 9 averaging circuit 10 switch 11 D / A converter 12 LPF 101 adder 102 register 201 VCO 202 minutes Frequency divider 203 Reference oscillator 204 Phase comparator 205 Loop filter

Claims (2)

(57) [Claims] 1. A frequency synthesizer having a phase-locked loop comprising a voltage-controlled oscillator capable of arbitrarily setting an output frequency according to a control voltage, comprising: a reference oscillator for outputting a reference clock; and a reference clock from the reference oscillator. A first AN that outputs the reference clock during a closed loop operation and stops outputting the reference clock during an open loop operation in response to an open loop / closed loop switching signal supplied to the other input terminal as an input.
The value of the D gate circuit, from 0 to cumulative count by the reference clock divides the frequency output from said first AND gate circuit to 2π radians
A counter for generating and outputting a reference phase signal のof a sawtooth waveform having a frequency range, a fixed frequency divider for dividing the output frequency of the voltage controlled oscillator to 1 / P (P ≧ 1) and outputting a divided clock; The divided clock is output as one input, and the divided clock is output during the closed loop operation, and the output of the divided clock is stopped during the open loop operation, according to the open loop / closed loop switching signal supplied to the other input terminal. A second AND gate circuit, and a numerical control for outputting as a feedback phase signal φ a value obtained by modulating 2π radians of a phase integrated output obtained by integrating a predetermined phase increment step value according to the output clock timing of the second AND gate circuit An oscillator, and the reference phase signal ψ and the feedback phase signal φ are expressed by an equation ε =
[｛(Ψ-φ) + 3π｝ mod2π] -π (however,
｛·｝ Mod2π is the remainder when divided by 2π radians)
And a phase comparison circuit that outputs a phase error signal ε having an output range of (−π to π) radians, and a closed loop operation open by the open loop / closed loop switching signal.
The averaging operation of the phase error signal ε in a predetermined time zone after the start
When the value 1 outside the average value of the phase error is obtained,
An averaging circuit that outputs the held value in a loop operation, and inputs the phase error signal ε and 1 outside the phase error average value to open the phase error signal ε during the closed loop operation by the open loop / closed loop switching signal. 1 outside the average phase error value during loop operation
A D / A converter for converting the output of the switch into an analog value, and a voltage-controlled oscillator for removing the quantization noise component included in the output of the D / A converter. And a low-pass filter for giving the control voltage. [Outside 1] 2. The counter according to claim 1, wherein a frequency-divided clock from said fixed frequency divider is supplied as one input of said first AND gate circuit, and said counter outputs a feedback phase signal φ. 2. The frequency synthesizer according to claim 1, wherein a reference clock from said reference oscillator is supplied as one input of said AND gate circuit to output a reference phase signal か ら from said numerically controlled oscillator.