JPH0730418A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To provide a frequency synthesizer having a high frequency switching speed and capable of reducing phase noise generated after the switching of frequency. CONSTITUTION:This frequency synthesizer is constituted of a circuit for generating a frequency control signal, a band limiting circuit 14 for receiving an output from the generating circuit and a voltage controlled oscillator 15 and the circuit for generating the frequency control signal is constituted of a counter A 11 for receiving reference oscillation frequency and dividing the frequency, a counter B 12 for receiving an output from the oscillator 15 and dividing the frequency of the received output, a reset signal generating circuit 18 for resetting both the counters A 11, B 12, a switch 17 for receiving an output from the circuit 18 and sending a signal to the counters A 11, B 12, a mode switching signal generating circuit 16 for generating a signal to control the opening/closing of the switch 17, and a phase comparator 13 for receiving the outputs of the counters A 11, B 12 and comparing their phases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer having a high frequency switching speed and little phase noise after switching.

[0002]

2. Description of the Related Art In a conventional frequency synthesizer, a frequency switching operation is performed by detecting a time-varying phase difference between a reference signal phase and a voltage-controlled oscillator phase, performing negative feedback control of the phase signal, and synchronizing the phases. I was going. The operation will be described below with reference to FIG.

The counter A11 receives a reference signal as an input and continuously changes its value, and the counter B12 outputs a voltage controlled oscillator 15
The value is continuously changed with the output of as input. The values of both counters correspond to the divided signal phase. Phase comparator 15
Outputs a signal proportional to the difference between the output signal phase of the counter A11 and the output signal phase of the counter B12, and this signal passes through the band limiting circuit 14 and is then input to the voltage controlled oscillator 15 as a control signal. The voltage controlled oscillator 15 outputs a signal based on the control signal, and this signal is supplied to the counter B12.
Entered in.

By repeating the above operation, the phases are synchronized and the frequency is switched at the same time. The feedback loop at this time constitutes a secondary PLL relating to the phase signal of the output of the voltage controlled oscillator.

In order to realize high-speed frequency pulling in such a circuit, it is necessary to widen the band of the band limiting circuit. However, in this case, there is a problem that the phase noise is deteriorated, and when used in a modulation circuit or the like, the transmission characteristics are deteriorated.

On the other hand, a circuit configuration improved for the purpose of high-speed frequency switching (for example, a circuit described in the 1992 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, 2nd volume, page 255) will be described with reference to FIG. The operation of this circuit will be described below.

The numerically controlled oscillator 31 sets a value by the channel setting and the output of the predictor 35 by using the reference signal as a clock, and the counter 32 sets the value by using the output of the voltage controlled oscillator 15 as an input. Numerically controlled oscillator 31 value and counter 3
The value of 2 is compared by the phase comparator 13, and the phase comparison output is D
After analog conversion by the A converter 33, it is input to the voltage controlled oscillator 15 through the band limiting circuit 14. After completion of the pull-in, the averaging circuit 34 averages the output of the phase comparator 13, and the predictor 35 outputs the frequency to be switched next by the voltage controlled oscillator 15 according to the output of the averaging circuit 34 and the next channel instruction. The predicted value of the numerically controlled oscillator 31 that generates the control signal is output. At the time of frequency switching, the input of the counter 32 is cut off and reset, and at the same time, the operation of the numerically controlled oscillator 31 is stopped and the predicted value is set in the numerically controlled oscillator 31 to preset the frequency in the band limiting circuit. . After that, the operation of the numerically controlled oscillator 31 and the input of the counter 31 are started, and the normal pull-in operation of the secondary PLL is performed.

In the case of the circuit shown in FIG. 3, the number of bits of the counter increases when it is attempted to obtain stability of ± 2 to 3 kHz with respect to a high frequency such as several GHz.
Further, if the voltage-frequency characteristics of the voltage controlled oscillator vary, it becomes difficult to preset with high accuracy.

As described above, in the conventional frequency synthesizer, it is difficult to stably realize low phase noise, high accuracy and high speed frequency switching under the condition that the voltage-frequency characteristics of the voltage controlled oscillator are allowed to vary. is there.

[0010]

A frequency synthesizer provided by the present invention as a means for solving the above-mentioned problems includes a circuit for generating a frequency control signal, a band limiting circuit for receiving the circuit output, and a band limiting circuit output. A first counter configured to receive a signal and output a signal to the frequency control signal generator, and a circuit for generating the frequency control signal, the first counter dividing the frequency by receiving the reference oscillation frequency; A second counter that receives the output of the oscillator to divide the frequency, a reset signal generating circuit for resetting the first counter and the second counter, and an output of the reset signal generating circuit that receives the first counter and the A switch for sending a signal to the second counter, a mode switching signal generating circuit for generating a signal for controlling opening / closing of the switch, and Phase comparison for receiving the output of the first counter and the output of the second counter, receiving the output of the first counter and the output of the second counter, and performing the phase comparison between the output of the first counter and the output of the second counter It is characterized by being composed of a container.

[0011]

The present invention uses the feedback circuit of the primary loop, which has an excellent transient response speed. By resetting the counter once for each phase comparison and aligning the phases of the counters, the phase difference after a certain period of time becomes proportional to the frequency.

When such an operation is performed, a first-order loop with respect to frequency can be constructed, and high-speed frequency pull-in becomes possible. At this time, there is a problem that the spectrum of the obtained signal spreads because the phase is not synchronized.However, after resetting the counter after stopping the frequency, the phase of the voltage controlled oscillator output that changes momentarily is used as the reference signal. A signal with high oscillation accuracy and high purity can be obtained by performing phase synchronization that follows the phase.

That is, ON / O for resetting the counter
By switching the frequency pull-in mode and the phase synchronization mode with the FF, high-speed, high-accuracy and low-phase-noise frequency switching can be realized simultaneously.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram for explaining the present invention.

The counter A11 receives the reference signal and changes its value, and the counter B12 receives the output of the voltage controlled oscillator 15 and changes its value.

The phase comparator 13 outputs a signal proportional to the difference between the value of the divided output signal of the counter A11 and the value of the divided output signal phase of the counter B12, and this signal stabilizes the circuit. After passing through the band limiting circuit 14 to be operated as described above, it is input as a control signal to the voltage controlled oscillator 15.

The voltage controlled oscillator 15 outputs a signal based on the control signal, and this signal is input to the counter B12.
This is the same operation as a normal synthesizer.

In the present invention, in order to switch the mode for pulling in the frequency at a high speed and the mode for performing the phase synchronization, the mode switching signal generating circuit 16 for outputting a control signal for switching and a switch for switching the mode by this control signal. 17 and a reset signal generation circuit 18 that outputs a signal for controlling the reset of the counter A11 and the counter B12 to realize the frequency pull-in mode.

For example, a circuit can be constructed by using a charge pump type phase comparator as the phase comparator 13, a normal frequency dividing counter as the counter A11 and the counter B12, and a low pass filter or a lag lead filter as the band limiting circuit 14.

When the frequency division number of the counter B12 is changed, the phases of the counter A11 and the counter B12 are deviated. As a result, the mode switching signal generation circuit 16 generates a signal for turning on the switch 17, and enters the frequency pull-in mode.

The reset signal generating circuit 18 includes a counter A.
After ΔT when the value of 11 becomes 2π, a reset signal is output, and this resets the counter A11 and the counter B12 via the switch 17. When the cycle of the reference signal is T, T + ΔT is longer than the latest cycle of the counter B output.

For example, in the case of digital cordless, the difference between the highest frequency and the lowest frequency is 3 of the lowest frequency.
%, The cycle of the reset signal (a) is set to about 1.05 times the cycle of the reference signal input to the counter A11.

The phase comparator 13 outputs a voltage proportional to the difference between the values of the counter A11 and the counter B12. The operations of the counter A11, the counter B12, and the phase comparator 13 at this time will be described with reference to FIG.

The counters A11 and B12 are reset at time 0 and start frequency division. Counter A after T
The reference pulse divided by 11 is output, and the counter B
From 12, pulse is output before and after time T according to the value of the counter. Since both counters are reset at time 0, the length of the phase comparison pulse corresponding to the time difference generated by both pulses is equal to the frequency difference at this time.

The phase comparison pulse (f) is supplied to the counter A11.
When the frequency of the signal input to the counter B12 is higher than the frequency of the signal input to the counter B12, a positive pulse that rises at the rising edge of the output pulse (c) of the counter A and falls at the rising edge of the output pulse (e) of the counter B Become.
When the frequency of the signal input to the counter A11 is lower than the frequency of the signal input to the counter B12, the output pulse (e) of the counter B falls at the rising edge and the output pulse of the counter A (c) rises at the rising edge. It becomes a negative pulse.

The value (g) of the control voltage increases when the phase comparison pulse (f) is positive and decreases when the phase comparison pulse (f) is negative. Since the length of the phase comparison pulse (f) is proportional to the frequency difference between the signal input to the counter A11 and the signal input to the counter B12, the phase is not synchronized and only the frequency is pulled. At this time, the band limiting element of the loop is only the band limiting circuit 14, and if this band limiting circuit 14 is a low-pass filter or a lag lead filter, this circuit will form a first-order loop with respect to frequency, and it will become faster. The frequency can be pulled in.

When the frequency difference between the signal input to the counter A11 and the signal input to the counter B12 becomes small,
Or when it becomes zero, the mode switching signal generation circuit 16
Generates a signal for turning off the switch 17, and shifts to the phase synchronization mode. This operation can be easily determined by observing the phase comparison pulse (f).

When shifting to the phase synchronization mode, the connection between the reset signal generating circuit 18 and the counters A11 and B12 is disconnected. Therefore, the reset operation of the counter A11 and the counter B12 is released, and the counter A1 and the counter B12 are released.
The difference between 1 and the frequency-divided output signal phase of the counter B12 continuously changes.

The phase comparator 13 outputs a voltage proportional to the phase difference of the outputs of the counter A11 and the counter B12, which changes with time. Counter A11 and counter B at this time
12 and the operation of the phase comparator 13 will be described with reference to FIG.

In the phase synchronization mode, since the relative difference between the value (b) of the counter A11 and the value (d) of the counter B12 continuously changes, it rises when the value (b) of the counter A11 becomes 2π. The difference between the rising time of the output pulse (c) of the counter A11 and the rising time of the output pulse (e) of the counter B12 that rises when the value (d) of the counter B12 becomes 2π is the counter A at the comparison time.
It is proportional to the instantaneous phase difference between the signal input to 11 and the signal input to the counter B12.

The phase comparison pulse (f) is supplied to the counter A11.
When the phase of the signal input to the counter B12 is earlier than that of the signal input to the counter B12, a positive pulse that rises at the rising edge of the output pulse (c) of the counter A and falls at the rising edge of the output pulse (e) of the counter B Become.

When the phase of the signal input to the counter A11 is later than that of the signal input to the counter B12, the output pulse (e) of the counter B rises and the output pulse (c) of the counter A falls. It becomes a negative pulse that rises at the rising edge.

The value (g) of the control voltage increases when the phase comparison pulse (f) is positive and decreases when the phase comparison pulse (f) is negative. Since the length of the phase comparison pulse (f) is proportional to the instantaneous phase difference between the signal input to the counter A11 and the signal input to the counter B12, the phases are synchronized while finely adjusting the frequency. At this time, this circuit constitutes a secondary loop, and stable operation and highly accurate signals can be obtained.

As described above, the counter is reset to ON.
By switching between the frequency pull-in mode and the phase pull-in mode when it is OFF, the primary loop and the secondary loop can be switched without switching the filter.

[0036]

As described above, the oscillation frequency of the voltage controlled oscillator is switched at high speed in the frequency pull-in mode, and then the mode is shifted to the phase-locked mode to improve the frequency accuracy and stability and reduce the phase noise. Is possible. Such a switching operation has an excellent effect that the speed of the transient response can be switched by pulling in without switching the loop filter.

Further, the reset operation of the counter constitutes a primary loop, the frequency is pulled in at a high speed, and thereafter the reset operation is released to constitute a secondary loop, and the phase-locked mode is entered. , Stable operation and high precision signal can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a frequency synthesizer proposed by the present invention.

FIG. 2 is a block diagram of a conventional frequency synthesizer.

FIG. 3 is a configuration diagram of a frequency synthesizer using a phase / frequency preset.

FIG. 4A is a counter reset pulse, FIG. 4B is a counter A11 value, and FIG. 4C is a counter A11.
FIG. 3 is a diagram showing an output pulse of (1), a value of the counter B12, (e) an output pulse of the counter B12, (f) a phase comparison pulse, and (g) a phase comparator output voltage.

[Explanation of symbols]

 11 Counter A 12 Counter B 13 Phase Comparator 14 Band Limiting Circuit 15 Voltage Control Oscillator 16 Mode Switching Signal Generation Circuit 17 Switch 18 Reset Signal Generation Circuit 31 Numerical Control Oscillator 32 Counter 33 DA Converter 34 Averaging Circuit 35 Predictor

Claims (3)

[Claims] 1. A frequency synthesizer for use in switching a transmission frequency in a satellite communication system using a TDMA / TDD (time division multiple access) system, a circuit for generating a frequency control signal, and a frequency band limitation of the frequency control signal. And a band limiting circuit that generates a band limiting frequency control signal, and a voltage controlled oscillator that outputs a frequency signal of a frequency corresponding to the voltage of the band limiting frequency control signal, wherein the frequency control signal generating circuit is It is composed of a reference oscillation frequency generation unit, a first counter, a second counter, a reset signal generation circuit, a switch, a mode switching signal generation circuit, and a phase comparator, and the reference oscillation frequency generation unit is a crystal oscillator or the like installed therein. To generate the reference frequency oscillation signal by self-excitation, and the first counter divides the reference frequency oscillation signal. The second counter divides the frequency signal, the reset signal generating circuit generates a reset signal for resetting the first counter and the second counter, and the mode switching signal generating circuit opens and closes the switch. A reset switch opening / closing control signal for controlling the reset switch opening / closing control signal, the switch sending the reset signal to the first counter and the second counter in response to the reset switch opening / closing control signal, and the phase comparator having the first Receiving the output of the counter and the output of the second counter, performing phase comparison between the output of the first counter and the output of the second counter, and generating the frequency control signal by a voltage signal based on the phase difference between the two. A characteristic frequency synthesizer. 2. The frequency synthesizer according to claim 1, wherein the band limiting circuit is composed of a low-pass filter. 3. The frequency synthesizer according to claim 2, wherein the band limiting circuit is composed of a lag lead filter.