JPH08274628A - Digital pll - Google Patents

Abstract

PURPOSE: To provide a digital PLL which can improve the integrating accuracy of the phase error value without setting a master clock at a high speed and also can improve the frequency accuracy of an output signal. CONSTITUTION: This digital PLL is provided with an n-stage sequential loop filter 4 which performs the integrating operations in different phases, a polyphase clock generation circuit 6 which gives the n-phase clock signals of different phases to the filter 4, an adder 5 which adds together (n) pieces of integration signals outputted from the filter 4 and gives these added signals to a variable frequency divider 8, and a selection circuit 13 which selects and outputs the optimum one of polyphase clocks supplied from the circuit 6. Then the divider 8 is controlled by the optimum clock outputted from the circuit 13. In such a constitution, an output signal is drawn at a high speed and the jitters can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL.

[0002]

2. Description of the Related Art A conventional digital PLL is shown in FIG. In the conventional digital PLL, the phase comparator 3 detects the phase error amount between the input signal applied to the input terminal 1 and the output signal output from the frequency divider 7 to the output terminal 2, and outputs the phase error signal. The sequential loop filter 4 counts and integrates the phase error signals to generate an integrated output. The variable frequency divider 8 changes the frequency division number for dividing the master clock generated by the oscillation circuit 9 based on the integrated output, and outputs the output signal so that the phase error between the input signal and the output signal becomes zero. Control the frequency and phase of.

[0003]

However, FIG. 5a and FIG.
If a phase error signal such as b is counted using the rising edge of the master clock of FIG. 5c, FIG.
As shown in FIG. 5, the count value is 4, and in FIG. 5b, the count value is 4, as shown in FIG. 5e, and FIGS. 5a and 5b have the same value.
Therefore, appropriate control cannot be performed according to the phase error amount. Therefore, there are problems that the pull-in time of the output signal is increased and that the output signal has jitter. When the master clock is set to a high speed (3 times as an example) as shown in FIG. 5d, the count value of FIG. 5a is A (hex) as shown in FIG. 5g, and the count value of FIG. 5b is E (hex) as shown in FIG. 5h. However, an error detection capability of several nsec is required as a digital PLL characteristic, and there is a problem such as element delay in controlling using a master clock that is several times as large.

Further, in a conventional digital PLL, an N-Before-M filter, a Random walk filter or the like is used as a sequential loop filter. When the frequency of the master clock output from the oscillator circuit 9 is fMS, the frequency division number of the variable frequency divider 8 is m0, and the frequency division number of the frequency divider 7 is n0, the frequency of the output signal output from the output terminal 2 is fO is given by equation (1).

Fo = fMS / (m0 × n0) (1) The frequency division number of the variable frequency divider 8 is m1 from time 0 to t, and the frequency division of the variable frequency divider 8 is from time t to T. Let the number be m2. The frequency divider 7 sets the master clock from 0 to t to m1.
The number of divided clocks k1 and the number of clocks k2 obtained by dividing the master clock from t to T by m2 are divided by n0 to obtain equation (2).

N0 = k1 + k2 (2) k1 and k2 are rewritten by (3) and (4), respectively.

K1 = t × fMS / m1 (3) k2 = (T−t) × fMS / m2 (4) Equation (3), (4) in Equation (2) Substitute an expression.

N0 = t × fMS / m1 + (T−t) × fMS / m2 (5) Equation (6) is obtained by obtaining the period T from Equation (5).

T = n0 × m2 / fMS + (1-m2 / m1) × t (6) Since the period T is the time until the sum of k1 and k2 reaches n0, the period of the output signal Is equal to Therefore, the output frequency f
o is the reciprocal of T and is given by equation (7).

FO = 1 / (n0 × m2 / fMS + (1-m2 / m1) × t) (7) However, since the variable frequency divider 8 is controlled by the master clock, the time t is ( 8) Master clock fMS
It can take only a value that is an integer multiple of the reciprocal of.

T = (1 · fMS) × l1 (8) However, l1 = 0, 1, 2, ... That is, the control step of the output frequency fO depends on fMS, and fO becomes high. In order to control with accuracy, it is necessary to increase the speed of fMS, but an error detection capability of several nsec is required as a digital PLL characteristic. Therefore, there is a problem such as element delay in controlling by using the master clock of several times that.

An object of the present invention is to realize a digital PLL which has a high integration accuracy of the phase error amount without increasing the speed of the mass stack lock. Or, a digital PL that improves the accuracy of the output frequency without increasing the speed of the mass lock.
Realize L. Alternatively, it is to realize a digital PLL in which the accuracy of integration of the phase error amount is improved and the accuracy of the output frequency is improved without increasing the speed of the mass stack lock.

[0013]

The above object can be achieved by the following means.

(Means 1) A phase comparison circuit for generating a phase difference signal in accordance with the phase difference between the input signal and the output signal, and the phase difference signal as an input signal, and the integrated signal counting and integrating the input signal is output. A sequential loop filter, a variable frequency divider that generates the variable frequency division signal by changing the frequency division number of the master clock according to the input signal and the input signal, and the variable frequency division signal as the input signal. , A digital PLL consisting of a divider that divides an input signal to generate an output signal
In, a multi-phase clock generation circuit is provided.

(Means 2) The digital PL according to the above means 1
In L, an n-stage sequential loop filter that integrates with clocks of different phases output from a multi-phase clock generator, and a multi-phase clock generator that supplies n-phase clock signals with different phases to the n-stage sequential loop filter It is characterized by comprising a circuit and an adder for adding n integrated signals output from the n-stage sequential loop filter and giving the sum to a variable frequency divider.

(Means 3) In the digital PLL described in the means 1 or 2, there is provided a selection circuit for selecting and outputting an optimum clock from the multiphase clocks output from the multiphase clock generation circuit, It is characterized in that the variable frequency divider is controlled by the optimum clock output from the selection circuit.

[0017]

EXAMPLES The present invention will be described in detail below based on examples. FIG. 1 is a diagram showing an embodiment of a digital PLL of the present invention. The input signal applied to the input terminal 1 is
The phase comparator 3 detects the phase error amount from the output signal output from the frequency divider 7 to the output terminal 2. The phase error output detected by the phase comparator 3 is applied to an n-stage sequential loop filter composed of the sequential loop filter 4. The sequential loop filter includes an N-Before-M filter and a Randa.
An m Walk filter or the like is used. The n-phase clocks having different phases generated by the multi-phase clock generation circuit 6 are applied to the sequential loop filter 4. The multi-phase clock generation circuit is composed of, for example, the delay circuit shown in FIG. The adder 5 adds the integrated results of the n-stage sequential loop filters. n =
If the number is 3, the clocks generated by the multi-phase clock generation circuit are the three-phase clocks of FIGS. 5i, 5l, and 5o. Figure 5
i, FIG. 5l, and FIG. 5o, the results of counting FIG. 5a and FIG. 5b by the sequential loop filter are FIG.
5k, 5m, 5n, 5p, and 5q. Adder 5
Let Ka be the counting result of FIG. 5a and Kb be the counting result of FIG.
It is expressed by equation (10).

Ka = Kj + Km + Kp (9) Kb = Kk + Kn + Kq (10) where Kj, Km, Kp, Kk, Kn, and Kq are shown in FIGS. 5j, 5m, and 5p, respectively. , FIG. 5k, FIG. 5n, and FIG. 5q.

When n = 3, the result of FIG.
Substituting into equation (10) yields equations (11) and (12).

Ka = 4 + 3 + 3 = 10 (A: hex) (11) Kb = 4 + 5 + 5 = 14 (E: hex) (12) Therefore, in the conventional example, the master clock is set to 3 The same counting result as when doubling is obtained. That is, the integration accuracy of the phase error amount can be improved without increasing the speed of the master clock.

FIG. 2 is a diagram showing another embodiment of the digital PLL of the present invention. The phase error amount between the input signal applied to the input terminal 1 and the output signal output from the frequency divider 7 to the output terminal 2 is detected by the phase comparator 3 and the phase error signal is output. The sequential loop filter 4 counts and integrates the phase error signals to generate an integrated output. The variable frequency divider 8 operates based on the integrated output so as to change the frequency division number for dividing the master clock generated by the oscillator circuit 9 so that the phase error between the input signal and the output signal becomes zero. . In the control of the frequency division number of the variable frequency divider 8, the multiphase clock generation circuit 6 receives the master clock as an input to generate clocks of different phases of i-phase, and selects a clock of the optimum phase according to the phase error amount 13 selects to control the variable frequency divider.

The multi-phase clock generation circuit 6 is composed of, for example, the delay circuit shown in FIG. For example, FIG. 7 shows an output waveform of the multi-phase clock generation circuit 6 when i = 5. It is assumed that only the rising edge of the clock is used to control the frequency division number of the variable frequency divider 8 and the time at which the frequency division number of the variable frequency divider 8 is controlled at the rising edge of FIG. Next, suppose that the frequency division number of the variable frequency divider 8 is controlled at the rising edge of FIG. 7e at time t1. If the frequency of the multi-phase clock in FIG. 7 is fMS, the time difference between the phases in FIG. 7 is (1/5) × (1 · fMS), and the time from the rise of FIG. 7a to the rise of FIG. 7e is (4/5 ) ×
(1 / fMS). When the number of rising edges in FIG. 7a included in t1 is I1, the time t1 is given by equation (13).

T1 = (1 / fMS) × (l1 + 4/5) (13) Generally, the time t wave when the variable frequency divider 8 is controlled by using the i-phase multiphase clock. Equation (14) is obtained.

T = (1 / fMS) × (l1 + l2 / i) (14) where l1 = 0, 1, 2, ... L2 = 1, 2, ..., i The frequency of the output signal by is expressed by the equation (7) and becomes the control time t (14). That is, the control time t is (1 / fM
It is possible to perform fine control in a time of 1 / i of the cycle of the master clock, which is represented by S) × (12 / i). That is, when the multi-phase clock is not used, the same control as the master clock increased by i times is possible.

FIG. 3 is a diagram showing another embodiment of the digital PLL of the present invention. In FIG. 3, the integrated output of the phase error amount is obtained by adding the integrated result of the n-stage sequential loop filter operating with the multiphase clock by the adder 5. Moreover, the variable frequency divider 8 is controlled by the clock of the optimum phase selected by the selection circuit 13 by the integrated output output from the adder 5.

That is, the integrated result is expressed by equations (11) and (12).
As shown in the equation, the same integration accuracy as when the master clock is increased by n times is obtained, and the frequency division number of the variable frequency divider 8 can be controlled at the time t shown in the equation (13). As for the output frequency, the same frequency accuracy as when the master clock is increased i times is obtained.

[0027]

According to the digital PLL of the present invention, the accuracy of phase error integration can be improved without increasing the speed of the master clock, and control can be performed according to the amount of phase error and the pull-in time of the output signal can be increased. And the jitter can be reduced. Alternatively, an output signal with high frequency accuracy can be obtained without increasing the master clock speed. Alternatively, it is possible to increase the accuracy of phase error integration without increasing the speed of the mass stack lock, it is possible to control according to the amount of phase error, it is possible to speed up the lead-in time of the output signal and reduce the jitter, and It is possible to obtain an output signal with high frequency accuracy.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a digital PLL of the present invention.

FIG. 2 is a diagram showing another embodiment of the digital PLL of the present invention.

FIG. 3 is a diagram showing another embodiment of the digital PLL of the present invention.

FIG. 4 is a diagram showing a conventional digital PLL.

FIG. 5 is a diagram showing an operation of a digital PLL.

FIG. 6 is a diagram showing an implementation of a multi-phase clock generation circuit.

FIG. 7 is a diagram showing an example of output waveforms of a multiphase clock generation circuit.

[Explanation of symbols]

 1 input terminal 2 output terminal 3 phase comparator 4 sequential loop filter 5 adder 6 multi-phase clock generation circuit 7 frequency divider 8 variable frequency divider 9 oscillator circuit 10 clock input terminal 11 delay circuit 12 multi-phase clock output terminal 13 selection circuit

Claims (3)

[Claims] 1. A phase comparison circuit for generating a phase difference signal in accordance with a phase difference between an input signal and an output signal, and a sequential loop for taking the phase difference signal as an input signal and counting and integrating the input signal to output an integrated signal. A filter, a variable frequency divider for generating the variable frequency division signal by changing the frequency division number of the master clock according to the input signal and the input signal, and the variable frequency division signal for the input signal In a digital PLL consisting of a frequency divider that divides a signal to generate an output signal,
A digital PLL comprising a multi-phase clock generation circuit. 2. The digital PLL according to claim 1, wherein
An n-stage sequential loop filter that integrates with clocks of different phases output from a polyphase clock generator,
A multi-phase clock generation circuit for applying n-phase clock signals having different phases to the n-stage sequential loop filter;
N output from the n-stage sequential loop filter
A digital PLL comprising: an adder for adding the integrated signals to give a variable frequency divider. 3. The digital P according to claim 1 or 2.
The LL includes a selection circuit that selects and outputs an optimum clock from the multiphase clocks output from the multiphase clock generation circuit, and controls the variable frequency divider with the optimum clock output from the selection circuit. A digital PLL characterized by the following.