JP2940220B2 - FSK modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK modulator, and more particularly to an FSK modulator used for high-speed data communication.

[0002]

2. Description of the Related Art A conventional FSK modulator is, as shown in FIG.
A reference oscillator 1 that oscillates a reference signal of 10.5MH _Z, the 1
A first fixed frequency divider 2, a phase comparison frequency of 50KH _Z with the reference signal and the peripheral 210 min 0.5 MH _Z, a voltage controlled oscillator (VCO) 3 for outputting a signal 20MH _Z bands, this voltage controlled oscillator first mixer 4 3 and output by mixing the reference signal of the 10.5MH _Z outputs frequency (9MH _Z band) of the difference
If a variable frequency divider 5 to output a phase comparison frequency of the first frequency division number is determined the output by the data 13 of the mixer 4 (199 or 181) by the division to 50KH _Z, the fixed frequency divider a phase comparator 6 for comparing the 50KH _Z of the signal output from the 2 and the output of the voltage controlled oscillator 3 for dividing the 50KH _Z phase, the voltage output peripheral 100 minutes 20MH _Z zone controlled oscillator 3 2nd fixed divider 7 to make 200KHz _Z band
And the output of the second fixed frequency divider 7 and the reference signal are mixed to obtain 10.7
A second mixer 8, MH _Z, is composed of a filter 9 to remove the unwanted frequency components. The oscillation frequency of the voltage controlled oscillator 3 is controlled by the output of the phase comparator 6.

In this configuration, when the data 13 is a space, the variable frequency divider 5 performs frequency division by 199. Therefore 20MH
Output f _vco of the voltage controlled oscillator 3 and _Z zone is controlled such that the _{(f VCO -10.5MH Z) ÷ 199} = 50KH Z ∴f vco = 20.45MH Z. After the output of the voltage controlled oscillator 3 on the one hand that is peripheral 100 minutes in the second fixed frequency divider 7, 10.5MH _Z
The reference signal and the mixing in the second mixer 8, the output frequency is 10704.5KH _Z. When data 13 marks, the variable frequency divider 5 from performing peripheral 181 minutes, f _{vco is, (f vco -10.5MH Z) ÷} 181 = 50KH Z ∴f vco = 19.55MH Z , and the output frequency 10695.5MH _Z is obtained. That is, this FSK modulator constitutes a PLL circuit, and data 1
By changing the number of divisions by 3, different frequencies are output.

[0004]

In this conventional FSK modulator, the phase of the phase comparison frequency input to the phase comparator 6 is irrelevant to the data. However, a digital phase comparator often used in a PLL circuit detects edges of two input waveforms to determine a phase. Therefore, a variation (jitter) occurs in the time from when the input data changes to when the output of the modulator changes.

FIG. 4 shows an example of a timing chart. This chart shows the case where the phase comparator compares the phases at the rising edge of the input data.
4 is a change timing of the input data, and T21 to T24 are change timings of the output data corresponding thereto, and the respective time differences are delays of the modulation. Thus, when the input data changes immediately after the rising of the phase comparison frequency, the modulation delay is large, and when the input data changes immediately before the rising, the delay is small. Therefore, one cycle time of the phase comparison frequency becomes data jitter. By the way, in the example shown in FIG.
The longest time from the data change to the start of the voltage controlled oscillator 3 change is 20 μsec, and the shortest time is 0 μs.
Since this is μsec, the jitter is 20 μsec. An object of the present invention is to provide an FSK modulator in which such a jitter is eliminated.

[0006]

SUMMARY OF THE INVENTION An FSK modulator according to the present invention comprises a reference oscillator for producing a stable reference signal, a first fixed frequency divider for dividing the reference signal, a voltage controlled oscillator, and a voltage controlled oscillator. A variable frequency divider that divides the output of the oscillator by a number determined according to the state of the input data, and compares the phases of the output of the first fixed frequency divider and the output of the variable frequency divider. said voltage controlled oscillator and a phase comparator for controlling said first fixed frequency divider and the variable divider and edge of the input data Te
And an edge detector for detecting an edge and resetting when the state of the input data changes. In this case, a first mixer that mixes the output of the voltage controlled oscillator with a reference signal, converts the frequency, and inputs the resulting signal to the variable frequency divider, a second fixed frequency divider that divides the output of the voltage controlled oscillator, 2 The frequency conversion is performed by mixing the output of the fixed frequency divider with the reference signal.
It is possible to include a mixer and a filter for removing unnecessary frequency components in the signal output from the second mixer .

[0007]

According to the present invention, when the input data changes, the first fixed frequency divider and the variable frequency divider are reset by the edge detector to follow the change of the input data. Reduce the required delay variation.

[0008]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The same reference numerals are given to the same parts as those of the conventional configuration shown in FIG.
That is, 1 is a reference oscillator that outputs a 10.5 MHz reference signal, 2 is a first fixed frequency divider that performs 1/210 frequency division, and 3 is a 20M frequency divider.
Hz band voltage controlled oscillator, 4 is a first mixer, 5 is a variable frequency divider having a frequency division number of 199 or 181, 6 is a phase comparator, 7 is 1 /
A second fixed frequency divider for dividing the frequency by 100, 8 is a second mixer, 9
Is a filter. Further, in this configuration, there is provided an edge detector 10 for detecting a change in the data 13, that is, an edge of the signal, and resetting the first fixed frequency divider 2 and the variable frequency divider 5. 11 is an output terminal of the first fixed frequency divider 2,
12 is an output terminal of the variable frequency divider 5, and 14 is an output terminal.

In this configuration, the voltage controlled oscillator 3
The output of the MH _Z band 1 from the reference oscillator 1 in the first mixer 4
Is mixed with a reference signal of 0.5 MH _Z becomes 9MH _Z band, it is inputted to the variable frequency divider 5. Variable frequency divider 5 is 181/199 divides in accordance with the inputted signal to the mark / space data 13, and outputs the 50KH _Z. When the data 13 changes, it is reset by the edge detector 10. The first fixed frequency divider 2 is to output a 50KH _Z with 210 divides the reference signal 10.5MH _Z, by the edge detector 10 when the first fixed frequency divider 2 is also the data 13 is changed Reset. On the other hand, the output of the voltage controlled oscillator 3, after being 100 divided by the second fixed frequency divider 7, a 10.7MH _Z is mixed with the reference signal in the second mixer 8. Thereafter, the signal passes through the filter 9 to remove unnecessary frequency components, and is then output to the output terminal 14. The phase comparator 6 compares the output of the variable frequency divider 5 with the first
The phase of the fixed frequency divider 2 is compared, and the oscillation frequency of the voltage controlled oscillator 3 is controlled.

[0010] Here, when the frequency of the voltage controlled oscillator 3 20MH _Z band and f _VCO, when the data 13 _{marks, (f VCO -10.5MH Z) ÷} 181 = 50KH Z become so f _VCO = 19.55 MH _Z. At this time, the output frequency f _out is f _out = (f _VCO ) ÷ 100 + 10.5 MHz _Z = 1
The 0.695MH _Z. Similarly, when data 13 is _{space, (f VCO -10.5MH Z) ÷} 199 = 50KH Z ∴f VCO = 20.45MH Z f out = (f VCO) ÷ 100 + 10.5MH Z = 10.7045MH Z , and the mark , 10.7MH _Z ± 4.5K depending on the space
The output signal of the H _Z is obtained.

FIG. 2 is a timing chart showing the operation when data changes in this configuration. As can be seen from the figure, since the first fixed frequency divider 2 is reset at the change point of the input data, the frequency-divided signal rises after a certain time from the change of the input data. Similarly, since the variable frequency divider 5 is also reset at the change point of the input data, this signal also rises approximately a fixed time after the change of the input data (it changes slightly due to modulation). Since the phase comparator 6 compares the rising phases of both waveforms, as a result, the waveforms of the respective signals following the change of the input data are compared, and the delay amount of the modulator becomes substantially constant. That is, T11 to T14 in FIG. 11 indicate the change timing of the input data, and T21 to T24 indicate the change timing of the output data, and the respective delays are substantially constant. In this connection, in the example shown in FIG. 1, the data is changed to the change of the voltage controlled oscillator 3 starts, long time 10μsec (1 / 50KH in T12~T22 _Z ÷
2) If it is short, 9.1 µsec at T11 to T21 (181 ÷
(20.45-10.5) MH _Z ÷ 2), and the jitter 0.9μ
sec.

[0012]

As described above, according to the present invention, the first fixed frequency divider for dividing the output of the reference oscillator and the variable frequency divider for dividing the output of the voltage controlled oscillator have different input data states. An edge detector that resets when the input data changes; when an edge of the input data is detected and the state of the input data changes, each output of the first fixed frequency divider and the variable frequency divider outputs the input data. FSK that follows a change in the state and reduces the variation in the amount of delay to reduce jitter
There is an effect that a modulator can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of an FSK modulator according to the present invention.

FIG. 2 is a timing chart of main signals in FIG.

FIG. 3 is a block diagram illustrating an example of a conventional FSK modulator.

FIG. 4 is a timing chart of main signals in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reference oscillator 2 first fixed divider 3 voltage-controlled oscillator 4 first mixer 5 variable divider 6 phase comparator 7 second fixed divider 8 second mixer 9 filter 10 edge detector 13 data

Claims (2)

(57) [Claims] A reference oscillator for producing a stable reference signal;
A first fixed frequency divider for dividing the reference signal, a voltage-controlled oscillator, a variable frequency divider for dividing the output of the voltage-controlled oscillator by a number determined according to the state of input data,
A phase comparator for controlling the voltage controlled oscillator by comparing the phase of the output of the first fixed frequency divider with the output of the variable frequency divider; and the first fixed frequency divider and the variable frequency divider. An FSK modulator comprising: an edge detector that detects an edge of the input data and resets when the state of the input data changes. 2. A first mixer which mixes an output of the voltage controlled oscillator with a reference signal, converts the frequency and inputs the frequency converted signal to the variable frequency divider, and a second fixed frequency divider which divides the output of the voltage controlled oscillator. a vessel, a second mixer for frequency converting the output of the second fixed frequency divider is mixed with a reference signal, the second Mi
2. The FSK modulator according to claim 1, further comprising: a filter for removing unnecessary frequency components in a signal output from the mixer.