JPS6327477Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a frequency synthesizer used in a tuning circuit of an FM receiver.

Conventionally, there are various frequency synthesizers that use variable frequency dividers, but all of them have complicated configurations, require a wide pull-in range, tend to have a poor signal-to-noise ratio, and have a tendency to use variable capacitors instead of voltage-controlled oscillators (VCOs). Therefore, in the method of forcibly varying the frequency and sampling the frequency output, there is a risk of skipping to an adjacent channel unless the drift characteristics of the VCO itself are suppressed, which poses a problem when used in a narrow channel space. Ta.

In view of the above problems, this invention provides a frequency synthesizer that can subdivide a channel space with a relatively simple configuration.

Embodiments of this invention will be described below with reference to the drawings.

Figure 1 shows the circuit configuration, and Figure 2 shows an example of 25
12 shows each waveform diagram when obtaining a frequency division ratio of . In the figure, 1 is a reference oscillator such as a crystal, 2 is a pulse shaping circuit, and 3 is a predetermined frequency division ratio, for example 1 bit.
(1/2), a variable frequency divider with about 2 bits (1/4) or 4 bits (1/10), 4 is a phase comparator, 5 is an amplifier,
6 is a frequency minute value setter, 7 is a voltage controlled oscillator (hereinafter referred to as VCO), and 8 is a voltage setter.

In Figure 2, A is the reference frequency, B and C are the output waveforms of the pulse shaping circuit 2, respectively, and outputs for varying the sampling frequency and division ratio, and D is the VCO.
The output and E indicate the frequency-divided output.

The operation of the above configuration will be explained next. The VCO 7 obtains a predetermined oscillation frequency by the voltage setter 8 and inputs it to the variable frequency divider 3. The variable frequency divider 3 divides the frequency of the VCO output D, and this frequency division ratio is set to a different value depending on the level of the output C for varying the frequency division ratio. In other words, if the output for variable frequency division ratio is low (L), the variable frequency divider 3 will change to the original frequency division ratio (for example, 1/
10), but when the output C for changing the frequency division ratio is high (H), the frequency is divided by the value set by the frequency minimum value setter 6. For example, this can be achieved by gating the preset signal of a presettable counter, which is often used as a variable frequency divider, with the output signal for varying the frequency division ratio.
Therefore, when the output of the frequency minimum value setter 6 is "5", the output of the variable frequency divider 3 for variable division ratio is 1/10 at low (L) and 1 at high (H). The division ratio is /5.
In this way, the variable frequency divider 3 divides the output of the VCO 7 at a division ratio of 1/10 (assumed), and
The frequency is divided by the frequency division ratio variable output C at a rate set by the frequency minimum value setter 6 (for example, 1/5) at a rate of once per cycle of the reference frequency. It is assumed that it operates at 1/10 of the original cycle. The phase comparator 4 compares the phase of the other signal at the moment when the signal with a longer period changes its potential even if the frequencies of the two input terminals are different. It is an anti-coincidence circuit (EX-OR). This is the median value when the other input signal (divided output E) rises (or falls) at exactly the middle timing of the pulse of one reference input signal (sampling frequency B); When the phase of (divided output E) advances, the comparison output is passed through a low-pass filter (LPF).
The output potential increases (or decreases) as the integrated potential, and vice versa if there is a delay. Therefore, when the frequency of the divided output E is increased, it becomes the median value for every integer multiple of the frequency of the sampling frequency B (reference frequency A).

Now, if the VCO output is A, it is normally divided by 1/10 to become a divided output of A x 1/10, and if the period is set by the output for variable division ratio, for example 1/5. , the frequency is divided by a combination of A/10 and A/10×1/5. As an example, the sampling frequency is 83
If sampling is performed one by one, a frequency division ratio of 1/1/10 + 1/1/5 x (83-1) = 825 will be obtained.

Therefore, even if the frequency of the output H of the variable frequency divider 3 is lower than the frequency of the output L of the pulse shaping circuit 2, the sampling lock period can be made wider than the frequency interval of the channel plan, and at the same time, the VCO design becomes easier because the allowable range of drift characteristics is widened. Although the frequency setting of the VCO is controlled by voltage, a variable capacitor may also be used for this purpose. Also, even if the lock loop is released, the oscillator continues its oscillation operation, so in automatic tuning, after detecting tuning by performing a voltage sweep, you can read the frequency and use it as the variable frequency divider setting value. Sweeping can be performed regardless of the response time of , and the sweep speed can be increased.

As mentioned above, according to this invention, the channel space can be subdivided with a relatively simple configuration, there is no need to increase the loop gain due to the sampling lock, and the signal-to-noise ratio is also advantageous. Also, it does not require much space and is advantageous in terms of cost.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a waveform diagram of each output. In the figure 1... Reference oscillator, 2... Pulse shaping circuit, 3... Variable frequency divider, 4... Phase comparator, 7...
...VCO, 8... Voltage setting device.

Claims (1)

[Scope of utility model registration request] The oscillation output of the voltage controlled oscillator is divided by two predetermined frequency division ratios using a variable frequency divider, and the phase comparison is performed using the frequency division output and the sampling frequency of the reference oscillator in an integer multiple relationship. Therefore, the oscillation output is controlled, and the frequency division period of the variable frequency divider is changed by two predetermined frequency division ratios in synchronization with the period of the reference frequency from the reference oscillator. frequency synthesizer.