JPH028438Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to a radio receiver that uses a phase-locked loop (PLL) as a local oscillation circuit to perform automatic sweeping. Regarding the constructed radio receiver.

A radio receiver that uses a PLL for its local oscillation circuit is generally configured as shown in Figure 1, and the PLL
By changing the frequency division ratio of the programmable frequency divider 2 constituting the oscillator 1, a local oscillation frequency that is twice the reference frequency of the reference frequency oscillator 4 is generated from the voltage controlled oscillator 3, and channel selection is performed. A voltage variable capacitance element is used in the voltage controlled oscillator 3, and the capacitance is changed according to the output voltage from the low-pass filter 5 to control the oscillation frequency.The characteristics of the voltage variable capacitance element are shown in Fig. 2. As shown in the figure, since the frequency change with respect to the applied voltage is small at the low frequency point A and the high frequency point C, the frequency change from the time the division ratio of the programmable frequency divider 2 is changed until the corresponding local oscillation frequency is obtained. , that is, the lock time of PLL1 is longer than in the straight section B.

By the way, as a method of performing automatic sweeping with such a PLL 1, a frequency division ratio setting counter 6 for setting the frequency division ratio of the programmable frequency divider 2 and a sweep pulse generation circuit 7 are provided, and the frequency division ratio setting counter 6 sweeps. By sequentially counting pulses, the local oscillation frequency is changed and swept by changing the division ratio of the programmable frequency divider 2, and when the pulses are received and an output is generated from the reception detection circuit 8, the sweep pulse generation circuit 7
The device is configured to stop pulse generation and maintain the reception state.

At this time, the pulse generation period of the sweep pulse generation circuit 7 is determined by changing the frequency division ratio of the programmable frequency divider 2, taking into consideration the characteristics of the voltage variable capacitance element described above, as shown in FIG. The PLL1 lock time until the oscillation frequency is obtained is based on the lock time T' at the low and high frequency points where the lock time is longest, and furthermore, the next pulse is generated while the lock is not locked, thereby preventing the station from being skipped. In order to prevent this, the time T is set by adding the margin time ΔT in consideration of the variation in the characteristics of the voltage variable capacitance element, so even in the straight line section B where the sweep speed is constant but the lock time is short, the same This has the disadvantage that it takes T time and the sweep time becomes longer.

Therefore, as a method of shortening the sweep time, a method as shown in FIG. 4 has been implemented in which the cycle of pulse generation is controlled by lock detection of the PLL 1. i.e. PLL
A lock detector 9 is provided to detect when the lock is locked, and if there is no received signal when the lock is detected, the next sweep pulse is generated. According to this, it is necessary to consider the margin time ΔT as shown in Figure 3. However, due to the characteristics of the voltage variable capacitance element, the lock time of PLL1 is not constant, so the sweep speed is not constant, especially at low and high frequencies. In some cases, the drawback was that it gave the operator a strange feeling when the sweep speed was slow.

SUMMARY OF THE INVENTION Accordingly, the present invention has been devised to overcome the above-mentioned drawbacks, and provides a radio receiver configured to shorten the sweep time while keeping the sweep speed constant.

An embodiment of the present invention will be described below with reference to FIG.
Components that are the same as those in FIG. 4 are indicated by the same drawing numbers, and explanations thereof will be omitted.

In this case, the output of the pulse generator 7 and the output of the lock detection circuit 9 are input to the division ratio setting counter 6 via the AND gate 10, and the pulse generation period of the pulse generator 7 is the longest PLL1.
The period is set to be slightly longer than the lock time T'. Therefore, when the frequency division ratio setting counter 6 counts pulses and the frequency division ratio of the programmable frequency divider 2 is changed, the output of the low-pass filter 5 becomes the sixth
As shown in the figure, it goes through a transient response and reaches a predetermined value.
After time T' has elapsed, the lock detection circuit 9 detects the PLL.
When a lock of 1 is detected, one input of the AND gate 10 is set to H level, and the sweep pulse generated a little later than the lock detection is input to the division ratio setting counter 6, and the frequency is divided. ratio to 1
only increases. In this manner, the sweep pulse generator 7 generates sweep pulses at a constant cycle and sweeps are performed until the reception detection signal is generated. At this time, if the PLL 1 is not yet locked when the sweep pulse is generated, the AND gate 10 is closed and the pulse is not input to the division ratio setting counter 6.
Furthermore, it waits for one cycle until the next sweep pulse is generated. Therefore, for example, at low and high frequencies, the PLL may be lower than the set sweep pulse generation period.
Even if the lock time of 1 becomes longer, reception can be performed reliably. Thus, in this case, the sweep time is longer than the method controlled only by lock detection shown in Fig. 4, but since there is no need to provide the margin time ΔT as in the case of Fig. 1, the sweep time is longer than in the case of Fig. 1. Sweep time is reduced. Furthermore, in the present invention, since the sweep pulses are generated at a constant period, the sweep speed is also constant.

As mentioned above, the radio receiver of the present invention is configured so that the sweep pulse generation period corresponds to the longest lock time of the PLL and also performs lock detection at the same time. It is no longer necessary to provide a margin time to account for variations in the characteristics of the voltage variable capacitance element, which shortens the sweep time, and the sweep can be performed at a constant speed, eliminating any strange sensations experienced by the operator. , which has extremely great practical effects.

[Brief explanation of the drawing]

Figure 1 shows a conventional example of a radio receiver, Figure 2 shows a conventional example of a radio receiver.
Figure 3 shows the characteristics of the voltage variable capacitance element, Figure 3 shows the waveforms of the main parts of Figure 1, Figure 4 shows another conventional example of a radio receiver, and Figure 5 shows the characteristics of the present invention. A diagram showing the configuration of a radio receiver, and FIG. 6 is a diagram showing waveforms of the main part of FIG. 5. 1...PLL, 2...Programmable frequency divider,
3... Voltage controlled oscillator, 6... Counter for frequency division ratio setting, 7... Sweep pulse generation circuit, 8... Reception detection circuit, 9... Lock detection circuit.

Claims (1)

[Scope of utility model registration request] In a radio receiver whose local oscillation circuit is configured with a PLL and which performs sweeping by changing the division ratio of a programmable frequency divider of the PLL, means for detecting whether or not it is in a receiving state; means for generating a signal for changing the division ratio of a programmable frequency divider at a period approximately equal to the longest lock time;
means for detecting that the programmable frequency divider is locked, and changing the frequency division ratio of the programmable frequency divider by detecting coincidence between the outputs of the lock detection means and the frequency division ratio change signal generation means, and detecting reception by the reception detection means. and means for stopping changes in the division ratio of the programmable frequency divider.