JPS6084016A - Pll circuit - Google Patents

Abstract

PURPOSE:To attain high speed response and also to realize high stability by decreasing substantially the period controlling the oscillation of a voltage controlled oscillator (VCO) in a loop so as to reduce a dead time of the loop. CONSTITUTION:An external input rectangular wave signal (a) is impressed to a monostable multivibrator MM13 from a terminal 5 and the MM13 applies a pulse (b) having a pulse width TW to a phase comparator PD12. When an output of the MM13 is at high level, the PD12 outputs a high level VH or a low level VL, and when the output of the MM13 is at low level, the PD12 outputs an intermediate level VM. When the output of a frequency divider 4 is at high level, the PD12 outputs the VL at the period of the TW and the PD12 outputs the VH at the low level. If there is a difference between the phase of the output signal of the frequency divider 4 and the phase of an externally inputted rectangular wave signal, the ratio of a period TH when the PD12 outputs the VH to a period TL when the PD12 outputs the VL is changed in the TW and the phase of the output signal of the frequency divider 4 is controlled so that the phase difference is made coincident. The output of the PD12 is the VM at the period other than the TW, and the VCO3 is brought substantially into the free running state.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an improvement in a phase-locked loop, such as a 1n IPLL circuit, for obtaining an oscillation output that is phase-locked with an input signal.

<Description of Prior Art> Conventionally, analog type PLL circuits and digital type PLL circuits have been frequently used in various devices, but these conventionally used PLL circuits have low L% and high-speed response. However, it was unsuitable for specific applications requiring high stability. This point will be explained in detail below using the drawings.

FIG. 1 is a diagram showing a general configuration of a conventional PLL circuit. In Figure 1, 1 is the phase comparator (PD), %2 is P
Low-pass filter as a loop filter for LL circuit (
3 is a voltage controlled oscillator (VCO), 4 is an h frequency divider, and 5 is a terminal to which an input signal is supplied. The phase comparator 1 is generally classified into analog type and digital type, and PLL circuits are accordingly classified into analog PLL circuits and digital PLL circuits.

First, a conventional analog PLL circuit will be explained. FIG. 2 is a diagram showing a main part configuration of an example of a conventional analog PLL circuit. In the figure, 6 is a waveform shaping circuit, 7 is a multiplication circuit, and these constitute a phase comparator. Referring to FIG. 1, OVa, which constitutes the phase comparator 1 at 6.7, is an LPF υ and corresponds to LPF2 in FIG. Further, 8 is a terminal to which a rectangular wave for phase comparison as the output of the h frequency divider shown in FIG. 1 is supplied, and 9 corresponds to terminal 5 in FIG. This is a terminal to which a wave signal (for example, a horizontal synchronizing signal of a television signal) is input as a narrow pulse with a duty of 50 or less. 10 is an output terminal s that supplies an output signal to the VCO 3 shown in FIG. 1; VCC is a terminal to which a power supply voltage is applied;
VB is a terminal to which a bias voltage is applied.

FIG. 3 is a timing chart showing the waveforms of each part of FIGS. 2(a) to (e). The operation of the circuit shown in FIG. 2 will be described below. The phase comparison rectangular wave (a) inputted to the input terminal 8 from the h frequency divider 4 is converted into a sawtooth wave (b) by the waveform shaping circuit 6 composed of RC passive elements, and then multiplied. Supplied to Kibishi. On the other hand, the input terminal 9 is supplied with the above-mentioned externally input cuff rectangular wave signal (c), and a part of the above-mentioned sawtooth wave (b) is converted into the externally input rectangular wave signal ( e) is extracted by (d).

This extracted signal (d) is passed through the LPF 2a as a loop filter consisting of R and C to the external input signal (c).
) and the phase comparison rectangular wave (a).
When the oscillation phase of O3 is delayed, the oscillation frequency of VCO3 is controlled to increase, and when it is advanced, the oscillation frequency is controlled to decrease. Therefore, the VCO 3 is always controlled in a direction that reduces the phase error and is phase locked.

Now, in the analog PLL circuit as described above, the VCO is controlled over the entire period, but since the phase shift is detected at a predetermined period, the information on the phase shift is
It takes a certain amount of time for it to be reflected in the CO control. This means that the response speed of the LPF2a is
This means that the response speed of the entire circuit is determined, and the response of the LPF 2a becomes an obstacle in constructing a high-speed response PLL circuit.

That is, for example, if the frequency of the external input rectangular wave signal is 15.73
Assuming 4KHz (horizontal synchronization frequency of television signal), LPF2a is 15.734K of the output of multiplier 7.
Since it is necessary to sufficiently remove the Hz component and its related components, the cutoff frequency must normally be set to several hundred Hz. This caused difficulty in achieving high-speed response.

In this type of analog PLL circuit, it is possible to attenuate the frequency component of the external input square wave signal by sampling and holding the output of the multiplier 7, but in this case as well, the frequency of the signal is Then, Vlft degree (63.556μ5e when f = 15.734KHz)
c), so a significant improvement in response could not be expected due to the accompanying deterioration of frequency characteristics.

Furthermore, when considering stability, stability is impaired by phase lag associated with LPF and sample hold.

Next, a conventional digital PLL circuit will be explained. FIG. 4 is a diagram showing an example of the configuration of a conventional digital PLL circuit. Components in FIG. 4 that are similar to those in FIG. 1 are given the same numbers. 11 is an AND gate, and 2b is an LPF corresponding to LPF 2 in FIG. Figure 5 (5)
, (13L (c) is a timing chart showing the waveforms of each part in FIGS. 4(a) to (d).The operation will be explained below.

FIG. 5(2) shows a state in which the PLL circuit shown in FIG. 4 is phase-locked. output(
This shows the state when the phase of b) is advanced. As is clear from the figure, when the phase of the output signal of the branch divider 4 advances, that is, when the phase of the output signal of the VCO 3
When the phase of the oscillated signal advances, the pulse width of the output pulse (C) of the AND gate 11 becomes narrower than when the phase is locked, and the control voltage (d) supplied to the VCO 3 becomes lower.

Therefore, the oscillation frequency of the VCO 3 becomes low and the phase of the signal oscillated by the VCO 3 is delayed. As a result, the phase lock state as shown at the beginning of the fifth time is drawn.

FIG. 5(C) shows a state when the phase of the output signal (b) of the branching device 4 is advanced compared to the external input rectangular wave signal (a).

In this case, as is clear from the figure, when the phase of the output signal (b) of the frequency divider 4 advances, the pulse width of the output pulse (c) of the AND gate 11 is wider than when the phase is locked, and the pulse width is supplied to fiVcO3. The controlled voltage (d) increases. Therefore, the oscillation frequency of the VCO 3 also increases, and the phase of the signal oscillated by the VCO 3 advances, leading to a phase locked state.

In the digital PLL circuit described above, since the VCO is controlled throughout the entire period, a smoothing means such as an LPF must be used, resulting in a response delay similar to the analog PLL circuit described above. However, it was extremely difficult to construct a PLL circuit with high-speed response.

Also, what about this delayed response? The stability of the PLL circuit was also impaired.

<Objective of the Invention> The present invention provides a PLL circuit that is capable of high-speed response and has high stability by eliminating problems related to high-speed response and high stability in conventional PLL circuits such as dual-connected ones. The purpose is to

Description of Examples> The present invention will be explained in detail below using examples.

FIG. 6 is a block diagram showing the configuration of a PLL circuit as an embodiment of the present invention. In FIG. 6, 3 is VCo,
4 is a frequency divider, 5 is a terminal into which an external input rectangular wave signal is input, and 12 is a high level, low level, and intermediate level 3.
The PD 13 that can output levels is a mono multivibrator (MM). Figure 7 (4), 03), (C)
FIGS. 6(a) to 6(d) are timing charts showing waveforms of each part, and the operation will be explained below.

The external input square wave signal (a) is input through terminal 5, and MM
The pulse width of o M M 13 applied to 13 is Tw (
The pulse (b) shown in FIG. 7 is supplied to the PDI 2. P.D.
As the other input of I2, the output (c) of the frequency divider 4 which has counted down the oscillation output of the VCo3 to h is inputted as a comparison signal, and the phase comparison is performed here.

Here, the operation of PDI2 will be explained.0PD12 is M
Only when the output of M13 is at the no-y level, it becomes the no-y level (Vu shown in the seventh figure) or the low level (VL shown in the seventh figure).
), and when the output of MM13 is low level, it outputs the first intermediate level (VM shown in FIG. 7). Also, MM1
When the output of the divider 4 is at a high level, that is, during the period Tw, when the output of the branching device 4 is at a no-y level, the PD 12 outputs Vt, and when it is at a low level, the PD 12 outputs V[.

The output (d) of PDI2 is sent directly to vcoa,
3 is PDI2 (7) 3 types of output v −< /l/ ML
, VMIVu, respectively, oscillate three types of frequencies: F't and FMI FH. The oscillation output is h frequency divider 4
After being frequency-divided here, it is supplied to the comparison input terminal of PDI2, forming a closed loop.

Now, if for some reason the phase of the output signal of the frequency divider 4 is delayed compared to the phase of the external input rectangular wave I, the PDI within the above-mentioned period Tw as shown in Fig. 7 CB).
The period during which the circuit 2 outputs Vi (indicated by T in the figure) is longer than the period during which it outputs VL (indicated by Tt in the figure). Therefore, the period during which the VCO 3 oscillates at the oscillation frequency Fn becomes longer than the period during which it oscillates at the oscillation frequency Ft. Therefore, the output signal of the frequency divider 4 is controlled to advance in phase.

On the other hand, if the phase of the output signal of the frequency divider 4 is delayed compared to the phase of the external input rectangular wave signal, as shown in FIG.
Within Tw, Tt becomes longer than TI, and the period in which VCo3 oscillates at FL becomes longer than the period during which it oscillates at Fn. Therefore, in this case, control is performed so that the phase of the output signal of the frequency divider 4 is delayed.

In periods other than Tw, the output of PDI 2 is V
M, and the oscillation frequency of the VCo3 is FM. Frequency divider 4 is an h frequency divider, which divides the frequency of the external input rectangular wave signal into F
If R, then Fw is selected to be nFi. Therefore T
During periods other than w, the VCo3 essentially free runs and is not controlled. Also, of course Fo
It is higher than FM < Ft is a frequency lower than FM.

Due to the above-mentioned effect? When the PLL circuit enters a phase-locked state, as shown at the beginning of Part 7, a multi-phase locked state is maintained where, for example, both TFI and Tt are "/2 Tw.As described above, the ratio of TH and Tt (however, TH+TL= A negative feedback PLL is configured by the control of Tw).

Below, the operation of the above-mentioned PLL circuit will be analyzed.

Now, if the voltage-frequency characteristic of VCO3 is F=kV (1), then it becomes. Also, the output signal level of PD12 is vH9Vt,
If the period of the output signal oscillated by the VCO 3 when in VM is τH9τL and τM, then the period corresponding to the generation period of the external input rectangular wave signal is To (shown in Figure 7).
, TM is the period during which the output signal level of PD12 is VM, and when the PLL circuit is phase-locked, Tn, T
The number of pulses generated by vcoa at t and Ty is 1.
If h and m, then TH=TL=Tw/2 when the PLL circuit is phase-locked. However, t+h+m=n (5).

The PLL circuit is out of phase lock, and the frequency divider 4
Let t', h', and rn' be the number of pulses generated by the VCO 3 at To, Tt, and TM, respectively, when the phase of the output signal advances by mt from the phase lock position. On the other hand, the period (T
o') is To' = t' TL + h' TI + m'
TM (7). Substituting equation (6) into equation (7) 3
), To'=(t+ΔtFc)τt+(h−ΔtFn)τR
+(n-(t+ΔtFt) (h-ΔtFi))τM=
tτt+hrn+(n-1h)τM+ΔtFhτ
L-ΔtFnτH-ΔtFt, τM+MutFaτM(8
). By the way, since trt hτi + mτM = TO (9), To' = To + Δtrm (Fti - Ft,
) (1(It), so we get To' − To = 4 ”or, oυM (, To corresponds to the period of the output signal of the frequency divider 4 when the PLL circuit is phase-locked. Since it corresponds to the period, <11) is the time axis roof.

The gain (GT) is 1, and the time axis dynamic range (D) is DT.
21-: □ (-0 moan FM 2.

The loop gain can be set to any large value by increasing Fit-Ft, but in reality, FM = 4 MHl, FL: I MHz, Fo =
Approximately 7 MHz is appropriate. At this time, the loop gain is 1.5.

Next, a specific circuit configuration of a PLL circuit that operates as described above will be explained. Figure 8 shows PD12 in Figure 6.
FIG. 2 is a diagram showing a specific example of a circuit. In Figure 8, R3
-R1, are each a resistor, CI-Ct are each a capacitor, D
, -D are diodes respectively, Tr, -Trs are transistors, 21 is a terminal to which the output signal of MM13 is supplied in FIG. 6, 22 is a terminal to which the output of the divider 4 is supplied, 23 is a power supply Terminal 24 is a terminal to which voltage Vcc is supplied, and outputs a control voltage to be supplied to VCO3.

In this configuration, when the output of %MM13 is at a low level, the transistor Tr+ is turned off, so that the transistors Tr, , Tr are both turned off. Therefore, transistors Tr, Tr, and Tr6 are also turned off.

Now, assuming that the resistance values of the resistors R3 to RIll are all the same, the voltage output from the terminal 24 will be V2 Vcc. Next, the output of MM13 is at high level, and the branching unit 4
When the output of transistors Tr and Tr
, is turned on. Therefore, the transistor Tr is turned on, and thereby the transistor Tre is also turned on. On the other hand, since the transistor Tr is off, the transistor Tr is turned off. Therefore, terminal 24 has the above-mentioned '/2
A voltage at a low level compared to Vcc is output. However, diode D.

D4. The voltage at the terminal 24 becomes 1/2 Vcc - VO2 because the amplitude is limited by the limiter composed of the resistor RI4 r R+s and the capacitor C11. (However, VO2 is the forward voltage of diode D4.) Also, when the output of MM13 is high level and the output of frequency divider 4 is low level, transistors Tr,, Tr are on, transistor Tr=
is turned off, and as a result, transistor Tr is turned on, and transistor Trs is turned off.

Therefore, a voltage at a higher level than the above-mentioned 1/2 VCC is output to the terminal 24. However, since the amplitude is similarly limited by the limiter mentioned above, the voltage at the terminal 24 is '/2 Vc
c + VO3 (Vna is the forward voltage of diode D).

In this way, by appropriately determining the resistance value of the resistor RHo''Rlg and the forward voltage of the diodes Ds and D4 in the configuration shown in FIG. 8, the above-mentioned Vll shown in FIG.
This provides a PD that outputs three levels: VM and Vt.

According to the PLL circuit of the embodiment described above using FIGS. 6 to 8, the control of the VCO3 in the loop is performed only by Tw set by MM13, and the remaining period (To-Tw
), the vcoa effectively becomes a free run (oscillation frequency FM). Therefore, the loop wasted time is apparently T
Since the time period is only w, the dead time is reduced to Tw/To compared to a conventional analog PLL circuit using sample and hold (sampling is performed at the To period), and an extremely high-speed response is possible.

Furthermore, since the loop LPF is not used, the response speed is not determined by the LPF.

Therefore, since there is no band limit, the same loop gain can be obtained in almost all bands.Furthermore, there is no transient response, so PLL noise such as overshoot after phase lock pull-in does not occur, making it highly stable. A PLL circuit can be obtained.

FIG. 9 is a block diagram showing the configuration of a PLL circuit as another embodiment of the present invention. Components similar to those in FIG. 6 are given the same numbers. In Fig. 9, it is a 14-waveform shaping circuit, and 12& outputs an output according to the output waveform of the waveform shaping circuit 14 only when the output of MM13 is high level, and unconditionally when the output of MM13 is low level. devco
Outputs an output VM for free running a around its center frequency.

Figures 10 (A), (B), and (C) are Figure 9 (a)
~(e) A timing chart showing waveforms of each part, and the operation will be explained below using this timing chart. The waveform shaping circuit 14 outputs the frequency divider as shown in Figure 10 (e).
) is made into a sawtooth wave as shown in FIG. 10(d). The waveform of the sawtooth wave when the output of MM13 (shown as (b) in Figure 10) is at a high level is shown in Figure 10 (e).
The output is as shown below.

Now, the phase of the output signal of the splitter 4 is the external input rectangular wave signal (
MM13 output signal)
PD when the output of MM13 is high level as shown in B)
The output of the frequency divider 12a acts in a direction that increases the oscillation frequency of the VCO 3 and advances the phase of the output signal of the frequency divider 4.

On the other hand, if the phase of the output signal of the divider 4 is advanced compared to the external input rectangular wave signal, as shown in FIG. 10(C), MM1
When the output of PD 3 is at a high level, the output of PD 12a is lower than VM, and since the oscillation frequency of VCO 3 is lowered, the phase of the output signal of divider 4 is delayed.

ξAs shown at the beginning of the 10th cycle, a phase lock state is achieved.

The above-mentioned PLL circuit operates. Next, a specific circuit example of the waveform shaping circuit 14 and PD 12a shown in FIG. 9 is shown in FIG. In FIG. 11, 21' is a terminal to which the output signal of the MM13 is supplied, 22' is a terminal to which the output signal of the divider 4 is supplied, and 23' is the power supply voltage Vc.
24' is a terminal that supplies a side control signal to the VCO3. In addition, R9-R22 are resistors and Cl
0I C11 are capacitors, and 25 is an analog switch. The output of frequency divider 4 is capacitor C11C11,
A waveform shaping circuit consisting of a resistor R7° produces a waveform as shown in FIG. 10(d), and is supplied to the terminal 24' via the analog switch 25 only when the output of the MM13 is at a high level. When the output of the MM13 is at a low level and the analog switch 25 is turned off, a level obtained by dividing Vcc by the resistor Ra l R12 is output from the terminal 24'.

The fruit is ripe as explained using FIGS. 9 to 11 above,
For the remaining period, the configuration is such that the VCO 3 is virtually allowed to run free. Also, the size of the phase shift is MM13
This is reflected in the level of the output signal of the PD 12a when is at a high level. Therefore, the dead time of the loop is small and it is possible to respond at high speed. Furthermore, since there is no need to use a loop LPF, it has the same effect as the embodiment shown in FIG. 6 described above.

In addition, in the embodiments shown in FIGS. 9 to 11, PD12a
The configuration is such that the output of the waveform shaping circuit 14 is triggered at the rising edge of MM13, and sampled and held by a sample hold circuit that is reset at the falling edge of MM13. MM1
It is also possible to adopt a configuration in which the output of No. 3 is held while it is at the No. 3 level.

In the above-mentioned two embodiments, the time width set by the MM13 was constant, but for example, in a transient state until the PLL circuit is phase-locked, the time width is expanded and dynamic It is also possible to configure the range to be large and to narrow the time range after locking to enable high-speed response.

<Description of Effects> As explained above, the PLL circuit according to the present invention substantially shortens the period during which the oscillation of the controlled oscillator is controlled, thereby reducing the dead time of the loop and enabling high-speed response. It is highly effective in that it also has high stability.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the general configuration of a conventional PLL circuit, Figure 2 is a diagram showing the main part configuration of an example of a conventional analog PLL circuit, and Figure 3 is similar to Figures 2 (a) to (e). Timing chart showing waveforms of each part; Figure 4 is a diagram showing an example of the configuration of a conventional digital PLL circuit; Figure 5 (5), (B), and (C) are timing charts showing waveforms of each part of the fourth figure. , FIG. 6 is a block diagram showing the configuration of a PLL circuit 1 as an embodiment of the present invention, FIG. A diagram showing a specific example of the circuit of the PD in the present invention. Fig. 9 is a timing chart showing the waveforms of each part, Fig. 11 is a diagram showing a specific circuit example of the main part of Fig. 9. 3 is a voltage controlled oscillator, 4 is an h frequency divider, 12° 12a is a A phase comparator, 13 is a monomultipipe rake, and 14 is a waveform shaping circuit.Ce)

Claims (1)

[Claims] 1) A PLL circuit including a controlled oscillator and phase comparison means for controlling the oscillator according to a phase difference between a signal related to the output of the oscillator and an input signal, wherein the phase comparison means controls the oscillator. A PLL circuit characterized in that it comprises means for setting a period in which the PLL circuit operates.