JPS6346013A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain a stable oscillation output with high accuracy by supplying an oscillation output of a voltage control type variable oscillator by only one shot at every N shots through a gate circuit to a phase comparator, and obtaining a phase comparison output. CONSTITUTION:The titled circuit consists of a voltage control type variable oscillator 110, a frequency divider 120 for dividing an oscillation output into 1/N (N is an integer), a gate circuit 130 for allowing the oscillation output to pass through by only one shot at every N shots, a phase comparator 140, and a loop filter 150. By a voltage control type variable oscillator 110 by which a phase comparison output of a phase of an input signal pulse given to a signal input terminal 160 and a phase of a gate output pulse by the gate circuit 130 becomes a control voltage, an oscillation output of a 1/N period whose phase has been fixed against a period T of an input signal pulse is obtained and outputted from a signal output terminal 170. In this way, a stable oscillation output whose phase has been fixed is obtained from the voltage control type variable oscillator 110 with high accuracy.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A Industrial field of application B0 Overview of the invention C0 Prior art 4 Problems to be solved by the invention E4 Means for solving the problems (Fig. 1) F1 Effect G, Examples (G-1) Disc Format (Figures 2 to 5) (G-2) Magneto-optical disk device (Figure 6) (G-3)
An example of a laser drive circuit (Figs. 7 and 8) (G-4) Specific example of a PLL circuit (Figs. 9 and 10) A control clock pulse such as a sampling clock pulse used in a processing circuit is formed by a single clock pulse (PLl, :Pbase l, o).
ckedl, oop) circuit.

1. Summary of the Invention The present invention provides various control methods for forming pulses.
L L times h'81, the oscillation output of the voltage-controlled variable oscillator is supplied to the phase comparator once every N oscillations via the non-note circuit to obtain a phase comparison output. In this way, a highly accurate and stable oscillation output can be obtained from the voltage controlled variable oscillator.

C1 Conventional technology In general, Pl, 1, which forms various control clock pulses.
The circuit, for example, as shown in FIG.
The frequency is divided into The loop filter 250 converts the voltage into a control voltage and supplies it to the voltage-controlled variable oscillator 210.

The PLL circuit performs phase comparison at the period T of the input signal pulse, and outputs from the signal output terminal 260 an oscillation output with a 1/N period whose phase is fixed to the period T of the input signal pulse.

D8 Problems to be Solved by the Invention By the way, in the conventional PLL circuit configured as described above, when the frequency division ratio 1/N of the frequency divider 220 is set to a large value, due to the phase delay in the frequency divider 220, etc. It is difficult to obtain a stable oscillation output from the voltage-controlled variable oscillator 210 by locking the phase to the input signal pulse with high precision, and it is difficult to realize a practical lock generation circuit even with a voltage of around N-200. there were.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, the present invention provides a novel configuration that enables a voltage-controlled variable oscillator to provide a stable oscillation output that is phase-locked with high accuracy to the phase of an input signal pulse. The purpose is to protect the PLI circuit.

r<, Means for Solving the Problems In order to achieve the above-mentioned object, the PLL circuit according to the present invention uses a voltage-controlled variable oscillator as shown in the block diagram of FIG. 110 and ”-Power distribution 1! The oscillation output of the controlled variable oscillator 110 is l/N (N is an integer)
A frequency divider 120 that divides the frequency, and a gate that uses the frequency divided output from the frequency divider 120 as a gate pulse 'ic, and passes only one pulse from the voltage-controlled wall voltage controlled variable oscillator 110 to the N waves 'Iu. circuit 130 and -1- gate circuit 130
- a loop that converts the comparison output from the phase comparator 140 into a control voltage and supplies it to the voltage-controlled variable oscillator 110; filter 150
It is characterized by consisting of.

In the r'Ll circuit according to the present invention, the signal input terminal 160
The phase of the input signal pulse given to and the gate circuit 1
In the voltage-controlled variable oscillator 110 whose control voltage is the phase comparison output with the phase of the gate output pulse by 30,
1/ whose phase is fixed to the period T of the above input signal pulse
An oscillation output of N periods is obtained and outputted from the signal output terminal 170.

G. Example Hereinafter, an example of a PLL circuit according to the present invention will be described in detail with reference to the drawings.

In this embodiment, the present invention is applied to a magneto-optical disk device that records and reproduces data using a magneto-optical disk, which has been known as a large-capacity recording medium in which data can be rewritten. be.

First, the formant of the magneto-optical disk in this embodiment will be explained.

G-1. Disk Format FIG. 2 schematically shows the recording pattern of the magneto-optical disk in this embodiment.

In Fig. 2, the magneto-optical disk l has a diameter of, for example, about 13 cm, and is 300M high on the lunar surface.
It has a fertilizer capacity of . This disk l is Kakuren 1
The disk is rotated at a constant rate, and data is recorded by forming tracks 2 concentrically, for example, with one track per rotation. The number of tracks on one side is about 18,000 to 20,000, and each track is divided into, for example, 32 sectors.

In addition, [-2 each track is shown enlarged in FIG.
It consists of a pit area 2a having pits for nerfs and a data area 2b in which data is written, and these are provided alternately along the circumferential direction. "-The lengths of the pinodo area 2a and the data jJf area 2b are:
When converted to Hyde, for example, "-Pino l?" IJi area 2
a is 2 high, and the data area 2b is 16 high.

As shown in FIG. 4, three pits l-+)a, PR, and Pc are formed in each of the pit regions 2a. The pits I'PA, Ps are formed with a vertical shift across the center line of the track formed on the disk l, and the pit Pc is formed on the center line. The diameter of each of these pits PA, P, PC is 0.
The actual length of the focus area is about 15 to 30 μm.

FIG. 5 shows the arrangement of pinots P, , P, , P, in the radial direction of the disk I (in the direction of the arrow in FIG. 2). That is, the pits Pa and Pc are arranged linearly, and the pits P are arranged one after the other in the longitudinal direction of the track every 16 pits. Above 1
The array of pits PA whose positions are shifted every six pits is used to perform a track count, which will be described later, in order to determine the track number currently being scanned by the optical pickup.

Further, the pit PA is a sample pulse SP.

Alternatively, each pit PB, Pc is sampled by sample pulse SP2, and each pit PB, Pc is sampled by sample pulse SP3.
Further, the specular area between the pits PB and Pc is sampled by the sample pulse SP4, and is used for various servo and clock generation described later.

G 2. magneto-optical disk device FIG. 6 shows the overall configuration of the magneto-optical disk device.

In this embodiment, data D1 to be recorded is supplied to the input terminal 11 from, for example, a computer or the like via an interface. This data D is the modulation circuit 1
After being sent to the laser drive circuit 13, the signal is sent to the laser drive circuit 13 after being subjected to predetermined modulation including pit conversion. This laser drive circuit 13 is given a control signal for each mode of writing, reading, or erasing from the above-mentioned interface, and outputs a signal for driving the laser diode 21 of the ζ optical pickup 20 in response to the control signal, and outputs a signal for driving the laser diode 21 of the ζ optical pickup 20. The clock used as the reference clock during recording and erasing
A drive pulse (No. 3) with a timing corresponding to the clock CCK and a high frequency drive signal at the time of reading are supplied to the laser diode 21.

-1- The optical pickup 20 includes, in addition to the laser diode 21, a photodiode 22 and two photodetectors 23 and 24 each divided into four parts. The photodiode 22 detects the intensity of the laser light emitted by the laser diode 21. The photodetectors 23 and 24 detect the reflected light of the laser beam by the magneto-optical disk 1 through analyzers, one of which detects the positive component of the Kerr rotation angle, and the other of which detects the positive component of the Kerr rotation angle. The negative direction component of is detected.

Further, the motor 14 is operated by a morph servo circuit 15, for example, as a PLL (Phase Locked Loo).
A servo is performed based on p) to accurately rotate the disk 1 at a predetermined speed (angular speed).

The laser light output from the laser diode 21 is irradiated onto the magneto-optical disk l and is also incident on the photodiode 22.

The photodiode 2 corresponds to the light intensity of the laser beam.
The output of 2 is supplied to a sample Hall l" (S/H) circuit 17 via a DC amplifier circuit 16. In this S/H circuit 17, the output of This output is sent to the laser drive circuit 13 via the APC amplifier circuit 18 as an auto-matic power converter (APC).
rol) is supplied as a control signal. by this,
The light intensity of the laser light output from the laser diode 21 is maintained at a predetermined value.

The optical pickup 20 receives the reflected light of the laser beam from the disc L through an analyzer not shown in the figure.
The respective outputs of the photodetectors 23 and 24 are sent to a preamplifier circuit 31, respectively.

From this preamplifier circuit 31, each of the photodetectors 2
3. Photodetection signal SA (SA=A+B+C-1-D(Δ'l
11'+c'+D') (including a DC component) is directly sent to the focus servo circuit 32, and the photodetection signal Sl+[3B
-(AC-11D)+(A'C'-13'l'lil) is sent to the focus servo circuit 32 via the S/H circuit 33 which performs a lean-sol bold operation in response to the number pulse SP.

A focus servo control signal generated by the focus servo circuit 32 based on the signals SA and SR is sent to the optical pink-up 20 to perform focus control.

Further, the photodetection signals S, (S
c=A+B+C+D+A'+B'+C'+D') are sent to the peak value detection circuit 41.3/H circuit 51.52.53 and the sampling clamp circuit 61, respectively.

The photodetection signal Sc is a detection signal of a concavo-convex pattern in the focus area 2a of the disc 1. The peak value detection circuit 41 detects the peak value of the photodetection signal Sc, and the unique pattern detection circuit 42 detects a unique interval between the bits PB and PC on the disk 1. Detects the pit pattern and displays the above beep)
P c is detected, and the detection output is sent to the pulse generation circuit 44 via the delay circuit 43 . The pulse generating circuit 44 generates the channel clock CCK as a reference clock synchronized with the above-mentioned and... Pc based on the detection output obtained by the unique pattern detection circuit 42, and Height cross BYC, servo height "1 Tsuku S"
BC and sample pulses SP+, Sc2, SPi
, Sc4, and SPs are formed and output (see FIG. 5). Although not shown, the channel clock CCK is supplied to all the circuit blocks.The sample pulse SP is supplied to all the circuit blocks.

HaS/! 1 circuit 51, sample pulse 51)
2 is supplied to the S/H circuit 52 and the sample pulse 5
1) 3 is supplied to the S/l-1 circuit 52. The sample pulse SP4 is also supplied to the S/H circuit 17.33 and also to the sampling clamp circuits 61.62. Note that the sample pulse SP5 is used, for example, to detect the moving direction of the optical pickup 20Q). In addition, −F peak value detection circuit 4
1 and the unique pattern detection circuit 42 are supplied with Kate pulses from the pulse generation circuit 44.

In each of the S/H circuits 51, 52, and 53, each of the sample pulses SP, , S
P2. A sample and hold operation is performed at sp3.

The output from the S/H circuit 51 and the output from the S/H circuit 52 are compared in level by a comparator 54. This comparison output is the disk 1 of the above bin PA.
Reversing every 16 torasok in relation to the radial arrangement above,
The signal is sent to the tracking servo/seek circuit 55 as a traverse count signal, and also to the multiplexer 56. The multiplexer 56 selectively outputs a higher level signal among the signals from the S/H circuits 51 and 52 and sends it to the subtraction circuit 57. In the subtraction circuit 57, a difference signal between the signal from the multiplexer 56 and the signal from the S/H circuit 53 is formed and sent to the tracking servo/seek circuit 55 as a tracking error signal. The tracking servo/seek circuit 55 performs tracking control and feeding control of the optical pickup 20.

Further, the 1-th sampling clamp circuit 61 receives the 10th photodetection signal Sc, and the sampling clamp circuit 62 receives the photodetection signal 5o (Sn=(Δt r< −+−
c→-D)-(A'+B'+C'+D')] are supplied from the preamplifier circuit 31, respectively. The photodetection signal S is a detection signal of the concavo-convex pattern in the focus area 2a of the disc 1, as described above.

Further, the above-mentioned photodetection signal A;1°C S11 is a detection signal of data written in the data area 2b of the disc 1. Each signal is clamped by the ripple pulse S4 in each of the R/C 9F1 circuits 61 and 62 and sent to the multiplexer 63.

The switching selection operation of the multiplexer 63 is controlled by the control signal 15 from the sink detection/address decoding circuit 64.

For example, first, the photodetection signal M3. is the analog signal via the sampling clamp circuit 61 and multiplexer 63.
Assuming that the output from the demodulation circuit 66 is sent to a digital (A/D) converter 65, converted into a digital quantity, and then sent to a demodulation circuit 66, the output from the demodulation circuit 66 is sent to a sync detection/address decoding circuit 64, At the same time, the address information is decoded.

Then, according to the address information of the data to be read supplied from a computer or the like via an interface, the multiplexer 63 is switched and controlled when the address information and the actual address match, thereby producing a photodetection signal S for the data area 2b. , is the A/D converter 65. Data D is sent to the demodulation circuit 66 and obtained through demodulation processing including bit conversion from the output terminal 67. is now output. This data D. is sent to a computer etc. via an interface.

Furthermore, when writing data, a control signal is sent from the sync detection/7 dress decoding circuit 64 to the modulation circuit 12, and in response to this control signal, the data to be written is sent from the modulation circuit 12 to the laser drive circuit 13. pat me like that.

G-3, Example of laser drive circuit A specific example of the configuration of the laser drive circuit 13 is shown in FIG.

Note that this FIG. 7 shows the laser diode 21 and AP
The C circuit system is also shown.

In this configuration example, a control pulse for instructing a read operation is supplied to the terminal 71, and a control pulse for instructing a write operation or an erase operation is also supplied to the terminal 75.

Terminal 71 is connected to the base of transistor Q2 via transistor Q1. This transistor Q2
The transistor Q3 has its collector and emitter commonly connected. The collector of the transistor Q3 is connected to the heath of the transistor Q4 and the resistor R. The emitter of the transistor Q4 is connected to the base of the transistor Q through a diode 72. - Each transistor Q3. Q4 and tie auto 72 constitute a ring oscillator. Further, the emitters of the transistors Q3 and Q5 are commonly connected to the collector of a current source transistor Q6, and the emitters of the transistors Q are connected to the power supply terminal 13 via a resistor R2. Moreover, the above transistor Q.

is connected to a terminal 74 that provides a predetermined heath voltage VBB.

Further, the terminal 75 is connected to the base of a transistor Q8 via a transistor Q7.

The collector of this transistor Q8 is connected to the laser diode 21, and the transistor Q,
connected to the collector. In addition, the transistor Q,
has its collector installed via resistor R3,
The heath is connected to the terminal 74. Each of the above transistors Qa.

Q, each emitter is commonly connected to the collector of the current source transistor Q1o, and the transistor Q10
The emitter of is connected to the power supply terminal 73 via a resistor R6.

The photodiode 22 for detecting the intensity of the laser beam emitted from the laser diode 21 has a resistor R5.
It is also connected to a switching element -r77 via a 1III arithmetic amplifier 76 for DC amplification. The switching element 7 is connected to a 7I capacitor C1 and an operational amplifier 78 having a high input impedance. The switching element 77 is
The photodiode 2 is supplied with the sample pulse SP4 via the operational amplifier 76.
The output of 2 is sampled with a sample pulse SP, denoted by F, and the sample signal is
Performs a hold operation. Further, the output terminal of the operational amplifier 78 is connected to each inverting input terminal of each operational amplifier 79, 80 by a resistor R.
6. L-registered operational amplifier 79.8
0 is applied to each non-inverting input terminal (II! voltage V REF is applied, one output terminal is connected to the heath of the transistor Q6, and the other output terminal is connected to the transistor Q6).
Connected to 1o heath. Further, the inverting input terminal of the operational amplifier 80 is connected to a terminal 81 via a resistor R7. This terminal 81 is supplied with a control signal for switching and controlling the output of the laser diode 21 between the write operation mode and the erase operation mode.

Next, the operation of the laser drive circuit configured as described above will be explained.

When the terminal 71 is at the low (L) level, the transistors Ql and Q2 are held in the off state, and the ring oscillator formed by the transistors Q3 and Qs operates at, for example, 70.
Performs high frequency oscillation operation of about 0MHz to IGHz. As a result, the laser diode 21 is supplied with a high frequency current having a peak value of current 1cso from the current source transistor Q6 via the transistor Q5, and is driven at high frequency. Furthermore, when the terminal 71 is at a high (H) level, the transistors C++ and Q2 are held in the on state, so that the current lesH from the transistor Q6 flows through the resistor R1 through the transistor Q2.
, the driving of the laser diode 21 is stopped, and the oscillation operation of the ring onlator is also stopped.

The laser diode 21 is driven by high frequency current,
1i:j5 This is performed by supplying a control pulse that becomes L level to the terminal 71 during the extraction operation mode.

Furthermore, when the input terminal 75 is at L level, each transistor Q, QB is held off, and the current source transistors Q, QB are kept off. The current i css flows through the transistor Q to the resistor R3 and does not flow to the laser diode 21. In addition, the terminals 75 are connected to each transistor Q1. When Qa is turned on, the current source transistor Q,.

A current i css flows to the laser diode 21 via the transistor Q8. In this embodiment, for example, in the write operation mode, by supplying a control pulse corresponding to data to the terminal 75,
Data is written by driving the laser diode 21 in pulses corresponding to the data.

Furthermore, the operation of the laser drive circuit will be specifically explained with reference to FIG. Note that FIG. 8 shows the current value i supplied to the laser diode 121. The current waveform in the write operation mode is shown in FIG. 8A, the current waveform in the erase operation mode is shown in FIG. 8B, the current waveform in the read operation mode is shown in FIG. The current waveform in the standby operation mode is shown in Figure 8.

In the write operation mode, both terminals 71 and 75 are held at the L level during the period corresponding to the pit area 2a, so that the laser diode 21 is driven by a high frequency current as shown in FIG. 8A. be done. Also,
During the period corresponding to the data area 2b, the terminal 71 is held at H level and a data pulse corresponding to the write data is supplied to the terminal 75, thereby pulse-driving the laser diode 21 to write the data. Write. The timing of this write operation, that is, the timing of the data pulse, coincides with the channel clock CCK formed based on the detection output of the pit PC.

Here, during the period corresponding to the focus area 2a, even in various operation modes other than this write operation mode, the [/- the die auto 21 is always driven by a high frequency current and a read operation is always performed.

In the erase operation mode, during the period corresponding to the data area 2b, the above terminal 71 is held at level 11, and the ``-'' ◇
:1; By repeatedly supplying pulses to child 75
(, as shown in FIG. 8B, the above laser diode)-'
21 is pulse-driven to perform a data erasing operation. The timing of this erasing operation, that is, the timing of the above-mentioned repeat pulse, also coincides with the above-mentioned channel clock and 1 clock CCK.

In the read operation mode, each terminal 7 is
1.75 are both held at [7 levels, as shown in FIG. 8C, data is read out by driving the above-mentioned read diode 21 with a high frequency current.

Furthermore, in the standby operation mode, as shown in Figure 8,
During the period corresponding to the data area 2b, the terminal 75 is held at L level, the drive of the laser diode 21 is stopped, and only the reading of the pit area 2a is performed.

Here, in any of the above-mentioned operation modes, the bases of the transistor Q6 and the transistor Q1 are APC-controlled by the operation of the APC circuit system including the photodiode 22, etc.
1 output (light intensity) is maintained at a predetermined value. In addition, in the erase operation mode, a larger drive current is applied to the laser diode 21 than in the record operation mode, so that the control signal voltage applied to the terminal 81 is changed between the record operation mode and the erase operation mode so that the erase operation is reliably performed. and set to different values.

In this way, by efficiently pulse-driving the laser diode 21 during the data write operation mode and the erase operation mode, the life of the laser diode 21 can be extended, and power consumption can be reduced. Radio interference etc. can also be reduced.

(, -4, T, 'Specific example of LL circuit) In this embodiment, the pulse generating circuit 44 has a PL circuit according to the present invention, as shown in FIG.
1. , the circuit is applied.

In the specific example shown in FIG. 9, a voltage-controlled variable oscillator (
VCO) 110 has a TTL level two-phase output (CK),
(CK) is used. and,
The positive phase output (CK) of the voltage controlled variable oscillator 110 is output from the signal output terminal 170 and is 1/N
It is supplied to the clock input terminal of the frequency divider 120, the clock input terminal of the first D-type flip-flop 131 of the gate circuit 130, and the first AND gate circuit 132.

Further, - the negative phase output of the voltage controlled variable oscillator 110 (
CK) is supplied to the clock input terminal of the second D-type flip-flop 133 of the gate circuit 130 and the second AND gate circuit 134.

The frequency divider 120 is composed of an N-ary (in this specific example, 200-ary, that is, N=199) counter, and counts the positive phase output (CK) of the voltage-controlled variable oscillator 110, and counts the positive phase output (CK) of the voltage-controlled variable oscillator 110. , the count output is set to the NA of the gate circuit 130.
The output of the NAND gate circuit 135 is cleared at the rising edge of the affirmative output (Q) of the first D-type flip-flop block 131, which is supplied to the data input terminal. ing.

As shown in the timing chart of FIG. 10, the NAND gate circuit 135 is configured such that the value of the 8-bit count output supplied from the frequency divider 120 is N-1, that is, r198J.
The logic is rLJ when . and,
The first D-type flip-flop 131 whose data input terminal is supplied with the output of the NAND gate circuit 135 is
An affirmative output (Q) obtained by delaying the NAND output by one clock is supplied to the clear input terminal of the frequency divider 120 as a clear pulse. Furthermore, the first D-type flip-flop 131 converts its negative output (Q) into a second
The second ΔN+) gate circuit 1 is supplied to the other input terminal of the D-type flip-flop 133.
34. In addition, the positive output (Q) obtained by delaying the negative output (Q) of the second I type rough flip-flop 133, )- first D type flip-flop 131 by 1 cro, 1 AND gate circuit 132.

This 3L gate circuit 130 has a 3L configuration.
) type flip-flop 131 as a negative output (Q) as a single control pulse.
4, the voltage Y1 . The negative phase pulse (CK) of the controlled variable oscillator 110 is supplied as ΔN1]2 output to the 8N+) gate circuit 141 of the −1− phase comparator 140, and the second 1) type flip-flop 133 from the first AN I) gate circuit 132 whose positive output (0) is a -1 control pulse;
The value of the 8-hit 3i number output from the frequency divider 120 is ANDed with the positive-phase pulse (CK) of the voltage-controlled variable oscillator 110 that exists every period of N, that is, r199, and the NAND of the phase comparator 140 is used as the output. Gate circuit 142
supply to.

Further, the phase comparator 140 includes an AND gate circuit 14
The output terminal of N 1 is connected to the input terminal of a loop filter 150 via a forward diode 143 and a resistor 144, and the output terminal of N
The output terminal of the AND gate circuit 142 is the reverse diode 1.
45 and a resistor 146 to the input end of the loop filter 150. In addition, each of the gate circuits 14
The detection output RZ from the above-described unique pattern detection circuit 42 is supplied from the signal input terminal 160 to each input terminal of 1.142.

The loop filter 150 includes an operational amplifier 15
1. An integrating circuit constituted by each resistor 152, 153 and a capacitor 154 is used, and each gate circuit 141, 142 of the phase comparator 140 is used as a current pump to balance the charging and discharging current of the capacitor 154. The oscillation phase of the mold 1-11 variable oscillator 110 is controlled.

In the pulse generator 44 having such a configuration, 1) the phase comparator 140 receives the input signal pulses, the detection output RZ from the unique pattern detection circuit 42, and each gate output AND from the gate circuit 130; ,,A
During the period when ND2 is supplied [1 ear] acts as a current pump for the above loop filter 150, and during the period shown in the timing chart, a reverse bias is applied to each diode 143 and 145, and the comparison output The end is in an open state, and a so-called three-state phase comparison operation is performed.

As shown in FIG. 10, the signal input terminal 716
The above voltage is set by the gate outputs AND, , AND2 of the gate circuit 130 so as to clear the frequency divider 120 at the center position to of the input signal pulse supplied to the gate circuit 130, that is, the center position to of the detection output RZ by the above-mentioned unique pattern detection circuit 42. The oscillation phase of controlled variable oscillator 110 is fixed.

H. Effects of the Invention As is clear from the description of the above embodiments, P according to the present invention
In the LL circuit, the voltage-controlled variable oscillator uses the phase comparison output between the phase of the gate output pulse and the phase of the input signal pulse by the gate circuit that passes the oscillation output of the voltage-controlled variable oscillator once every N pulses as a control voltage. Since the oscillation phase of the oscillator is controlled, a stable oscillation output can be obtained from the voltage-controlled variable oscillator by locking the phase of the input signal pulse with high accuracy regardless of the frequency division ratio of the frequency divider.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a PLL circuit according to the present invention, FIG. 2 is a schematic diagram showing a recording pattern of a magneto-optical disk in an embodiment of the present invention, and FIG. FIG. 4 is a schematic diagram showing the configuration of each track in the above embodiment, FIG. 4 is a schematic diagram showing the configuration of each focus area, and FIG. 5 is a schematic diagram showing the configuration of each focus area along the radial direction of the disk. FIG. 6 is a schematic diagram showing the arrangement state;
The figure does not show the overall configuration of the embodiment of the magneto-optical disk device.
FIG. 7 is a circuit diagram showing a specific configuration example of the laser drive circuit in the above embodiment, and FIG. 8 is a timing chart marked with - to explain the operation of the laser drive circuit. The ninth part is a circuit diagram showing a specific configuration example of the pulse generator circuit to which the present invention is applied in the embodiments 1 to 1, and Figure 1O explains the operation of the pulse generator circuit to which the present invention is applied. This is a timing chart for FIG. 11 is a block diagram showing a conventional example of a PLL circuit. 44... Pulse generation circuit 110... Voltage controlled variable oscillator 120... Frequency divider 130... Gate circuit 140... Phase comparator 150 - Loop filter 160... Signal input terminal 170... Signal input terminal

Claims (1)

[Claims] A voltage-controlled variable oscillator, a frequency divider that divides the oscillation output of the voltage-controlled variable oscillator by 1/N (N is an integer), and a gate pulse for the frequency-divided output of the frequency divider. a gate circuit that allows the oscillation output of the voltage-controlled variable oscillator to pass through only one out of every N pulses; a phase comparator that compares the phase of the gate output pulse from the gate circuit with the phase of the input signal pulse; A phase-locked loop circuit comprising a loop filter that converts a comparison output from a phase comparator into a control voltage and supplies the voltage-controlled variable oscillator to the voltage-controlled variable oscillator.