JPH0887833A - Pll circuit and information processor - Google Patents

Abstract

PURPOSE: To obtain a PLL circuit, and an information processor employing the PLL circuit, which can be constituted of a VCO comprising a single CMOS and in which the sensitivity of VCO can be adjusted while stabilizing the operation. CONSTITUTION: A pull-in type phase comparator 34 compares the phase between a clock signals MLOAD1 and NLDO and delivers a pull-in charge signal CHGP and a pull-in discharge signal DISP based on the phase difference. A lock-in type phase comparator 36 compares the phase between a differentiated binary signal and clock signal CLK and then delivers a clock-in charge signal CHLR and a clock-in discharge signal DISR based on the phase difference. An output signal from any one phase comparator selected based on a signal PULLIN1 is smoothed according to a cut-off frequency set at a filter 32 and a VCO control voltage VCOIN is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an optical disk device for recording / reproducing information on / from an optical disk (disc-shaped information recording medium) based on a clock signal having a different frequency according to its radius. The present invention relates to an information processing device and a PLL circuit that generates a clock signal used when recording and reproducing the information.

[0002]

2. Description of the Related Art For example, as a method for recording information on an optical disc, MCAV (Modified Constant Angular) is used.
Velocity) method. In this method, information is recorded on an optical disc at a constant density, so that information is recorded based on clock signals having different frequencies according to the radius of a track to be recorded.

In the optical disc apparatus adopting the MCAV system, a master PLL circuit for generating a clock signal required as a timing for recording information, and a data required for reading and reproducing the information from the optical disc. Data P for generating a clock signal for discriminating between
The LL circuit is built in. PLL (Phase-Locket Loo
p) means a phase locked loop, and is a circuit configuration that detects the phase difference and controls by feedback so that the frequency and phase of the oscillator always match the frequency and phase of the input signal. For more information on PLL in general, see "How to use PLL-IC" by Hata and Furukawa (Akiha Shuppan), for example.

The master PLL circuit receives a high-precision single-frequency reference clock signal supplied from an external clock source such as a crystal oscillator as an input signal and generates clock signals of various frequencies.

The data PLL circuit generates a data signal and a reproduction timing clock signal which are phase-synchronized with the reproduction binary signal when the reproduction binary signal obtained by binarizing the reproduction signal obtained from the optical disk is input. is there.

In the master PLL circuit, a signal obtained by dividing a clock signal of a constant cycle obtained from an external reference oscillator such as a crystal oscillator with a high precision by M (M is a division ratio set by the user) and a signal of the master PLL circuit. A voltage controlled oscillator (Voltage Contorolled Oscillator), which is one of the components,
Called VCO for short. The output loop clock signal from (1) is frequency-divided by N (N is a frequency division ratio set by the user), and the feedback loop is configured so that the phase difference becomes "0". A portion for performing phase comparison is called a phase comparator, and the phase comparator configured by the master PLL circuit is a pull-in type phase comparator used when two input signals to be subjected to phase comparison are periodic.

In the pull-in type phase comparator, only the timings of the rising edges of the two input signals are significant, and in the loop formed in the master PLL circuit, the timings of the rising edges of these two input signals should be matched. Ideally it works. However, in an actual phase comparator, rising edges of two input signals are not generated at the same time, only one of them is advanced, and a charge signal is generated for a certain time from the time when both edges are generated. There is some phase between the two input signals. The fixed time of the charge signal is the time until the two flip-flops forming the phase comparator are reset, and this time depends on the delay time of this path.

As a result of the phase comparison by the phase comparator, when the phase of the output signal from the VCO is advanced with respect to the reference clock signal from the outside such as a crystal oscillator, the input voltage of the VCO is lowered, and the VCO input voltage is lowered. When the phase of the output signal is delayed, the VCO input voltage may be increased. The VCO input voltage is obtained by charging a capacitor that holds a charge. Since the result of the phase comparison is obtained by the pulse width, a voltage change proportional to the phase difference can be obtained by charging or discharging with a constant current during this pulse width. There are various methods such as using an operational amplifier to obtain a constant current.

The master PLL circuit performs phase comparison between a signal obtained by dividing a reference clock signal from the outside such as a crystal oscillator by M and a signal obtained by dividing the clock signal from the VCO by N,
Since the phase difference between both signals is set to "0", if the frequency of the external reference clock signal is f0 [Hz], the frequency f of the output clock signal of the master PLL circuit is f.
Is f = (N / M) f0 [Hz]. Here, M is the disc rotation speed, modulation method, minimum pit pitch, MCAV
It is determined by the conditions such as bandwidth in the system. The modulation method is a channel coating method such as 1-7 modulation or 2-7 modulation. The minimum pit pitch is the pit interval when the pit interval is the shortest on the channel code. For example, in the case of 1-7 pit edge recording (also referred to as mark length recording), it corresponds to "1010" in the channel code. It is the pit interval, and in the case of 2-7 pit edge recording, "1" in the channel code
It is a pit interval corresponding to "00100".

In the MCAV system, a certain number of tracks in the radial direction are called a band, and the frequency of a clock signal for recording information is constant within this band. The band width is the width of the band in the radial direction. If the bandwidth is small, the frequency will be switched frequently, and control will be complicated. Further, if the band width is large, the difference in the minimum pit pitch between the inside and outside of the band becomes large, and as a result, the recording density decreases. On the other hand, the phase comparison interval is M / f0
[S], but if this time is short, the jitter becomes worse.

The data PLL circuit detects the phase difference between the rising edge of the digital signal obtained by binarizing the signal read from the recording medium and the clock signal which is the output of the VCO by the lock-in type phase comparator. A data signal and a reproduction timing clock signal which are phase-synchronized with the reproduction binary signal are generated based on the reproduction binary signal obtained by binarizing the reproduction signal obtained from the optical disk. This lock-in type phase comparator requires a clock signal which is the output of the VCO and its logically inverted clock signal from the viewpoint of operation, and is the ratio of the high and low times in one clock of the clock signal. It is desirable that the duty be as close to 50% as possible.

When the input signal of the data PLL circuit is the pit position recording, either the rising edge or the falling edge of the input digital signal has a meaning, and the polarity is such that this meaningful edge becomes a rising edge. If the binary signal (input digital signal) is input as it is, phase comparison can be performed. Further, when the input signal of the data PLL circuit is pit edge recording, both the rising edge and the falling edge of the binarized signal have a meaning, so it is necessary to digitally differentiate and input.

The reproduced signal obtained from the optical disk must be binarized by some method and converted into a digital signal (reproduced binary signal). For example, when reading a disc on which pit edges are recorded, a method of binarizing a reproduction signal at an appropriate slice level or a timing of inverting the intersection of this signal and zero level by differentiating the reproduction signal twice. There are ways. An appropriate slice level is a level that follows a change in the center of the eye pattern due to a change in recording film sensitivity in the recording area or a change in recording laser intensity.

In the subsequent stage of the data PLL circuit, the data signal output from the data PLL circuit is discriminated by the rising edge of the reproduction clock timing signal.

In the data PLL circuit, the frequency of the reproduction clock timing signal is a natural number multiple of the frequency of the input signal (to be exact, n ≧ 2, n is reproduction in order to correspond to a non-periodic data waveform with missing teeth). The output of the lock-in type phase comparator becomes zero at the point that the frequency of the clock timing signal becomes a natural number indicating how many times the frequency of the input signal), and there are many stable points. In the data blank area on the disc (the data area following the preformatted area in the data format on the disk where user data etc. has not been written yet), the data of the next preformatted area further following the blank area So that the data PLL circuit can be pulled in correctly when
The frequency of the master PLL circuit is adjusted to the frequency of the recording clock signal of the address (that is, the track) to be read, and the divided signal of the output clock signal of the master PLL circuit is input to the data PLL circuit to generate the oscillation frequency of the data PLL circuit. Need to be set to almost the same frequency. Also, at the time of reproducing information, the master PLL circuit is set to the frequency that should be currently read, and this and the data P
The oscillation frequency of the LL circuit is constantly compared to monitor whether the data PLL circuit is operating at an abnormal frequency.

In this way, the master PLL circuit and the data P are
The LL circuit has a configuration in which each has a VCO.

For example, in the case of an analog VCO, the VCO preferably has an input as an analog voltage and outputs a clock signal having a frequency directly proportional to this voltage value. Also, when many VCOs are manufactured, the ratio of the frequency (f) of the output clock signal to the input voltage (V), that is,
It is desirable that the slope of the straight line of the fV characteristic (hereinafter referred to as sensitivity) does not vary from a certain desired value.

The sensitivity is a constant value when the fV characteristic is an ideal linear function, but becomes a function of the input voltage V when the characteristic is not linear. When it can be regarded as almost linear, there are many cases where various characteristic calculations are performed when designing a PLL loop with a constant value.

Since the VCO sensitivity is related to the band of the PLL loop, it is an important factor affecting the characteristics of the PLL loop. For example, the higher the sensitivity, the wider the band of the PLL loop and the faster the response. In this way, VCO f
How close the -V characteristic is to linear is one of the components of the loop.
It becomes an important index as one. Further, if there are large variations in the sensitivity when a large number of VCOs are manufactured, the characteristics of the PLL circuit also vary among optical disk devices, and stable operation cannot be guaranteed, which is a problem.

The VCO has various oscillation methods. For example, "How to use PLL-IC" by Hata and Furukawa mentioned above.
(Akiha Shuppan) describes some methods, and introduces an emitter-coupled multivibrator, a VCO having a CMOS configuration, a VCO using an operational amplifier, etc., depending on the difference in circuit form. Next, the features of the operation principle of each method will be briefly described.

In the emitter-coupled multivibrator, f
While the linearity of the −V characteristic is excellent and variations in sensitivity are small, an external capacitor is required to set the sensitivity. A VCO having a CMOS structure is also suitable for low power consumption and high integration of ICs. A VCO using an operational amplifier has many parts such as external resistors and capacitors for setting the sensitivity, while the free-running oscillation frequency is determined by the values of the external resistors and capacitors.
It is convenient to have a free-running oscillation frequency that is accurate to some extent, but in principle the slew rate of an operational amplifier limits the oscillation frequency, so it is necessary to use a relatively expensive operational amplifier at high frequencies.

Among various VCOs having such characteristics,
Considering the linearity of the fV characteristic of the VCO and the variation in sensitivity, the method using an emitter-coupled multivibrator is often adopted.

[0023]

Since the VCO based on the method using the emitter-coupled multivibrator used in the conventional PLL circuit uses a bipolar transistor,
Considering the use of LSI for the PLL circuit, a full custom LSI
For example, a wafer is made in advance up to the step immediately before wiring, and then the wiring step is performed according to the logic circuit requested by the user.
The most popular CMOS among ion specific ICs)
Compared with the gate array, it cannot be denied that it is significantly inferior in terms of design work and manufacturing period.

Further, the VCO having the CMOS structure has a large variation in sensitivity, and particularly when the sensitivity becomes larger than the design value, the same frequency change can be obtained with a smaller voltage change, and thus the VCO is vulnerable to noise.

If a master PLL circuit and a data PLL circuit are combined into one set to be integrated into an LSI, the VCO is also reduced to two.
You need one. As described above, the VCO is an oscillator that generates a clock signal having a frequency proportional to the value (analog value) of the input voltage, and is easily affected by fluctuations in power supply voltage, fluctuations in installation potential, noise, etc. Depending on the position, two VCOs may interfere with each other and stable operation may not be obtained. Further, the power consumption of the output terminal of the VCO is proportional to fCV ² where C is the output capacitance, V is the high-level voltage value, and f is the frequency of the output clock signal, and two VCOs are placed in a limited space. When placed and operated at high frequencies, the heat generation may reach the limit. That is, it is disadvantageous to use two VCOs as the clock frequency increases, aiming at high-speed data transfer.

Further, if a PLL circuit is constructed with one VCO, when V is changed from information reproduction to information recording, V
The phase change of the output frequency of CO is small, the frequency abnormality detection is performed to monitor whether the data PLL circuit is operating at an abnormal frequency, and the reference frequency signal is obtained after the frequency abnormality is detected. Need to be done.

Therefore, the present invention can be configured by one VCO having a CMOS structure, and its response characteristic can be adjusted in accordance with the variation in the sensitivity of the VCO.
Moreover, the PL can be used without impairing the function of the conventional PLL circuit.
An object of the present invention is to provide a PLL circuit capable of stabilizing the operation of the L circuit and an information processing device using the PLL circuit.

A further object of the present invention is to provide a PLL circuit which can be downsized and can save power, and can be shortened in development period and development cost.

[0029]

The PLL circuit of the present invention comprises:
A PLL circuit for generating a clock signal of a predetermined frequency used when recording and reproducing information on an information recording medium, comparing the phases of a reference clock signal and the clock signal, and based on the phase difference. A second phase difference signal based on the phase difference obtained by comparing the phases of the first output means for outputting the first phase difference signal, the reproduction clock signal reproduced from the information recording medium, and the clock signal. When outputting information to the information recording medium, the first output means is selected, and when reproducing information from the information recording medium, Based on the selection means for selecting the second output means and the phase difference signal output from the one output means selected by the selection means,
And a clock signal generating means for generating the clock signal of the predetermined frequency.

Further, the PLL circuit of the present invention comprises a voltage controlled oscillator for generating a clock signal of a predetermined frequency used when recording and reproducing information on an information recording medium, a reference clock signal, and the voltage controlled oscillator. From the binarized reproduction information read from the information recording medium, and a first output means for comparing the phase with the clock signal output from the information recording medium and outputting a first phase difference signal based on the phase difference. Second output means for comparing the phases of the extracted clock signal and the clock signal output from the voltage controlled oscillator and outputting a second phase difference signal based on the phase difference;
Selecting means for selecting one of the output means and the second output means, and for recording the information on the information recording medium, the first output means is selected to record the information. When the information is reproduced from the medium, the first control means for controlling the selecting means so as to select the second output means, and the voltage control when the second outputting means is selected by the selecting means Comparing the frequency of the clock signal output from the oscillator and the frequency of the reference clock signal,
Frequency abnormality detecting means for detecting a frequency abnormality of the clock signal output from the voltage controlled oscillator, and when the frequency abnormality detecting means detects a frequency abnormality, selects the first output means for the selecting means. And a second control unit that controls the selection unit to select the second output unit after a predetermined time from when the frequency abnormality detection unit no longer detects the frequency abnormality. Filter means for smoothing the phase difference signal output from the selected output means and outputting the control voltage of the voltage controlled oscillator.

Further, the PLL circuit of the present invention has a voltage controlled oscillator for generating a clock signal of a predetermined frequency used for recording and reproducing information on an information recording medium, and a reference clock signal at a predetermined frequency division ratio. Dividing means for dividing and outputting a divided clock signal, the divided clock signal output from the dividing means and the clock signal output from the voltage controlled oscillator are compared in phase, and the phase difference is obtained. First based on
Of the phase difference signal, the clock signal extracted from the binarized reproduction information read from the information recording medium, and the phase of the clock signal output from the voltage controlled oscillator. And a second output means for outputting a second phase difference signal based on the phase difference, and a selection means for selecting one of the first output means and the second output means. Selecting means for selecting the first output means when recording information on the information recording medium, and selecting the second output means when reproducing information from the information recording medium And a frequency dividing timing based on a clock signal output from the voltage controlled oscillator for the frequency dividing means when the second output means is selected by the selecting means. The divided signal divided by And a filter means for smoothing the phase difference signal output from the output means selected by the selecting means and outputting the control voltage of the voltage controlled oscillator. It is characterized by having done.

The information processing apparatus of the present invention is an information processing apparatus for recording and reproducing information on an information recording medium based on a clock signal of a predetermined frequency output from one voltage controlled oscillator. Reading from the information recording medium, first output means for comparing the phases of the reference clock signal and the clock signal output from the voltage controlled oscillator, and outputting a first phase difference signal based on the phase difference. A second phase difference signal that compares the phases of the clock signal extracted from the output binarized reproduction information with the clock signal output from the voltage controlled oscillator, and outputs a second phase difference signal based on the phase difference. Output means, a selection means for selecting one of the first output means and the second output means, and the first output when recording information on the information recording medium. hand Is selected and the information is reproduced from the information recording medium, the control means for controlling the selecting means to select the second output means and the position output from the output means selected by the selecting means. The phase difference signal is smoothed according to a predetermined cutoff frequency, and the filter means for outputting the control voltage of the voltage controlled oscillator, and the cutoff frequency of the filter means are changed to input / output response characteristics of the voltage controlled oscillator. And adjusting means for adjusting.

The information processing apparatus of the present invention is an information processing apparatus for recording and reproducing information on an information recording medium based on a clock signal of a predetermined frequency output from one voltage controlled oscillator. Reading from the information recording medium, first output means for comparing the phases of the reference clock signal and the clock signal output from the voltage controlled oscillator, and outputting a first phase difference signal based on the phase difference. A second phase difference signal that compares the phases of the clock signal extracted from the output binarized reproduction information with the clock signal output from the voltage controlled oscillator, and outputs a second phase difference signal based on the phase difference. Output means, a selection means for selecting one of the first output means and the second output means, and the first output when recording information on the information recording medium. hand Is selected to reproduce the information from the information recording medium, the first control unit controls the selection unit to select the second output unit, and the selection unit selects the second output unit. And a frequency abnormality detecting means for detecting a frequency abnormality of the clock signal output from the voltage controlled oscillator by comparing the frequency of the clock signal output from the voltage controlled oscillator with the frequency of the reference clock signal. When the frequency abnormality detecting means detects a frequency abnormality, the selecting means is controlled to select the first output means, and the frequency abnormality detecting means stops detecting the frequency abnormality for a predetermined time. Second control means for controlling the selection means to select the second output means later, and a phase difference output from the output means selected by the selection means. Performs smoothing No., characterized by comprising a filter means for outputting a control voltage of the voltage controlled oscillator.

Further, the information processing apparatus of the present invention is an information processing apparatus for recording and reproducing information on an information recording medium based on a clock signal of a predetermined frequency output from one voltage controlled oscillator. A dividing means for dividing the reference clock signal by a predetermined dividing ratio to output the divided clock signal, a divided clock signal outputted from the dividing means, and a clock outputted from the voltage controlled oscillator. A first output means for comparing the phase with the signal and outputting a first phase difference signal based on the phase difference; and a clock signal extracted from the binarized reproduction information read from the information recording medium. And a clock signal output from the voltage controlled oscillator, and outputs a second phase difference signal based on the phase difference between the clock signal output from the voltage controlled oscillator, the second output means, the first output means, and the second output means. Output Selecting means for selecting any one of the stages, and when recording information on the information recording medium, selecting the first output means and reproducing information from the information recording medium, First control means for controlling the selecting means to select the second output means; and when the selecting means selects the second output means, the voltage control oscillator is supplied to the frequency dividing means from the voltage controlled oscillator. Second control means for controlling so as to output a frequency-divided signal that is frequency-divided at frequency-division timing based on the clock signal that is output, and the phase difference output from the output means selected by the selection means. And a filter means for smoothing the signal and outputting the control voltage of the voltage controlled oscillator.

[0035]

The dividing means divides the reference clock signal by a predetermined dividing ratio to output the divided clock signal, and the first outputting means outputs the divided clock signal and the voltage controlled oscillator. A clock that is compared with the phase of the clock signal, outputs a first phase difference signal based on the phase difference, and is extracted from the binarized reproduction information read from the information recording medium by the second output means. When a signal is compared with the phase of a clock signal output from the voltage controlled oscillator and a second phase difference signal based on the phase difference is output to record information on the information recording medium, When the first output means is selected and information is reproduced from the information recording medium, the second output means is selected and the phase difference signal output from the selected output means is filtered by the filter means. Through the specified cutoff frequency Smoothing is performed, the control voltage of the voltage controlled oscillator is output, and the cutoff frequency of the filter means is changed in accordance with the input / output response characteristics of the voltage controlled oscillator to adjust the variation in the sensitivity of the voltage controlled oscillator. it can.

When the second output means is selected, the frequency of the clock signal output from the voltage controlled oscillator is compared with the frequency of the reference clock signal,
A frequency abnormality of the clock signal output from the voltage controlled oscillator is detected, and when the frequency abnormality is detected, the first output unit is controlled to be selected, and after a predetermined time from when the frequency abnormality is not detected. By controlling the second output means to be selected, even if a frequency abnormality occurs during information reproduction, a clock signal that serves as a reference during information reproduction can be obtained, and the operation of the PLL circuit is stabilized. It becomes possible.

When the second output means is selected,
By controlling the frequency dividing means to output a frequency-divided signal that is frequency-divided at frequency-dividing timing based on the clock signal output from the voltage-controlled oscillator, information reproduction to information recording are performed thereafter. At this time, the phase change of the clock signal output from the voltage controlled oscillator can be reduced, and the operation of the PLL circuit can be stabilized.

Further, since each means of the PLL circuit is composed of a one-chip LSI composed of CMOS elements, the circuit can be downsized and power can be saved, and the development period and the development cost can be reduced. .

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 schematically shows the structure of an optical disk device. This optical disk device records information (data write) on the optical disk 1 using focused light,
Alternatively, reproduction of recorded information (data read)
Is to do.

The optical disc 1 is formed by coating a metal coating layer of tellurium, bismuth or the like in a donut shape on the surface of a disk-shaped substrate made of, for example, glass or plastic, and is substantially constant in the radial direction. A plurality of tracks for recording information at a density are provided, and information is recorded by changing the frequency of a clock signal used for recording information according to the radius of the tracks. In addition, such a recording method is applied to MCAV (Modified Constant A).
It is referred to as an integer velocity).

This optical disc 1 has a spindle motor 2
By, for example, rotating at a constant speed. The spindle motor 2 is controlled by a spindle motor control circuit 3.

Recording and reproduction of information with respect to the optical disk 1 are performed by the optical head 2. In this optical head 4, an objective lens (not shown) is supported by a wire or a leaf spring, and this objective lens is driven by a drive coil (not shown) in the focusing direction (optical axis direction of the lens) and the tracking direction (orthogonal to the optical axis of the lens). Direction).

Further, the laser driving circuit 5 drives a semiconductor laser oscillator (not shown) in the optical head 4 to emit a laser beam, and this laser beam is passed through a collimator lens (not shown) and a half prism to the objective lens. It is focused and irradiated onto the optical disc 1. Further, the reflected light from the optical disc 1 is guided to a four-part photodetector (not shown) via the objective lens, the half prism, a condenser lens (not shown), and a cylindrical lens.

From the laser driving circuit 5, a current proportional to the emission intensity of laser light is supplied to the semiconductor laser oscillator. A mark is recorded on the optical disk 1 by irradiating it with a laser beam having a light intensity sufficiently higher than that of the laser beam irradiated during reading. The laser light intensity during reading should be such that the recording mark does not deteriorate.

The optical head 4 is fixed to a drive coil of a linear motor 6, the linear motor 6 is connected to a linear motor drive circuit 7, and the drive coil is excited by the linear motor drive circuit 7, The optical head 4 is adapted to move in the radial direction of the optical disc 1.

The linear motor control circuit 8 is connected to the linear motor drive circuit 7 and controls the drive current value, waveform, etc. at the time of seek.

In this way, the optical head 4 is roughly moved in the radial direction of the optical disk 1 by the linear motor 6.
At this time, the speed, position, and moving direction of the linear motor 6 are detected by slits at equal intervals called a scale, for example. The slit spacing of the scale is, for example, about 200μ
In m, one slit cycle can be controlled in four divisions. For example, since the track interval is 1.6 μm, the linear motor is controlled by a scale with an accuracy of about 30 tracks.

The optical head position detector 9 detects the position of the optical head 4 on the optical disk 1. As a method thereof, for example, an absolute speed is detected by blocking light from a light emitting element (not shown) attached to the optical head 4 by a scale, and the position of the optical head 4 is detected by integrating the speed. . Alternatively, a start position detection sensor that detects that the optical head 4 is located at the innermost peripheral position of the optical disc 1, and an end position that detects that the optical head 4 is located at the outermost peripheral position of the optical disc 1. There is also a method of using a sensor or the like.

The tracking control loop includes a tracking error detection circuit 10, a phase compensation circuit 11 and a switch 1.
2, an adder 13, a tracking control circuit 14, and a drive coil (not shown) for moving the objective lens in the optical head 4 in the tracking direction.

The tracking error detection circuit 10 performs operations including addition, subtraction, and division on four outputs from a four-division photodetector (not shown) in the optical head 4 to generate a tracking error signal and phase. It is output to the compensation circuit 11.

The phase compensating circuit 11 functions to stably operate the drive coil for moving the objective lens in the optical head 4 in the tracking direction based on the tracking error signal.

The switch 12 opens and closes in accordance with a control signal from the CPU 50, which will be described later, to disconnect and connect the tracking control loop. The switch 12 has a function of, for example, disconnecting the tracking control loop at the time of seek and connecting the tracking control loop when the optical head 4 finishes moving into the target track.

The adder 13 adds the voltage value of the analog signal output from the phase compensation circuit 11 and the voltage value of the analog signal output from the D / A converter 20 to obtain the analog signal of the voltage value. It is what is output.

The tracking control circuit 14 includes an adder 13
The drive current corresponding to the voltage value of the analog signal output from the device is supplied to the drive coil for moving the objective lens in the optical head 4 in the tracking direction.

The focusing control loop includes a focusing error detection circuit 15, a phase compensation circuit 16, a switch 17, an adder 18, a focusing control circuit 19, and a drive coil (not shown) for moving the objective lens in the optical head 4 in the focusing direction. ).

The focusing error detection circuit 15 performs arithmetic operations including addition, subtraction, and division on four outputs from a four-division photodetector (not shown) in the optical head 4 to generate a focusing error signal, It is output to the compensation circuit 16.

The phase compensating circuit 16 functions to stably operate the drive coil for moving the objective lens in the optical head 4 in the focusing direction based on the focusing error signal.

The switch 17 opens and closes in accordance with a control signal from the CPU 50 to disconnect and connect the focusing control loop. This switch 17
Has a function of, for example, disconnecting the focusing control loop at the time of seek and connecting the focusing control loop when the optical head 4 finishes moving into the target track.

The adder 18 adds the voltage value of the analog signal output from the phase compensation circuit 16 and the voltage value of the analog signal output from the D / A converter 20 to obtain the analog signal of the voltage value obtained. It is what is output.

The focusing control circuit 19 includes an adder 1
The drive current corresponding to the voltage value of the analog signal output from the reference numeral 8 is supplied to the drive coil for moving the objective lens in the optical head 4 in the focusing direction.

The D / A converter 20 converts a digital signal, which is a control signal from the CPU 50, into an analog signal.

The modulator 21 is a formatter 41 which will be described later.
The data to be recorded on the optical disc 1 sent from the device is modulated into a signal suitable for recording, for example, (1-7) RLL modulation data.

The laser drive circuit 5 drives the semiconductor laser oscillator in the optical head 4 with the (1-7) RLL modulation data modulated by the modulator 21.

The crystal oscillator 30 generates a clock signal serving as a reference for the entire apparatus, and outputs a clock signal having an oscillation frequency of 8 MHz, for example.

The PLL circuit 31 is a portion surrounded by a broken line and is made into an LSI and is contained in one package. In this PLL circuit 31, a wafer in which basic cells composed of n-channel and p-channel CMOS transistors are arranged in a grid is prepared in advance, and only a wiring pattern between the basic cells is determined according to a given circuit. , A gate array capable of realizing an LSI, particularly a CMOS gate array. The feature is that compared with other LSIs, only the wiring process is required, so that the development period is greatly shortened and the development cost is low.

The PLL circuit 31 is composed of a master PLL circuit and a data PLL circuit.

The master PLL circuit is mainly composed of the phase comparator 3
4, a filter 32, and a VCO 35.

The phase comparator 34 is a phase comparator used when the input waveform is periodic, and is obtained by dividing the frequency of the clock signal from the crystal oscillator 30, which is the reference clock, and the VCO 35.
It compares the phase of the clock signal output from the frequency-divided one and outputs the phase difference signal with the phase difference as the pulse width. This phase comparator 34 will also be referred to as a pull-in type phase comparator 34 in the following description.

The filter 32 is mainly composed of a capacitor and a resistor, and executes a low-pass filtering process in which only the low-frequency band of the phase difference signal output from the phase comparator 34 is passed and smoothed. is there.

The VCO 35 outputs a clock signal having a frequency proportional to the voltage value of the output signal of the filter 32, that is, the master clock signal MCLK.

As described above, the master PLL circuit compares the phase of the signal obtained by dividing the clock signal of the constant cycle obtained from the crystal oscillator 30 with high accuracy and the signal obtained by dividing the clock signal which is the output from the VCO 35. The feedback loop is configured so that the phase difference becomes “0”.

The data PLL circuit is mainly composed of the phase comparator 3
6, a filter 32, and a VCO 35.

The phase comparator 36 is a phase comparator used when the input waveform is an aperiodic signal, that is, a signal with missing teeth.
Output clock from CO 35 and binarization circuit 39 described later
It compares the phase with the binarized signal from and outputs an output signal (phase difference signal) corresponding to the phase difference. A phase comparator having such a function is called a lock-in type phase comparator.

The filter 32 is mainly composed of a capacitor and a resistor, and executes a low-pass filtering process for passing and smoothing only the low-frequency band of the output signal output from the phase comparator 36. .

The VCO 37 outputs a clock signal having a frequency proportional to the voltage value of the output signal from the filter 32.

As described above, the data PLL circuit is obtained by binarizing the reproduction signal read from the optical disk 1
For example, a feedback loop is configured such that the rising edge of the binarized signal and the clock signal output from the VCO 35 are compared in phase, and a feedback loop is configured so that the phase difference becomes almost “0” and synchronized with the reproduction signal. To obtain the clock signal.

The reproduction amplifier 38 amplifies a reproduction signal from a photodetector (not shown) in the optical head 4, and the amplified reproduction signal is sent to the binarization circuit 39.

The binarization circuit 39 binarizes the reproduction signal sent from the reproduction amplifier 38 and outputs a binarized reproduction signal (binarization signal). That is, a slice level control signal for controlling the slice level is generated based on the phase difference signal output from the phase comparator 36, and the slice level control signal is used to reproduce the slice level control signal while maintaining an appropriate slice level voltage. Amplifier 3
The binarization is performed on the reproduction signal sent from the No. 8. As another method of binarizing, there is also a method of differentiating the reproduced signal from the reproducing amplifier 38 twice and setting the zero-cross point of the signal as the inversion timing of the binary signal.

Here, the method of controlling the slice level is described in, for example, Japanese Patent Application No. 6-76358, and therefore its explanation is omitted here.

The binarized signal output from the binarization circuit 39 is input to the data PLL circuit of the PLL circuit 31. Here, in the case of mark length recording, a clock signal phase-synchronized with the edge of the binary signal, A binary signal synchronized with the timing is output.

The clock signal output from the PLL circuit 31 and, for example, a binarized signal which is (1-7) RLL modulated data are input to the demodulator 40 to demodulate the binarized signal. is there. Here, RLL (Run Length Limit)
ted) modulated data is "1" in the data string.
The number of "0s" between "1" and "1" is limited, and the sequence of "1" and "1" does not occur. "0" between "1" and "1"
In the case of (1-7) RLL modulation data, the number is 1 to 7. Therefore, 2 bits of data before RLL modulation are converted to 3 bits when RLL modulation is performed. Demodulator 40
Then, based on such a principle, the reproduced data obtained by demodulating the binarized signal output from the PLL circuit 31 is output, and the clock signal for determining the reproduced data is output. The clock signal output from the demodulator 40 is synchronized with the clock signal output from the PLL circuit 31.

The formatter 41 receives the reproduced data from the demodulator 40 and a clock signal for discriminating the reproduced data, and converts the reproduced data into various sync codes.
The error correction code, user data, etc. are separated. That is, the reproduction data is composed of a plurality of blocks, and each block is an array of various synchronization codes, error correction codes, user data, etc. according to a predetermined data format. In a specific example, for example, 12
It shows the case of an inch optical disc.

In FIG. 2, a header preamble HPA is provided at the beginning of one block, which is a 24-byte synchronization pattern for setting the reception synchronization timing of this block. The specific pattern is (1-7)
When expressed as RLL modulated data, "1001001"
“00100” is repeated 24 times.
Note that all the patterns shown below are expressed as (1-7) RLL modulation data.

An address mark AM is provided next to the header preamble HPA, which is a 1-byte synchronization code indicating the start of the subsequent block ID number ID1.
The specific pattern is "0100000010"
Is. After the block ID number ID1, similarly, the address mark AM and the block ID number ID2, the address mark AM and the block ID number ID3, and the address mark AM and the block ID number ID4 follow. still,
The block ID numbers ID1 to ID3 each have 40 bytes, while the block ID number ID4 has 17 bytes.

For example, the block ID number ID4 includes an 8-byte ID number IDNB and an 8-byte ID number I.
ND is divided into 1-byte post-preamble IDPA. The pattern of the post preamble IDPA is “100100100100”.

The 156 bytes so far are the pre-format area, which is the area previously written.

The written flag WF is an 8-byte flag, and when the recorded data is recorded in a data field described later and then the recorded data is read out for collation or the like (during read-after-write), "10010010010".
The flag of the pattern in which "0" is repeated eight times is written.

A data area of 4838 bytes follows the written flag WF. This data area is composed of a data preamble DPA, a data mark DM, and a data field.

The data preamble DPA is a 17-byte synchronization pattern, and its concrete pattern is "10010".
0100100 ”has been repeated 17 times. The data mark DM is a sync code of 8 bytes which indicates the start of the data field. The specific pattern is “1010101010101001001001.
"001" is repeated four times.

The data field is an area where the actual data is written, and the user data and error correction code EC
This is a 4813-byte area in which C and the synchronization code Rsync are written.

The data field has a format as shown in FIG. That is, 38 bytes of user data and 1-byte synchronization code Rsync are set to 1 in this order.
123 sets are continuously formed, and a 16-byte error correction code ECC area is provided at the end.

The data format of one block is composed of 5011 bytes as described above. The reproduction data is composed of a plurality of blocks, and normally, a blank area (GAP) of 95 bytes or larger exists between the blocks.

Returning to the explanation of FIG. The formatter 41 obtains the reception timing and the like from the synchronization code, sends them to the buffer controller 42 via the bus 53, sends only the error correction code and the user data to the buffer memory 43, and accumulates them here. ing.

When the buffer controller 42 receives the reception timing from the farmer 41, it controls the user data and the like stored in the buffer memory 43 via the bus 53 to the protocol controller 44, and the protocol controller 44 sends them to the optical disk device. To an external device (not shown), and the external device receives the data read from the optical disc 1.

The CPU 50 controls the entire apparatus. Further, the frequency division ratio corresponding to the frequency of the clock signal according to the radius of the track on the optical disk 1 accessed by the optical head 4 is set in the PLL circuit 31.

The memory 51 stores a control program for this apparatus and the like, and the CPU 50 carries out a control operation according to the program. Further, the division ratio corresponding to the frequency of the clock signal according to the radius of the track of the optical disc 1 is also stored.

The error detection circuit 52 corrects an error by an error correction code ECC (Error Correction Code) in the reproduction data or adds an error correction code ECC to the recording data to detect an error in the reproduction information and the recording information. , To make corrections.

Data and the like are exchanged between the CPU 50 and each of the above-mentioned components via the bus 53.

Data (recording data) for recording on the optical disc 1 is sent to the protocol controller 44 from an external device of this device. The data sent to the protocol controller 44 is sent to the buffer memory 43 and stored therein under the control of the buffer controller 42.

The formatter 41 receives the data to be recorded on the optical disk 1 via the bus 53, adds various synchronization codes, the error correction code ECC added in the error detection circuit 52, and the like, as shown in FIG. The data format is configured and transmitted to the modulator 21.

FIG. 3 schematically shows a configuration example of the PLL circuit 31, and more specifically shows the PLL circuit 31 shown in FIG.

The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 3, the clock signal FCLK having a constant frequency output from the crystal oscillator 30 is the M frequency divider 7
The value is input to 0 and is divided according to the value of the division ratio M. The value of the frequency division ratio M is a natural number and is set from the CPU 50 shown in FIG. 1 via the bus 53 and the register 60.
It is provided to the M divider 70 in a 1-bit binary number format. The upper limit of the frequency division ratio M is determined by the number of bits when the value of the frequency division ratio M is given from the CPU 50. The clock signal output from the M divider 70 has a cycle that is M times the cycle of the clock signal output from the crystal oscillator 30.

The pull-in type phase comparator 34 and the lock-in type phase comparator 36 are switched by the signal PULLIN1 output from the output terminal of the 4-input NAND circuit 71. That is, the signal PULLIN1 is "1".
In the case of, the pull-in type phase comparator 34 is selected (that is, the master PLL circuit is selected), the data write state is set, and in the case of “0”, the lock-in type phase comparator 36 is selected ( That is, the data PLL circuit is selected), and the data read state is set.
Further, the signal PULLIN0 obtained by inverting the signal PULLIN1 output from the output terminal of the 4-input NAND circuit 71 by the inverter circuit 72 switches the constant of the filter 32 (described later).

The pull-in type phase comparator 34 includes the M divider 7
The clock signal MLOAD1 obtained by dividing the clock signal FCLK from the crystal oscillator 30 by M at 0 and VCO3
5, the clock signal VCLK output from
The clock signal CLK divided by k is further divided by 2N
The phase comparison is performed with the clock signal NLD0 divided by 2 by 4 and the pull-in charge signal CHGP and the pull-in discharge signal DISP are output. The clock signal CLK is also input to the pull-in type phase comparator 34 as a timing signal for its operation. The clock signals MLOAD1 and MLOAD0 are in an inverse relationship with each other.

The pull-in charge signal CHGP means a charge signal of the pull-in type phase comparator 34, and a VCO control voltage VCO input to the VCO 32 is input to a charge holding capacitor (not shown in FIG. 2) in the filter 32.
This is a signal for charging in the direction in which IN rises, and the amount of charging is proportional to the width of the charge signal.

The pull-in discharge signal DISP is
In the sense of a discharge signal of the pull-in type phase comparator 34, V is applied to the charge holding capacitor in the filter 32.
This is a signal for charging (hereinafter referred to as discharging) in a direction in which the VCO control voltage VCOIN input to the CO 32 drops, and the amount of discharging is proportional to the width of the discharge signal.

The lock-in phase comparator 36 performs a phase comparison between the clock signal CLK from the k frequency divider 73 and the differential binary signal, and the clock signal CLK is synchronized with the phase of the differential binary signal. , Lock-in charge signal CH
It outputs GR and a lock-in discharge signal DISR. Further, the reproduced binary signal DATA synchronized with the clock signal CLK is output.

The lock-in charge signal CHGR means a charge signal of the lock-in type phase comparator 36,
A VCO control voltage V input to the VCO 32 is input to a charge holding capacitor (not shown in FIG. 2) in the filter 32.
It is a signal for charging in the direction of increasing COIN, and the amount of charging is proportional to the width of the charging signal.

Lock-in discharge signal DISR
Means a discharge signal of the lock-in type phase comparator 36, and the VCO control voltage VCOIN input to the VCO 32 is input to the charge holding capacitor in the filter 32.
Is a signal that charges (that is, discharges) in such a direction that the voltage drops, and the amount of discharge is proportional to the width of the discharge signal.

The filter 32 has a pull-in charge signal C.
HGP, pull-in discharge signal DISP, lock-in charge signal CHGR, lock-in discharge signal DISR, signal PULLIN0 are input, and VCO
The control voltage VCOIN is output.

The VCO 35 is a VCO control voltage VCOIN.
The clock signal VCLK having a frequency proportional to is output.

The k frequency divider 73 frequency-divides the clock signal VCLK from the VCO 35 by k and outputs the clock signal CLK. The frequency division ratio k is a natural number of 1, 2, 4, or 8, and is used from the CPU 50 shown in FIG.
It is set via 0, and is divided by the k-divider 73 with 2-bit data
Given to.

The 2N frequency divider 74 frequency-divides the clock signal CLK by 2N and outputs the clock signals NLD0 and NLD1. The clock signals NLD0 and NLD1 are inverse to each other. The frequency division ratio N is the CPU 5 shown in FIG.
The clock signal CLK is set from 0 to 2 via the bus 53 and the register 60, for example, as 8-bit data.
Divide by N.

The frequency check circuit 75 has a control signal E
RLVL1, ERLVL2, and ERCHINH are input, and a clock signal FCLK from the crystal oscillator 30 which is a reference clock signal and a clock signal MLOAD1 obtained by dividing the clock signal FCLK from the crystal oscillator 30 by the M divider 70 by M. , M frequency divider 70 divides the clock signal FCLK to obtain a plurality of frequencies of clock signals M01 to M10, and a 2N frequency divider 74 outputs a clock signal NLD1 to generate a signal MLO.
AD0 is input. In the frequency check circuit 75, when the data PLL circuit is selected by the PLL circuit 31 at the time of reproducing information and the clock signal CLK that is phase-synchronized with the reproduced binary signal is output, the clock signal CLK has an abnormal frequency. It is checked whether it is not operating, and when a frequency error is detected, the frequency abnormality detection signal ERRSO
Is output. At this time, the control signal ERL
VL1 and ERLVL2 specify a range in which a frequency abnormality is determined. The control signal ERCHINH is a frequency abnormality detection signal ERRSO when a frequency error is detected.
Is a gate signal of the signal PLLER necessary for generating The control signals ERLVL1, ERLVL2,
ERCHINH is from the CPU 50 shown in FIG. 1 to the bus 5
3, input via the register 60.

The frequency abnormality detection signal ERR from the frequency check circuit 75 is applied to the input terminal of the 4-input NAND circuit 71.
SO, a signal CMDPLIN0 which becomes “0” when the pull-in type phase comparator 34 is forcibly selected, a signal WGATE0 which becomes “0” at the time of data writing, and a signal output from the NAND circuit 76 are input.

The input terminal of the NAND circuit 76 is "1" during the blank area GAP shown in FIG.
Signal SPACEA and a gate signal SPACEEN1 that validates the signal SPACEA are input to the NAND circuit 7
A signal which becomes "0" is output from the output terminal of 6 during the effective blank area GAP.

Therefore, the signal PULLIN1 output from the NAND circuit 71 is the frequency abnormality detection signal ERRSO,
It becomes "0" only when the signal CMDPLIN0 and the output signal from the NAND circuit 76 are all "1". In other words, in other words, when a frequency error is detected, when the pull-in type phase comparator 34 is forcibly selected, at the time of data writing, or in any of the gap areas GAP, the pull-in type phase comparator 34 is selected. Is to be selected.
The signal CMDPLIN0 and the signal SPACEEN1 are
It is input from the CPU 50 shown in FIG. 1 via the bus 53 and the register 60.

The register 60 is the CPU 50 shown in FIG.
To write various control signals, which are also transmitted from the CPU 50 via the bus 53, from the various data transmitted from the CPU 50 via the bus 53, that is, the chip select signal CS for selecting the register 60, the address of the register 60, and the data to the register 60. Based on the port write signal WR of
Dividing ratio k, N, M, signal ERCHINH, ERLVL
1, ERLVL2, CMDPLIN0, SPACEEN
1 and the like are output respectively.

FIG. 4 shows a concrete example of the circuit configuration of the VCO 35. This circuit is publicly known and its detailed description is omitted.

In FIG. 4, this circuit has a p-channel MOS transistor and an n-channel M, which are shown as a legend.
CMOS (Complementary MOS) that is composed of OS transistors, and is actually a combination of p-channel MOS transistors and n-channel MOS transistors
Is often used.

In FIG. 4, terminals of the respective anodes of the capacitors C1 to C11 and p-channel MOS transistors (hereinafter also simply referred to as transistors) T1 to T1.
The power source voltage VD is connected to the respective source terminals of 3, T49 and T50, and the power source voltage VD is, for example, 5
V.

The cathode terminals of the capacitors C1 to C11, the gate terminals of the transistors T1 to T13, the drain terminals of the transistors T1 to T2,
The drain terminal of an n-channel MOS transistor (hereinafter also simply referred to as transistor) T46 is connected. That is, the transistors T1, T2, and T46 form a current mirror circuit.

The source terminals of the p-channel MOS transistors T14 to T23 are connected to the drain terminals of the transistors T4 to T13, respectively. The drain terminals of the transistors T14 to T23 are connected to the drain terminals of the n-channel MOS transistors T24 to T33, respectively. The gate terminals of the transistors T15 and T25 are connected to the connection points of the drain terminals of the transistors T14 and T24, respectively.
The respective gate terminals of the transistors T16 and T26 are connected to the connection points of the respective drain terminals of T1 and T25, and hereinafter, similarly, the transistors T17 and T27, the transistors T18 and T28, and the transistors T19 and T2.
9, transistors T20 and T30, transistor T21
, T31, transistors T22 and T32, and transistors T23 and T33, the gate terminals of the transistors that form the combination are connected to the connection points of the drain terminals of the transistors of the preceding combination.

The source terminals of the transistors T24 to T33 are connected to the drain terminals of the n-channel MOS transistors T35 to T44, and the drain terminal of the transistor T3 is connected to the drain terminal of the n-channel MOS transistor T34. The gate terminals of the transistors T34 to T44 are connected to each other, and the gate terminals of the transistors T34 to T44 are connected to the anode terminals of the capacitors C12 to C22, respectively.

The cathode terminals of the capacitors C12 to C22 and the source terminals of the transistors T34 to T44 are connected to each other, and the source terminals of the n-channel MOS transistors T47, T48 and T52 are connected to the connection points. The ground voltage, that is, 0v, is connected to the connection point.

To the connection points of the drain terminals of the transistors T23 and T33, the gate terminal of the transistor T49 and the gate terminal of the n-channel MOS transistor T51 are connected, and the source terminal of the transistor T51 and the drain terminal of the transistor T52 are connected. It The drain terminal of the transistor T50, the drain terminal of the transistor T51, and the drain terminal of the transistor T49 are connected to each other.
4, the gate terminals of T24 are connected.

Transistors T50, T52, T47, T
A signal CL is input to each of the gate terminals of 48. This signal CL is normally a logical value "1", but V
This signal is "0" when the oscillation from the CO35 is stopped.

The source terminal of the transistor T46 is connected to the drain terminals of the transistors T47 and T48. The VCO control voltage V is applied to the gate terminal of the transistor T46.
COIN is input.

The voltage-controlled clock signal VCLK is output from the connection point of the drain terminal of the transistor T50, the drain terminal of the transistor T51, and the drain terminal of the transistor T49.

The capacitors C1 to C22 are also composed of CMOS.

FIG. 5 schematically shows the input / output characteristics of the VCO 35, and the vertical axis shows the output clock signal VCL.
K frequency f [MHz], horizontal axis is VCO control voltage VCO
The voltage value Vin [V] of IN is shown.

As shown in FIG. 5, the frequency f of the output clock signal is almost proportional to the input voltage value v. The proportional constant S at this time is called the sensitivity of the voltage controlled oscillator, and S = Δf / Δv. When this input / output characteristic can be represented by a straight line, S has a constant value, but when it has a curve, the sensitivity S takes a different value depending on v. The sensitivity S is an important value when designing a PLL loop.

Further, the input / output characteristics vary among the manufactured VCOs as shown by the curves L1, L2 and L3. That is, the same VCO control voltage Vin
, The sensitivity S is different, and as a result, the frequency f of the clock signal to be output rises above and below the curve L1 (in the case of curve L2) or decreases (curve L3). in the case of). Further, in the case of the VCO having the CMOS structure as shown in FIG. 4, the characteristic variation tends to be large as compared with, for example, a system such as an emitter coupled multivibrator.

FIG. 6 shows a concrete example of the lock-in type phase comparator 36.

In FIG. 6, the lock-in type phase comparator 3
6 is mainly three D type flip-flop circuits FF
1, FF2, FF3.

The voltage VD that always inputs the logical value "1" to the data input terminal of the flip-flop circuit FF1.
D is input, and the differential binarized signal is input to its clock input terminal. Also, the reset input terminal has 2
The output terminal of the input AND circuit G1 is connected. The non-inverting output terminal of the flip-flop circuit FF1 is connected to the data input terminal of the flip-flop circuit FF2, and further 3
It is connected to two of the input terminals of the input NAND circuit G2.

The clock signal C output from the k frequency divider 73 is applied to the clock input terminal of the flip-flop circuit FF2.
LK is input, and its inverting output terminal is connected to another input terminal of the NAND circuit G4. Flip-flop circuit FF
The non-inverting output terminal of 2 is connected to the data input terminal of the flip-flop circuit FF3, and further, the reset input terminal of the flip-flop circuit FF3 and the 3-input AND circuit G3.
Is connected to one input terminal of the two-input NAND circuit G4.

The clock signal obtained by logically inverting the clock signal CLK by the inverter circuit G5 is input to the clock input terminal of the flip-flop circuit F3. The inverting output terminal of the flip-flop circuit FF3 is connected to the NAND circuit G4.
Is connected to the other input terminal and one input terminal of the 2-input OR circuit G6.

The output terminal of the NAND circuit G4 is connected to the delay circuit G7 in which four inverter circuits are cascade-connected, and the output of the delay circuit G7 is input to one input terminal of the AND circuit G1.

The signal D is applied to the other input terminal of the OR circuit G6.
ISRWID is input, and the output terminal of the OR circuit G6 is
It is connected to the other input terminal of the AND circuit G3.

The signal PULLIN0 is input to the other input terminal of the NAND circuit G2, and the AND circuit G3.
Is also input to the other input terminals of.

The signal SCLR0 is input to the other input terminal of the AND circuit G1 and the reset input terminal of the flip-flop circuit FF2. It should be noted that the logic value is "0" when the power of the PLL circuit 31 is turned on, but it is a signal which becomes "1" after a lapse of a fixed time from that point, and is usually "1".

The lock-in charge signal CHGR is output from the output terminal of the NAND circuit G2, and the lock-in discharge signal DISR is output from the output terminal of the AND circuit G3.
Is output. Further, the reproduction binarized signal DAT is output from the non-inverting output terminal of the flip-flop circuit FF2.

The signal ISRWID is a signal for setting the time width when the lock-in discharge signal DISR becomes the logical value "1". That is, the signal DISR
When the WID is the logical value "0", the lock-in discharge signal DISR becomes the logical value "1" for the time corresponding to a half clock of the clock signal CLK, and the signal DISRW.
When the ID is the logical value "1", the lock-in discharge signal DISR becomes the logical value "1" for the time corresponding to one clock of the clock signal CLK.

In this way, the lock-in type phase comparator 36
Is a signal that is the source of the VCO control voltage VCOIN, that is, a lock-in charge signal, that detects the phase difference between the rising timings of the differential binarized signal and the clock signal CLK and that corresponds to the phase difference. CHGR,
The lock-in discharge signal DISR is output.

Next, the operation of the lock-in type phase comparator 36 shown in FIG. 6 will be described with reference to the time chart shown in FIG.

In FIG. 7, when the signal SCLR0 is the logical value "1" and the signal DISRWID is the logical value "0", the signal PULLIN0 becomes the logical value "1" and the lock-in type phase comparator 36 is selected. Then, AND circuit G
The output of 1 changes from the logical value "0" to "1", and the reset of the flip-flop circuit FF1 is released. After that, when the differential binarized signal input to the clock input terminal of the flip-flop circuit FF1 rises, a signal having a logical value "1" is output from the non-inverting output terminal of the flip-flop circuit FF1. Then, the lock-in charge signal CHGR output from the output terminal of the NAND circuit G2 becomes the logical value "0". Next, after the signal of the logical value "1" is output from the non-inverting output terminal of the flip-flop circuit FF1, the logical value "0" is output from the inverting output terminal of the flip-flop circuit FF2 by the first rising of the clock signal CLK. The signal is output, and as a result, the lock-in charge signal CHG output from the output terminal of the NAND circuit G2.
R becomes the logical value "1" again.

On the other hand, after the logical value "1" is output from the non-inverting output terminal of the flip-flop circuit FF1,
A signal having a logical value "1" is output from the non-inverted output terminal of the flip-flop circuit FF2 at the first rising of the clock signal CLK, and then the flip-flop circuit FF at the first rising of the clock signal CLK.
A signal of logical value "1" is output from the non-inverting output terminal of No.2. As a result, the reset state of the flip-flop circuit FF3 is released, and at the same time, the lock-in discharge signal DISR becomes the logical value "1". After that, at the first rise of the inverted clock signal CLK (CLKB), a signal of logical value "0" is output from the inverting output terminal of the flip-flop circuit FF3. Then, the signal DISRWID, which is one input signal of the OR circuit G6, has the logical value "0", and therefore the logical value "0" is output from its output terminal.
Signal is output, and as a result, the lock-in discharge signal DISR output from the AND circuit G3 has a logical value "0". At this time, the pulse width of the lock-in discharge signal DISR corresponds to a half clock of the clock signal CLK.

After the signal having the logical value "1" is output from the non-inverting output terminal of the flip-flop circuit FF1, the reproduction 2 is performed in synchronization with the first rising of the clock signal CLK.
The binarized signal DATA is output from the non-inverting output terminal of the flip-flop circuit FF2. At this time, when the output from the non-inverting output terminal of the flip-flop circuit FF2 has the logical value "1", the output terminal of the NAND circuit G4 has the logical value "0", and the signal is delayed through the delay circuit G7. Is input to the AND circuit G1 and is delayed from the logic inversion signal (CLKB) of the clock signal CLK, and the flip-flop circuit FF1 is reset. Therefore, in the flip-flop circuit FF1,
The rising edge can be detected next to the differential binarized signal.

When the signal DISRWID has the logical value "1", the output of the OR circuit G6 always has the logical value "1", so that the lock-in discharge signal DISR changes its logical value at the rising edge of the clock signal CLK. It is in. As a result, the lock-in discharge signal DISR
Has a pulse width corresponding to one clock of the clock signal CLK. Except for this point, the signal DISRWI
This is the same as when D is a logical value "0".

Depending on the above-described characteristics of the VCO 35, the high-level time width and the low-level time width of the clock signal CLK may be different. In such a case, the signal DISRWID is set to "1" to lock. The gain for the in-discharge signal DISR may be halved.

FIG. 8 shows a concrete example of the pull-in type phase comparator 34.

In FIG. 8, the pull-in type phase comparator 34
Are mainly three D-type flip-flop circuits FF4,
It is composed of FF5 and FF6.

The data input terminals of the flip-flop circuits FF4 and FF5 are supplied with the voltage VDD such that the logical value "1" is always input, and the clock input terminal of the flip-flop circuit FF4 is supplied with the M frequency divider 70. Crystal oscillator 30
The clock signal MLOAD1 obtained by dividing the clock signal FCLK from M is divided into M, and the clock signal obtained by dividing the clock signal CLK by 2N by the 2N divider 74 is input to the clock input terminal of the flip-flop circuit FF5. NLDO is input.

The non-inverting output terminal of the flip-flop circuit FF4 is connected to one of the input terminals 1 of the 3-input NAND circuit G10, and is further connected to one input terminal of the 2-input NAND circuit G11.

The non-inverting output terminal of the flip-flop circuit FF5 is connected to the other input terminal of the NAND circuit G11,
Further, it is connected to one input terminal of the 2-input AND circuit G12. The inverting output terminal of the flip-flop circuit FF5 is connected to the other input terminal of the NAND circuit G10.

The output terminal of the NAND circuit G11 is connected to the data input terminal of the flip-flop circuit FF6, and the clock signal CLK is input to the clock input terminal of the flip-flop circuit FF6. The signal SCLR0 is input to the reset input terminal of the flip-flop circuit FF6. Further, the non-inverting output terminal of the flip-flop circuit FF6 is connected to the reset input terminals of the flip-flop circuits FF4 and FF5.

The signal PU is connected to the other input terminal of the NAND circuit G10 and to the other input terminal of the AND circuit G12.
LLIN1 is input, the pull-in charge signal CHGP is output from the output terminal of the NAND circuit G10, and the pull-in discharge signal DISP is output from the output terminal of the AND circuit G12.

Next, the operation of the lock-in type phase comparator 34 shown in FIG. 8 will be described with reference to the time chart shown in FIG.

In FIG. 9, when the signal SCLR0 becomes the logical value "1", the reset of the flip-flop circuit FF6 is released, and the signal PULLIN1 becomes the logical value "1", and the pull-in type phase comparator 34 is selected. Then, the gates of the NAND circuit G10 and the AND circuit G12 are opened. In such an initial state, since the signals of the logical value “0” are output from the respective non-inverting output terminals of the flip-flop circuits FF4 and FF5,
The pull-in charge signal CHGP output from the NAND circuit G10 has a logical value "1", and the pull-in discharge signal DISP output from the AND circuit G12 has a logical value "0".

In this state, when the clock signal MLOAD1 rises, a signal of logical value "1" is output from the non-inverting output terminal of the flip-flop circuit FF4.
The pull-in charge signal CHGP output from the NAND circuit G10 becomes the logical value "0", and the clock signal NLD0
When the output signal from the inverting output terminal of the flip-flop circuit FF5 becomes "0" due to the rise of the pull-in signal, the pull-in charge signal CHGP becomes the logical value "1" again.

On the other hand, when the non-inverting output terminal of the flip-flop circuit FF5 becomes the logical value "1" due to the rising of the clock signal NLD0, the pull-in discharge signal DISP output from the AND circuit G12 is the logical value "1".
Becomes At this time, since the logical value “0” is output from the output terminal of the NAND circuit G11, the logical value “0” is output from the non-inverting output terminal of the flip-flop circuit FF6 at the first rising of the clock signal CLK. Is output, and the flip-flop circuit FF
4 and FF5 are reset, and a signal of logical value "0" is output from each non-inverting output terminal. As a result, the pull-in discharge signal DISP becomes the logical value "0", and the initial state is restored.

Next, if the clock signal NLD0 rises earlier than the clock signal MLOAD1 rises, and the non-inverting output terminal of the flip-flop circuit FF5 becomes the logical value "1" due to the rise of the clock signal NLD0, the AND circuit G12. The pull-in discharge signal DISP output from the output terminal has a logical value "1". After that, at the first rise of the clock signal MLOAD1, a signal of logical value "1" is output from the non-inverting output terminal of the flip-flop circuit FF4, and a logical value "0" is output from the output terminal of the NAND circuit G11. Therefore, after that, at the first rising of the clock signal CLK, a signal of logical value "0" is output from the non-inverting output terminal of the flip-flop circuit FF6, and the signal resets the flip-flop circuits FF4 and FF5. A signal having a logical value "0" is output from the non-inverting output terminal of the. As a result, the pull-in discharge signal DI
SP has a logical value of "0" and returns to the initial state. During this time,
Since a signal of logical value "0" is output from the inverting output terminal of the flip-flop circuit FF5, the AND circuit G1
The pull-in charge signal CHGP output from 0 has a logical value “1”.

When the signal PULLIN1 has the logical value "1", the gates of the NAND circuits G10 and G12 are closed, and the pull-in charge signal CHGP output from the NAND circuit G10 has the logical value "1" and the AND circuit. The pull-in discharge signal DISP output from G12 has a logical value "0".

In this way, the pull-in type phase comparator 34 detects the phase difference between the rising timings of the clock signal MLOAD1 and the clock signal NLD0,
A signal which is a source of the VCO control voltage VCOIN, that is, a pull-in charge signal CHG corresponding to the phase difference.
P and a pull-in discharge signal DISP are output.

The time chart shown in FIG. 9 shows what happens to the waveforms of the pull-in charge signal CHGP and the pull-in discharge signal DISP when the rising edges of the clock signal MLOAD1 and the clock signal NLD0 occur at various timings. For explanation purposes, the clock signal MLOAD1 and the clock signal N
The rising timing of LD0 is arbitrary.

FIG. 10 shows a concrete circuit configuration of the 2N frequency divider 74.

In FIG. 10, the 2N frequency divider 74 is mainly composed of 4
It is composed of bit binary counter circuits CN1 to CN3.

First, the frequency division ratio N is
8 from ID0 to ID7 from the CPU 50 via the bus 53
Sent as bit data, and these are connected to the input terminals of the inverter circuits G15 to G22, respectively, and the output terminals of the inverter circuits G15 to G22 are connected to the input terminals of the register circuit 60a forming a part of the register 60. To be done. Setting data ID0 to ID7 of the division ratio N
Is the input timing of the control signal IOW21 that is also sent from the CPU 50 via the bus 53.
0a, and at the same time, the division ratio N
Is connected to the data preset input terminals of the counter circuits CN1 to CN3.

A clock signal obtained by logically inverting the clock signal CLK by the inverter circuit G23 is input to each clock input terminal of the counter circuits CN1 to CN3, and the counter circuits CN1 to CN3 are cascaded (series).
It is connected. That is, the carry output of the counter circuit CN1, that is, the signal which becomes "1" only for the period of one clock when the counter value of the counter CN1 becomes maximum is connected to the enable terminal of the counter circuit CN2 at the subsequent stage, and the counter circuit CN2. Becomes operable, and the carry output of the counter circuit CN2 is connected to the enable terminal of the counter circuit CN3 in the subsequent stage.
The counter circuit CN3 becomes operable.

To the input terminal of the NAND circuit G24, the predetermined output terminals of the counter circuits CN1 to CN3 are connected,
The counter circuit CN1 is output from the output terminal of the NAND circuit G24.
When ~ CN3 reaches a predetermined counter value, a signal that becomes "0" for a predetermined time is output. This signal is connected to the data input terminal of the flip-flop circuit FF10,
Further, the frequency division ratio N is input to the load input terminals of the counter circuits CN1 to CN3 and preset for each counter circuit.

In the flip-flop circuit FF10, the signal output from the NAND circuit G24 is supplied to the inverter circuit G24.
In synchronism with the timing of the logic inverted clock signal of the clock signal CLK output from 23, the non-inverted output terminal outputs the clock signal NLD0 obtained by dividing the clock signal CLK by 2N, and the inverted output terminal. Outputs the clock signal NLD1.

Note that the signal SCLRO is input to the reset input terminals of the counter circuits CN1 to CN3, the flip-flop circuit FF10, and the register circuit 60a.
The resetting of the L circuit 31 is released after a certain period of time has passed since the power of the L circuit 31 was turned on.

Next, with reference to FIGS. 11 to 14, a specific example of the circuit configuration of the M divider 70 and the frequency check circuit 75 will be described.

First, the circuit shown in FIG. 11 will be described. The frequency division ratio M is sent to the register 60 from the CPU 50 via the bus 53 as 8-bit data of ID0 to ID7, and these are respectively inverter circuits G30.
~ G37 connected to the input terminal of the inverter circuit G30
Each of the output terminals of G37 to G37 is connected to the input terminals of register circuits 60b and 60c forming a part of the register 60. The setting data ID0 to ID7 of the division ratio M is written in the register circuits 60 and b60c at the input timing of the control signals IOW01 and IOW11 that are also sent from the CPU 50 via the bus 53, and at the same time, the division ratio is output from its output terminal. The set value of M is set to each counter circuit CN4 to CN
6 is input to the data preset input terminal.

The counter circuits CN4 to CN6 are 4-bit binary counter circuits, and are the counter circuit C of FIG.
Cascade connection is performed similarly to N1 to CN3. still,
A voltage VDD that always has a logical value "1" is input to the data preset input terminal of the fourth bit of the counter circuit CN6, and as a result, the counter circuits CN4 to CN
6 constitutes an 11-bit counter.

The reference clock signal F from the crystal oscillator 30 is applied to the clock input terminals of the counter circuits CN4 to CN6.
CLK is input, and from the output terminals of the counter circuits CN4 to CN6, in order from the one having the least significant bit,
Signals M01, M11, M21, M31, M41, M5
1, M61, M71, M81, M91, M10 are output. Further, from the carry output terminal of the counter circuit CN3, when the counter value of the counter circuit CN6 becomes maximum, the signal RC that becomes "1" only for one clock cycle of the clock signal FCLK is output.

Next, FIG. 12 will be described. In FIG. 12, signals RC and M are input to the input terminal of the NAND circuit G25.
01, M21, M31, the signal M11 to the inverter circuit G
A signal logically inverted in 26 is input, and a signal MLD0 which becomes “0” for a predetermined time when the counter value of the counter circuits CN4 to CN6 reaches a predetermined counter value is output from the output terminal thereof. This signal MLD0 is
It is a clock signal having a cycle set by the division ratio M.

The selector circuits SEL1 to SEL3 are data selector circuits each including four circuits for selecting either one of the two data inputs A and B by the select input.

The signal M01 is input to the data input terminal A and the signal M11 is input to the data input terminal B of the first circuit of the selector circuit SEL1. The signal M11 is input to the data input terminal A of the second circuit of the selector circuit SEL1 and the signal M21 is input to the data input terminal B.
Is entered. The signal M21 is input to the data input terminal A and the signal M31 is input to the data input terminal B of the third circuit of the selector circuit SEL1. The signal M31 is input to the data input terminal A of the fourth circuit of the selector circuit SEL1 and the signal M4 is input to the data input terminal B.
1 is input.

The signal M41 is input to the data input terminal A and the signal M51 is input to the data input terminal B of the first circuit of the selector circuit SEL2. The signal M51 is input to the data input terminal A of the second circuit of the selector circuit SEL2, and the signal M61 is input to the data input terminal B.
Is entered. The signal M61 is input to the data input terminal A and the signal M71 is input to the data input terminal B of the third circuit of the selector circuit SEL2. The signal M71 is input to the data input terminal A of the fourth circuit of the selector circuit SEL2, and the signal M8 is input to the data input terminal B.
1 is input.

The signal M81 is input to the data input terminal A and the signal M91 is input to the data input terminal B of the first circuit of the selector circuit SEL3. The signal M91 is input to the data input terminal A of the second circuit of the selector circuit SEL3, and the signal M10 is input to the data input terminal B.
Is entered. The signal M10 is input to the data input terminal A and the signal M01 is input to the data input terminal B of the third circuit of the selector circuit SEL3. The data input terminal A and the data input terminal B of the fourth circuit of the selector circuit SEL3 are grounded.

The signal TST04 is input to the select input terminals of the selector circuits SEL1 to SEL3. This signal TST04 is a signal related to changing the number of rotations of the optical disc 1, and when the number of rotations of the optical disc 1 is slow, the signal MSK used for detecting a frequency abnormality described later is determined to be a frequency abnormality. It is necessary to increase the time width of the window that specifies the range
The switching signal at that time is this signal TST04.

In the selector circuits SEL1 to SEL3, the signal selected by the signal TST04 is the NAND circuit G27, the OR circuit G28, the NOR circuit G29, the NOR circuit G30, the NAND circuit G31, and the eight data inputs. Signals MD01, MD1 for generating the signal MSK by the decoder circuits DEC1, 2 which output data
1, MD21, MD31, MD02, MD12, MD2
2, output MD32.

Next, FIG. 13 will be described. In FIG. 13, the voltage VDD is input to the data input terminal of the flip-flop circuit FF20, the clock signal NLD1 from the 2N frequency divider 74 is input to the clock input terminal thereof, and the inverted output terminal of the flip-flop circuit FF20 is input. Outputs a signal whose logical value becomes "0" at the rising edge of the clock signal NLD1. This signal is input to one data input terminal of the selector circuit SEL4 that selects one of the two data inputs by the select input. The signal MLD output from the NAND circuit G25 of FIG. 12 is applied to the other input terminal of the selector circuit SEL4.
0 is input.

The signal PULLIN1 is input to the data input terminal of the flip-flop circuit FF21, and the signal MLOAD0 described later is input to its clock input terminal.
By the rise of this signal, the flip-flop circuit F
A logical value corresponding to the signal PULLIN1 is output from the output terminal of F21. This signal is the selector circuit SE
It is input to the select input terminal of L4, and the selector circuit SE
From the output terminal of L4, the flip-flop circuit FF21
When the signal output from the output terminal of is "1" (when the pull-in type phase comparator 34 is selected), the signal MLD0
Is output and is "0" (lock-in type phase comparator 3
6 is selected), the signal corresponding to the signal NLD1,
That is, the output signal from the flip-flop circuit FF20 is output.

The output signal of the selector circuit SEL4 is input to the data input terminal of the flip-flop circuit FF22,
The reference clock signal FCLK from the crystal oscillator 30 is input to the clock input terminal of the flip-flop circuit FF22, and at the rising timing thereof, the selector circuit SEL4 is output from the output terminal of the flip-flop circuit FF22.
The signal MLOAD0 of the logical value of the output signal of is output.

The signal MLOAD0 is input to the reset input terminal of the flip-flop circuit FF20 and the load input terminals of the counter circuits CN4 to CN6 of FIG. 11, and the frequency division ratio M is preset. That is, the signal PULLIN1
, The clock signal MLO generated by dividing the reference clock signal FCLK by M by the M divider 70.
Based on the timing of D, the counter circuits CN4 to CN6 of the M divider 70 are preset, and when the logic value of the signal PULLIN1 is "0", the 2N divider 74 is operated at the timing of the clock signal output from the VCO 35. Based on the timing of the clock signal NLD0 output from the M divider 7
The zero counter circuits CN4 to CN6 are preset.

In this way, the lock-in type phase comparator 36
When is selected, the frequency division timing of the M frequency divider 70 is set based on the frequency of the clock signal extracted from the differential binarized signal read from the optical disc 1. It is possible to reduce the phase change of the clock signal when shifting from time to data write.

From the inverting output terminal of the flip-flop circuit FF22, a signal ML obtained by logically inverting the signal MLOAD0.
OAD1 is output, and the signal is logically inverted by the inverter circuit G38 and output as the signal MLOAD0A.

The selector circuit SEL5 selects one of four data inputs by two select inputs.
It is a data select circuit containing a circuit.

4 of the first circuit of the selector circuit SEL5
Each of the data input terminals of the book has a signal M from FIG.
D31, MD21, MD11, MD01 are input, and the signals MD02, MD1 from FIG. 12 are respectively input to the four data input terminals of the second circuit of the selector circuit SEL5.
2, MD22, MD32 are input, and the signals ERLVL0, ERLVL1 are input to the selector input terminals.

The NAND circuits G35 and G3 are selected based on the signals selected by the signals ERLVL0 and ERLVL1 and output from each circuit in the selector circuit SEL5 and the signal MLOAD0 output from the flip-flop circuit FF22.
6. The flip-flop circuit FF23 allows the signal ERLVL to be output from the output terminal of the flip-flop circuit FF23.
A signal MSK of "0" is output during the range of 0, which is determined by ERLVL1 to be a frequency abnormality.

The signal ML is applied to the input terminal of the NOR circuit G37.
When OAD0, MSK, and TST07 are input and all of these signals have a logical value "0", a signal having a logical value "1" is output from the output terminal of the NOR circuit G37. That is,
A frequency abnormality is detected in the NOR circuit G37. The signal output from the NOR circuit G37 is 2
It is input to one data input terminal of a selector circuit SEL6 that selects one of the book data inputs by the select input. The signal TST06 is input to the other input terminal, and the signal TST03 is input to the select input terminal. The signals TST03, TST06, and TST07 are
This is a signal for a function test, and is "0" here during normal operation. Therefore, the output signal of the NOR circuit G37 is directly output as the signal PLLER from the output terminal of the selector circuit SEL6, and when the NOR circuit G37 detects the frequency abnormality, the logical value of the signal PLLER becomes "1". Next, FIG. 14 will be described. 14
In the 4-bit binary counter circuit CN7,
CN8 is connected in cascade, and the counter circuit CN7 has 1
The data preset input terminal of the bit is grounded and always has a logical value of "0". Further, the voltage VDD that always has the logical value "1" is input to the other data preset input terminals of the counter circuit CN7 and the data preset input terminals of 1 to 4 bits of the counter circuit CN8.

The signal MLOADOA of FIG. 13 is input to the respective clock input terminals of the counter circuits CN7 and CN8, and the signal PLLER of FIG. 13 is logically inverted by the inverter circuit G40 and input to their reset input terminals. ing.

Of the output terminals of the counter circuit CN7, the terminal that outputs the counter value corresponding to the second, third, and fourth bits from the least significant bit, and the output terminal of the counter circuit CN8 that is the third from the least significant bit. The three output terminals up to the bit are respectively connected to the six input terminals of the NAND circuit G41.

The output terminal of the NAND circuit G41 is connected to the data input terminal of the flip-flop circuit FF25, and the clock input terminal of the flip-flop circuit FF25 is
The signal MLOADOA is input. The non-inverting output terminal of the flip-flop circuit FF25 is connected to the enable terminal of the counter circuit CN7, and the inverting output terminal is one of the selector circuits SEL10 that selects either one of the two data inputs A and B by the select input. Connected to the input terminal of.

The signal TST22 is input to the other input terminal of the selector circuit SEL10, and the signal TST21 is input to the select input terminal. The signals TST21, T
ST22 is a signal for a function test, which is, for example, "0" here during normal operation. Therefore, from the output terminal of the selector circuit SEL10, the flip-flop circuit F
The output signal from the inverted output terminal of F25 is directly output as the frequency abnormality detection signal ERRSO.

The above-mentioned signal SCLRO is applied to the load input terminals of the counter circuits CN7 and CN8,
It is input to the reset input terminal of the flip-flop circuit FF25.

With such a circuit configuration, a frequency abnormality is detected and the logic value of the signal PLLER in FIG. 13 is "1".
Then, after that, when the frequency abnormality is no longer detected and becomes "0" again, the logical value "0" is maintained for a certain period of time. In the circuit configuration of FIG. 14, from the time when the logical value of the signal PLLER becomes “1” to “0” again until the number of 126 pulses of the signal MLDO as the signal MLOADOA is counted, the frequency abnormality detection signal ERRSO. Is a logical value "0". That is, when the frequency abnormality is detected, the frequency abnormality detection signal ERRSO has the logical value "0".
As a result, the signal PULLIN1 becomes a logical value “1” via the 4-input NAND circuit 71 in FIG. 3, and the pull-in type phase comparator 34 is selected, but a predetermined frequency is detected from the time when the frequency abnormality is no longer detected. When the time has elapsed, the pull-in type phase comparator 34 shifts to the lock-in type phase comparator 36.
It is designed to switch to. As described above, the timing for switching from the pull-in type phase comparator 34 to the lock-in type phase comparator 36 is provided with a margin because it is necessary to sufficiently charge the charge holding capacitor C50 described later.

Next, the operation of the frequency check circuit 75 will be described with reference to the time charts shown in FIGS.

FIG. 15 shows the case where the signal TST04 for switching the time width of the window of the signal MSK designating the range judged as the frequency abnormality is the logical value "0", that is, the window of the small time width. . That is, in the selector circuits SEL1 to SEL3 of FIG. 12, the signals M01, M11, M2 selected by the signal TST04 are selected.
Signals MD01, MD11, MD21, M for generating the signal MSK based on 1, M31, M41, M51, etc.
D31, MD02, MD12, MD22, MD32 are generated, and further, in the selector circuit SEL5 of FIG. 13, one of the four types of window widths is determined by the signals ERLVLO, ERLVL1 and the signal MSK is output. The signal MSK in FIG. 15 is a signal output from the inverting output terminal of the flip-flop circuit FF25 in FIG.

In FIG. 15, for example, the logical value of the signal ERLVL0 is "0" and the logical value of the signal ERLVL1 is "0".
In this case, (ERLVL0, ERLVL1) = (0, 0) is shown.

(ERLVL0, ERLVL1) = (0,
0), signals M01, M11, M21, M31, M
The logical values of 41 and M51 are "1", "1", and "0", respectively.
First clock signal F after becoming "0""1""1"
At the rising edge of CLK, the logic value of the signal MSK becomes “1”, and the signals M01, M11, M21, M31, M41,
The logical values of M51 are "0", "0", "0", and "1", respectively.
First clock signal FCLK after becoming "0""0"
At the rising edge of, the logical value of the signal MSK becomes "0",
The time width of the window is 21 of the clock signal FCLK.
This corresponds to the length of the cycle.

(ERLVL0, ERLVL1) = (0,
In the case of 1), signals M01, M11, M21, M31, M
The logical values of 41 and M51 are "1", "1", and "0", respectively.
The first clock signal F after becoming "1""0""1"
At the rising edge of CLK, the logic value of the signal MSK becomes “1”, and the signals M01, M11, M21, M31, M41,
The logical values of M51 are "0", "0", "0", and "0", respectively.
First clock signal FCLK after becoming "1" or "0"
At the rising edge of, the logical value of the signal MSK becomes "0",
The time width of the window is 37 of the clock signal FCLK.
This corresponds to the length of the cycle.

(ERLVL0, ERLVL1) = (1,
0), signals M01, M11, M21, M31, M
The logical values of 41 and M51 are "1", "1", and "0", respectively.
After becoming "0", "0", "1", the first clock signal F
At the rising edge of CLK, the logic value of the signal MSK becomes “1”, and the signals M01, M11, M21, M31, M41,
The logical values of M51 are "0", "0", "0", and "1", respectively.
First clock signal FCLK after becoming "1" or "0"
At the rising edge of, the logical value of the signal MSK becomes "0",
The time width of the window is 53 of the clock signal FCLK.
This corresponds to the length of the cycle.

(ERLVL0, ERLVL1) = (1,
In the case of 1), signals M01, M11, M21, M31, M
The logical values of 41 and M51 are "1", "1", and "0", respectively.
The first clock signal F after becoming "1""1""0"
At the rising edge of CLK, the logic value of the signal MSK becomes “1”, and the signals M01, M11, M21, M31, M41,
The logical values of M51 are "0", "0", "0", and "0", respectively.
First clock signal FCLK after becoming "0" and "1"
At the rising edge of, the logical value of the signal MSK becomes "0",
The time width of the window is 69 of the clock signal FCLK.
This corresponds to the length of the cycle.

At the time of data reading, that is, the signal PULL
When the logic value of IN1 is “0”, a signal based on the signal NLD0 from the 2N frequency divider 74 of FIG. 10 is output as the signal MLOAD0. However, the frequency check circuit 75 outputs the logic of this signal MLOAD0. When the portion having the value "0" is output during the time width of the window of the signal MSK, it is detected as a frequency abnormality.

The range for judging the frequency abnormality is the M frequency divider 70.
If the frequency division ratio of M is expressed in decimal, according to the circuit configurations shown in FIGS. 11 to 14, (ERLVL0, ERLVL
1) = (0,0), when a frequency error of (21 / M) × 100% occurs, the signal PLLER has a logical value “1”.
Becomes

FIG. 16 shows a case where the signal TST04 for switching the time width of the window of the signal MSK designating the range judged to be abnormal in frequency has a logical value "1", that is, a window having a large time width. . That is, in the selector circuits SEL1 to SEL3 of FIG. 12, the signals M01, M11, M2 selected by the signal TST04 are selected.
Signals MD01, MD11, MD for generating the signal MSK based on 1, M31, M41, M51, M61, etc.
21, MD31, MD02, MD12, MD22, MD
32 is generated, and further, the selector circuit SEL of FIG.
5, the signals ERLVLO and ERLVL1 cause
One of the four window widths is determined and the signal MSK is output.

(ERLVL0, ERLVL1) = (0,
0), signals M01, M11, M21, M31, M
The logical values of 41, M51, and M61 are each "1".
After becoming "1", "1", "0", "0", "1", "1", at the first rising edge of the clock signal FCLK, the signal MSK
Has a logical value of "1" and signals M01, M11, M2
The logical values of 1, M31, M41, M51, and M61 become "0", "0", "1", "0", "1", "0", and "0", respectively, and then at the first rise of the clock signal FCLK,
The logical value of the signal MSK is “0”, and the time width of the window corresponds to the length of 22 × 4 cycles of the clock signal FCLK.

(ERLVL0, ERLVL1) = (0,
In the case of 1), signals M01, M11, M21, M31, M
The logical values of 41, M51, and M61 are each "1".
After becoming "1", "1", "0", "1", "0", "1", at the first rising edge of the clock signal FCLK, the signal MSK
Has a logical value of "1" and signals M01, M11, M2
After the logical values of 1, M31, M41, M51, and M61 become “0”, “0”, “1”, “0”, “0”, “1”, and “0”, respectively, at the first rising edge of the clock signal FCLK,
The logical value of the signal MSK is “0”, and the time width of the window corresponds to the length of 38 × 4 cycles of the clock signal FCLK.

(ERLVL0, ERLVL1) = (1,
0), signals M01, M11, M21, M31, M
The logical values of 41, M51, and M61 are each "1".
After becoming "1", "1", "0", "0", "0", "1", at the first rise of the clock signal FCLK, the signal MSK
Has a logical value of "1" and signals M01, M11, M2
After the logical values of 1, M31, M41, M51, and M61 become “0”, “0”, “1”, “0”, “1”, “1”, and “0”, respectively, at the first rising of the clock signal FCLK,
The logical value of the signal MSK is “0”, and the time width of the window corresponds to the length of 54 × 4 cycles of the clock signal FCLK.

(ERLVL0, ERLVL1) = (1,
In the case of 1), signals M01, M11, M21, M31, M
The logical values of 41, M51, and M61 are each "1".
At the first rise of the clock signal FCLK after becoming "1""1""0""1""1""0", the signal MSK
Has a logical value of "1" and signals M01, M11, M2
After the logical values of 1, M31, M41, M51, and M61 become "0", "0", "1", "0", "0", "0", and "1", respectively, at the first rising edge of the clock signal FCLK,
The logical value of the signal MSK is “0”, and the time width of the window corresponds to the length of 70 × 4 cycles of the clock signal FCLK.

The following is similar to the description of FIG.

Next, referring to the time chart shown in FIG. 17, in the data format of the optical disc 1 as shown in FIG. 2, after writing various data in the data area, at the time of read-after-write, P when reading the preformatted area and writing the written flag WF
The operation of the LL circuit 31 will be described.

In FIG. 17, following the pattern of the post preamble IDPA, which is the last byte of the preformat area, at the moment when the area of the written flag WF is reached,
The signal PULLIN1 changes from the logical value "0" to "1".
While the signal PULLIN1 is at the logical value "0", the VCO control voltage V for the VCO 35 is supplied by the lock-in charge signal CHGR and the lock-in discharge signal DISR.
It is designed to output COIN.

While the signal PULLIN1 is at the logical value "1", as described above, the signal NLD1 and the signal MLOAD1 are set.
Pull-in charge signal CH generated according to the phase difference of
V by GP and pull-in discharge signal DISP
The VCO control voltage VCOIN for the CO 35 is output.

Next, a specific example of the circuit configuration of the filter 32 will be described with reference to FIG. In FIG. 18, the lock-in charge signal CHGR is input to the cathode of the diode D1, the anode of the diode D1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the variable resistor VR1.

Lock-in discharge signal DISR
Is input to the anode of the diode D2, and the cathode of the diode D2 is connected to one end of the resistor R2.
The other end of is connected to the other end of the variable resistor VR1.

The pull-in charge signal CHGP is input to the cathode of the diode D3, and the anode of the diode D3 is connected to one end of the resistor R3.

The pull-in discharge signal DISP is
Input to the anode of the diode D4,
The cathode of is connected to one end of the resistor R4.

The other end of the resistor R3 is connected to the other end of the resistor R4, and its connection point O1 is connected to the sliding terminal of the variable resistor VR1.

The operational amplifier G50 is used as an inverting amplifier circuit, and its input terminal is an imaginary short circuit, which is 2.5 V which is half the power supply voltage of this circuit. A connection point O1 is connected to the input terminal of this operational amplifier, and one end of a charge holding capacitor C50 is further connected.

The other end of the capacitor C50 has a changeover switch S.
1 movable contact. This changeover switch S1 8
One end of each of eight resistors R5 to R12 having different resistance values is connected to each of the fixed contacts, and one of the resistors R5 to R12 is selected by the movable contact so as to be connected to the capacitor C50. It has become.

The resistance R5 of the changeover switch S1
The selection of R12 is determined by the input / output characteristics of the VCO 35 as shown in FIG. That is, the pull-in type phase comparator 34 is selected and VC is set at a certain set frequency.
Make O35 oscillate. VCO35 at this time
Of the VCO control voltage VCOIN of
Estimate the sensitivity of O35. That is, when a certain set frequency is f and the VCO control voltage at this time is v, the slope S =
Estimate Δf / Δv and determine which resistor should be selected. For example, when the resistor R5 is selected and its resistance value is represented by R5 and the capacitance of the capacitor C50 is represented by C50, the cutoff frequency ω1 at this time is ω1 = 1 / (R5 · C5
0), which is called a filter constant here. The changeover switch S1 is controlled so as to select a resistor having a small resistance value when the estimated sensitivity is high, and to select a resistor having a large resistance value when the estimated sensitivity is small, thereby switching the filter constant. It is like this.

The other end of each of the resistors R5 to R12 is connected to the output terminal of the operational amplifier G50, and its connection point O2.
Is connected to one end of each of the resistors R13 and R14. The other end of the resistor R13 is connected to one end of the resistor R15, and the resistor R1
The other end of 4 is connected to one end of the resistor R16. Resistance R
A connection point O3 between the resistor 14 and the resistor R16 is connected to one end of the switch S2, and a connection point O4 between the resistor R13 and the resistor R15.
Is connected to the other end of the switch S2.

The signal PULLIN0 is input to the switch S2, and the connection point O3 and the connection point O4 are connected or released by the opening / closing control by this signal. That is, when the logical value of the signal PULLIN0 is "0", the connection points O3 and O4 are released, and when the logical value of the signal PULLIN0 is "1", the connection points O3 and O4 are connected.

One end of the capacitor C51 is connected to the connection point O4, and the other end and the other ends of the resistors R15 and 16 are both grounded.

Further, one end of the resistor R17 is connected to the connection point O4, and one end of R18 is connected to the other end. The other end of the resistor R18 is used as an observation terminal. From the other end of the resistor R17, VCO control voltage VCOIN
Is output.

The other end of the resistor R18 as an observation terminal is used for estimating the sensitivity of the VCO 35 for switching the filter constant described above. In the method, for example, an A / D converter (not shown) is connected to the observation terminal, where the VCO control voltage VCOIN is converted as an analog to digital voltage value, and the value is converted by the CPU 50. To the CPU 50, and the output frequency of the VCO 35 at this time is also notified to the CPU 50.
The PU 50 calculates sensitivity and the like based on various information stored in advance in the memory 51, and as a result, sends a control signal for selecting an optimum resistance value to the switch S1,
Switching control of the switch S1 can be performed. It is also possible to connect an appropriate measuring device (measurement oscillator or the like) to the observation terminal from the outside of the device and control the switch S1 from the measurement result to select an appropriate resistance.

In such a structure, when the lock-in charge signal CHGR becomes the logical value "0", the connection point O1
A current determined by the respective resistance values of the resistor R1 and the variable resistor VR1 flows in the direction from the variable resistor VR1, the resistor R1, and the diode D1 to charge the capacitor C50.

When the lock-in discharge signal DISR becomes a logical value "1", the diode R2 causes the resistor R
2. A current determined by the resistance values of the resistor R2 and the variable resistor VR1 flows in the direction of the variable resistor VR1 and the connection point O1,
Discharge the capacitor C50.

The signal PULLI input to the switch S2
When the logical value of N0 is "0", the connection points O3 and O4 are released, and the potential of the connection point O2 is divided by the resistors R13 and R15. At this time, the resistors R13, R15 and the capacitor C5
1 constitutes a low-pass filter, and includes resistors R13 and R
When the resistance values of 15 are expressed as R13 and R15, respectively, the parallel resistance value r1 can be expressed as r1 = 1 / {1 / (1 / R13) + (1 / R15)}, and the cutoff frequency ω2 is Capacitor C5
When the capacity of 1 is represented as C51, ω2 = 1 / (r1 · C5
It can be expressed as 1).

The signal PULLI input to the switch S2
When the logical value of N0 is "1", the connection points O3 and O4 are connected, and the potential of the connection point O2 is divided by the parallel resistance of the resistors R13 and R14 and the parallel resistance of R15 and R16. At this time, the resistance value r of the parallel resistance r2 formed by the resistors R13 and R14
2. Resistance value r of the parallel resistance r3 formed by the resistors R13 and R15
3 are r2 = 1 / {1 / (1 / R13) + (1 / R14)} r3 = 1 / {1 / (1 / R15) + (1 / R16)}, respectively, and the parallel resistance r2 , R3 parallel resistance r
The resistance value r3 of 4 is r4 = 1 / {1 / (1 / r2) + (1 / r3)}, and if the capacitance of the capacitor C51 is represented by C51, the cutoff frequency ω2 at this time is ω2 = 1 / (R4 ・ C
It can be expressed as 51).

As described above, when the logical value of the signal PULLIN0 is "0", that is, when data is written, the switch S2 is adjusted so as to reduce the cutoff frequency. A high cutoff frequency means that the damping factor of the loop of the PLL circuit 31 is high, that is, the jitter increases. A small cutoff frequency means that the damping factor is small, so that the loop is pulled in quickly and the stability of the loop is reduced, but the jitter is reduced. That is, when writing data, it is possible to suppress jitter to about 1/10 of that when reading data.

When data is read, that is, the signal P
When the logical value of ULLIN0 is "1", the voltage value of the VCO control voltage VCOIN becomes smaller than the voltage range of the VCO control voltage VCOIN corresponding to the frequency range used by this device. At this time, in the switch S2, the potential of the connection point O2 is slightly raised to perform the coordinate conversion on the horizontal axis in the input / output characteristics of the VCO 35 as shown in FIG.
4 and R16 are connected in parallel to the resistors R13 and R15, respectively.

As described above, according to the above-described embodiment, the reference clock signal FCLK from the crystal oscillator 30 is divided by the M frequency divider 70 based on the frequency division ratio M set by the CPU 50. The frequency-divided clock signal MLOAD1 is output, and in the pull-in type phase comparator 34, the clock signal MLOAD1 and the clock signal output from the VCO are divided by the k-divider 73 into the division ratio k set by the CPU 50.
The clock signal CLK, which is frequency-divided and output based on, is further frequency-divided and output by the 2N frequency divider 74 based on the frequency division ratio N set by the CPU 50.
And the pull-in charge signal CHGP and the pull-in discharge signal D based on the phase difference.
The lock-in type phase comparator 36 outputs the differential binary signal output from the binarizing circuit 39.
The phase is compared with the clock signal CLK, and the lock-in charge signal CHGR and the lock-in discharge signal DISR are output based on the phase difference, and the optical disc 1
At the time of recording information (at the time of data writing), the signal PULLIN1 becomes “1”, the pull-in type phase comparator 34 is selected, the pull-in charge signal CHGP and the pull-in discharge signal DISP are output to the filter 32, and the optical disc When information is reproduced from 1 (when data is read), the signal PULLIN1 becomes "0", the lock-in type phase comparator 36 is selected, and the lock-in charge signal CHGR and the lock-in discharge signal D are selected.
The ISR is output to the filter 32, and in the filter 32, the VCO control voltage VCOI observed from the other end of the resistor R18.
Based on N and the output frequency of the VCO 35 at this time, C
An optimum resistance is selected in advance from the resistances R5 to R12 by the switching control signal of the switch S1 output as a result calculated by the PU50, and the signal input to the filter 32 is smoothed according to the cutoff frequency set by the resistance. And the VCO control voltage VCOIN is output to control the variation in the sensitivity of the VCO 35.
The O control voltage VCOIN is output.

When the lock-in type phase comparator 36 is selected, the frequency of the clock signal CLK and the clock signal MLOAD1 in the frequency check circuit 75.
Of the clock signal output from the VCO 35 is detected, and when the frequency abnormality is detected, the frequency abnormality detection signal ERRSO becomes “1”, and thus the signal PULLIN1 becomes “0”, The frequency abnormality detection signal ERRSO is restored again after a delay time determined based on the reference clock signal FCLK from the time when the lock-in type phase comparator 36 is switched to the pull-in type phase comparator 34 and the frequency abnormality is no longer detected. "0"
Therefore, the signal PULLIN1 becomes "1", and the lock-in type phase comparator 36 is selected again, so that the clock signal CLK that serves as a reference during information reproduction is obtained even when a frequency abnormality occurs during information reproduction. Therefore, the operation of the PLL circuit 31 can be stabilized.

Further, in the M divider 70, when the lock-in type phase comparator 36 is selected, the clock signal NLD1 (the inverted clock signal of the clock signal NLDO) from the 2N divider 74 is divided by the M divider. By inputting to the load input terminals of the counter circuits CN4 to CN6 constituting 70 and dividing timing, it is possible to reduce the phase change of the clock signal CLK output from the VCO 35 when the information is reproduced and then the information is recorded. Therefore, the operation of the PLL circuit can be stabilized.

Further, by constructing the PLL circuit 31 by a one-chip LSI composed of CMOS elements, the circuit can be downsized and power can be saved, and the development period and the development cost can be reduced.

[0244]

As described above, according to the present invention, 1
It is possible to configure with VCO of CMOS constitution,
A PLL circuit capable of adjusting its response characteristic in response to variations in CO sensitivity and stabilizing the operation of the PLL circuit without impairing the function of the conventional PLL circuit. Also, an information processing device using the PLL circuit can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a configuration of an optical disc device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of a data format recorded on the optical disc of FIG.

3 is a diagram schematically showing an internal configuration of the PLL circuit of FIG.

FIG. 4 is a diagram showing a specific example of a circuit configuration of the voltage controlled oscillator (VCO) of FIG.

FIG. 5 is a diagram schematically showing input / output characteristics of a voltage controlled oscillator (VCO).

6 is a diagram showing a specific example of a circuit configuration of the lock-in type phase comparator of FIG.

7 is a time chart for explaining the operation of the lock-in type phase comparator of FIG.

8 is a diagram showing a specific example of the circuit configuration of the pull-in type phase comparator of FIG.

9 is a time chart for explaining the operation of the pull-in type phase comparator of FIG.

10 is a diagram showing a specific example of a circuit configuration of the 2N frequency divider shown in FIG.

11 is a diagram showing a specific example of the circuit configuration of the M divider and the frequency check circuit of FIG.

12 is a diagram showing a specific example of the circuit configuration of the M divider and the frequency check circuit of FIG.

13 is a diagram showing a specific example of a circuit configuration of the M divider and the frequency check circuit of FIG.

14 is a diagram showing a specific example of the circuit configuration of the M divider and the frequency check circuit of FIG.

FIG. 15 is a time chart for explaining the operation of the frequency check circuit.

FIG. 16 is a time chart for explaining the operation of the frequency check circuit.

FIG. 17 is a time chart for explaining the operation of the PLL circuit during read-after-write.

18 is a diagram showing a specific example of a circuit configuration of the filter of FIG.

[Explanation of symbols]

30 ... Crystal oscillator, 31 ... PLL circuit, 32 ... Filter, 34 ... Pull-in type phase comparator, 35 ... Voltage controlled oscillator (VCO), 36 ... Lock-in type phase comparator, 70 ...
M frequency divider, 71 ... NAND circuit, 72 ... Inverter circuit,
73 ... k frequency divider, 74 ... 2N frequency divider, 75 ... frequency check circuit.

Claims (6)

[Claims] 1. A PLL circuit for generating a clock signal of a predetermined frequency used when information is recorded on and reproduced from an information recording medium, wherein a phase of a reference clock signal is compared with that of the clock signal. First output means for outputting a first phase difference signal based on the phase difference; a reproduction clock signal reproduced from the information recording medium;
Second output means for comparing the phase with the clock signal and outputting a second phase difference signal based on the phase difference; and for recording information on the information recording medium, the first output means When the output means is selected to reproduce information from the information recording medium, the output means selects the second output means, and the position output from the one output means selected by the selection means. A PLL circuit, comprising: a clock signal generating means for generating a clock signal of the predetermined frequency based on a phase difference signal. 2. A voltage-controlled oscillator for generating a clock signal of a predetermined frequency used when recording and reproducing information on an information recording medium, a reference clock signal, and a clock signal output from the voltage-controlled oscillator. First output means for comparing the phases of the two and outputting a first phase difference signal based on the phase difference, and a clock signal read from the information recording medium and extracted from the binarized reproduction information, Second output means for comparing a phase with a clock signal output from the voltage controlled oscillator and outputting a second phase difference signal based on the phase difference; the first output means and the second output Selecting means for selecting one of the means, and when recording information on the information recording medium, when selecting the first output means and reproducing information from the information recording medium, The above The first control means for controlling the selecting means to select the output means of the above, and the frequency of the clock signal output from the voltage controlled oscillator when the second output means is selected by the selecting means and the reference. A frequency abnormality detecting means for comparing the frequency of the clock signal with the frequency abnormality of the clock signal output from the voltage controlled oscillator; and when the frequency abnormality detecting means detects the frequency abnormality, On the other hand, controlling to select the first output means, and controlling the selection means to select the second output means after a predetermined time from the time when the frequency abnormality is no longer detected by the frequency abnormality detecting means. The control means of No. 2 and the phase difference signal output from the output means selected by the selecting means are smoothed, and the control voltage of the voltage controlled oscillator is output. A PLL circuit comprising: a filter means. 3. A voltage controlled oscillator for generating a clock signal of a predetermined frequency used when information is recorded on and reproduced from an information recording medium, and a reference clock signal is frequency-divided by a predetermined frequency division ratio. The frequency dividing means for outputting the clock signal, the divided clock signal output from the frequency dividing means, and the clock signal output from the voltage controlled oscillator are compared in phase, and a first position based on the phase difference is compared. First output means for outputting a phase difference signal, a clock signal read from the information recording medium and extracted from binarized reproduction information, and a phase of a clock signal output from the voltage controlled oscillator are compared. A second output means for outputting a second phase difference signal based on the phase difference, a selection means for selecting one of the first output means and the second output means, and Information recording medium A first output means is selected when information is recorded on the first recording medium, and the second output means is selected when the information is reproduced from the information recording medium. When the second output means is selected by the control means and the selection means, the frequency dividing means divides the frequency at timing based on a clock signal output from the voltage controlled oscillator. Second control means for controlling to output a frequency-divided signal, and a filter for smoothing the phase difference signal output from the output means selected by the selecting means and outputting a control voltage of the voltage controlled oscillator. A PLL circuit comprising: 4. An information processing apparatus for recording and reproducing information on an information recording medium based on a clock signal of a predetermined frequency output from one voltage controlled oscillator, comprising a reference clock signal and the voltage. First output means for comparing a phase with a clock signal output from the controlled oscillator and outputting a first phase difference signal based on the phase difference; and a binarized reproduction read from the information recording medium. Second output means for comparing the phases of the clock signal extracted from the information and the clock signal output from the voltage controlled oscillator, and outputting a second phase difference signal based on the phase difference; Selecting means for selecting one of the output means and the second output means, and for recording the information on the information recording medium, selecting the first output means for recording the information. Medium When the information is reproduced from the output means, the control means for controlling the selecting means to select the second output means, and the phase difference signal output from the output means selected by the selecting means are supplied to a predetermined cutoff frequency. Filter means for smoothing the output voltage of the voltage controlled oscillator, and adjusting means for adjusting the input / output response characteristic of the voltage controlled oscillator by changing the cutoff frequency of the filter means. An information processing device comprising: 5. An information processing apparatus for recording and reproducing information on an information recording medium based on a clock signal of a predetermined frequency output from one voltage controlled oscillator, comprising a reference clock signal and the voltage. First output means for comparing a phase with a clock signal output from the controlled oscillator and outputting a first phase difference signal based on the phase difference; and a binarized reproduction read from the information recording medium. Second output means for comparing the phases of the clock signal extracted from the information and the clock signal output from the voltage controlled oscillator, and outputting a second phase difference signal based on the phase difference; Selecting means for selecting one of the output means and the second output means, and for recording the information on the information recording medium, selecting the first output means for recording the information. Medium When the information is reproduced from the first output means, the first control means for controlling the selection means so as to select the second output means, and the voltage controlled oscillator when the second output means is selected by the selection means A frequency abnormality detecting means for comparing the frequency of the clock signal output from the reference clock signal with the frequency of the reference clock signal to detect a frequency abnormality of the clock signal output from the voltage controlled oscillator; When an abnormality is detected, the selecting means is controlled to select the first output means, and the selecting means is operated to select the first output means after a predetermined time from when the frequency abnormality detecting means stops detecting the frequency abnormality. Second control means for controlling to select the second output means, and smoothing the phase difference signal output from the output means selected by the selection means, An information processing device comprising: a filter unit that outputs a control voltage of a pressure-controlled oscillator. 6. An information processing apparatus for recording and reproducing information on an information recording medium based on a clock signal of a predetermined frequency outputted from one voltage controlled oscillator, wherein a reference clock signal is divided into a predetermined portion. Dividing means for dividing by a dividing ratio and outputting a divided clock signal, and comparing the phases of the divided clock signal output from this dividing means and the clock signal output from the voltage controlled oscillator, First output means for outputting a first phase difference signal based on the phase difference, a clock signal extracted from the binarized reproduction information read from the information recording medium, and output from the voltage controlled oscillator. Any one of the second output means for comparing the phase with the clock signal to be output and outputting a second phase difference signal based on the phase difference, the first output means and the second output means. Choose one Selecting means for selecting the first output means when recording information on the information recording medium, and selecting the second output means when reproducing information from the information recording medium When the second output means is selected by the selection means and the first control means for controlling the selection means, the frequency division means is supplied to the frequency division means based on the clock signal output from the voltage controlled oscillator. Second control means for controlling so as to output the frequency-divided signal at the frequency division timing, smoothing the phase difference signal output from the output means selected by the selection means, and An information processing apparatus comprising: a filter unit that outputs a control voltage of a controlled oscillator.