JP3479459B2 - PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly, it can be suitably used for a PLL circuit for generating a clock synchronized with recorded data in an apparatus for recording / reproducing on a disk-shaped recording medium.

[0002]

2. Description of the Related Art In recent years, a system for recording / reproducing digital data using an optical disc as a recording medium has been proposed, and a CD (compact disc), an MD (mini disc), etc. have been put into practical use as a consumer system. . In these CD systems and MD systems, the recording method is CLV (Constant Linear).
Velocity) method is adopted.

In the CLV system, even if the radial position of the track scanned by the light beam is changed, the linear velocity is kept constant and the recording density is kept constant over the entire surface from the inner circumference to the outer circumference of the disk, whereby the disk capacity is increased. This is a recording method that has the advantage of contributing to the increase of However, in order to keep the linear velocity constant, it is necessary to change the rotational speed of the disk depending on the radial position of the disk at the read point.

Therefore, when a movement (seek) between two points having greatly different radial positions occurs, it takes a very long time to control the number of revolutions to a predetermined value due to the large inertia of the disk, and the seek occurs. Each time it occurs, a waiting time for CLV control is required.

As a result, the CLV system has a drawback that it causes a decrease in average transfer rate. In order to avoid such a drawback, data is read before the rotation of the disk reaches a desired rotation speed. To accurately read data from the reproduction signal before the linear velocity reaches a desired value, a clock synchronized with the reproduction signal is necessary. Therefore, the wide capture P with a wide frequency pull-in range is required.
The LL circuit is used.

The above CLV control and wide capture PL
The L circuit will be described by taking the MD system as an example. FIG. 8 shows a general configuration of the CLV control circuit and the wide capture PLL circuit of the MD system. In FIG.
Although not shown in the figure, the disk 1 has an absolute address embedded in advance in order to know the absolute position of the recording / reproducing point.

This is because the address data is bi-phase mark modulated and further FM modulated with a frequency deviation of a few percent,
The guide groove for tracking servo is meandered (wobbling) in response to the FM modulated signal so that the entire surface of the disk is embedded. This embedded signal is obtained by the pickup 3 by amplifying and filtering the push-pull signal for tracking servo.

This signal is hereinafter referred to as a wobbling signal. The wobbling signal is used, of course, for reproducing the absolute address, but as another important application, it is input to the CLV control circuit 4 and used for CLV control. The CLV control circuit 4 binarizes the input wobbling signal and divides it by the frequency divider 18, and further inputs the clock output of a stable oscillator such as the crystal oscillator 17 and also divides this signal by the frequency divider 19. Be lapped. Here, the frequency division ratios of the frequency dividers 18 and 19 are set so that the frequencies of the outputs of the frequency divider 18 and the frequency divider 19 match when the linear velocity of the disk matches a predetermined value. There is.

The outputs of the frequency dividers 18 and 19 are input to the frequency error detector 20 and the phase error detector 21, and the frequency error and the phase error between them are detected. The outputs of the frequency error detector 20 and the phase error detector 21 are input to the switch 22, and one of them is selected and input to the charge pump 23. The charge pump 23 is a so-called integrator, and also has a role of a loop filter having a DC value integration and a high frequency cutoff characteristic. Charge pump 2
The output of 3 is input to the driver circuit 24, and the spindle motor 2 is driven by the output of the driver circuit 24 to perform feedback control so as to keep the disk linear velocity constant.

Here, when the linear velocity of the disk 1 is farther than a predetermined value, the output of the frequency error detector 20 is selected by the switch 22, and when the linear velocity approaches the predetermined value, it is further increased. For precise control, the output of the phase error detector 21 is selected, phase locked and CLV controlled.

On the other hand, the wide capture PLL circuit 5 receives the wobbling signal and the RF signal obtained by reproducing the record data recorded on the magneto-optical medium by the optical pickup 3. The frequency error detector 6 divides the wobbling signal and a VCO (Voltage Conto).
The output of the rolled oscillator 26 is frequency-divided by the 1 / n frequency divider 11 to detect and output the frequency error.

Further, the phase error detector 7 receives the RF signal and 1 /
The phase error of the output of the n frequency divider 11 is detected and output. The outputs of the frequency error detector 6 and the phase error detector 7 are the switch 8
Is input to the charge pump 9. The input S of the switch 8 is connected to the X output of the timing controller 16. The charge pump 9 is a so-called integrator,
It also has the role of a loop filter having a DC cutoff and a high-frequency cutoff characteristic. The output of the charge pump 9 is the VCO 26
Is input to form a feedback loop.

Immediately after a seek occurs in this PLL circuit, the timing control unit 16 sets the output X to Low for a predetermined time, triggered by an instruction from the host device, and then sets it to High. Here, the higher-level device corresponds to a system microcomputer or the like that controls the entire MD system.

As a result, the switch 8 selectively outputs the output of the frequency error detector 6 for a predetermined period, and captures the frequency when the output of the VCO 26 is 1 / n by the 1 / n frequency divider 11 for phase pull-in. After pulling to the range, the switching unit 8 selects and outputs the output of the phase error detector 7 to lock the phase. In this case, the response of the VCO 26 is much faster than that of the spindle motor, so that a clock synchronized with the RF signal can be obtained before the linear velocity is controlled to a predetermined value.
The recorded data can be reproduced.

[0015]

However, in the conventional wide capture PLL circuit as described above, in order to quickly obtain the synchronization clock even when the seek with the large radius difference occurs, the VCO having an extremely wide oscillation range is used. Is required. For example, if the radius before seek is 15 mm and the radius after seek is 30 mm, the linear velocity immediately after seek is twice as fast as when CLV is stable, and the frequency of the synchronization clock is C
It is twice as much as when the LV is stable. Also, the radius before seek is 30
When the seek radius is 15 mm and the seek radius is 15 mm, the linear velocity immediately after the seek is 1/2 that at the time of CLV stabilization, and the frequency of the synchronous clock is also 1/2.

In order to cover all such cases, the oscillation range of the VCO must be capable of oscillating from 1/2 to 2 times the synchronous clock frequency when CLV is stable. There is a problem that it is difficult to obtain a VCO that oscillates in a wide range of frequencies, has linear characteristics with respect to an input voltage, and has a relatively simple configuration and that suppresses an increase in cost. . The present invention has been made in view of the above problems, and an object thereof is to provide a PLL circuit that solves at least one of these problems.

[0017]

In order to solve the above problems, the PLL circuit of the present invention has the following configuration.

That is, in the invention of claim 1, the frequency changes
Then, an input signal that converges to a predetermined frequency is compared with a clock to create an error signal, and the error signal controls the oscillation frequency of the oscillator that generates the source signal of the clock. In a PLL circuit that generates a clock synchronized with a signal, the frequency of the input signal changes
If the frequency is higher than the specified frequency,
Convergence pattern discriminator that discriminates whether to converge from a closed state
Stage, a plurality of frequency dividers for dividing the signal from the oscillator to generate clocks of different frequencies, and one of the plurality of signals output from the plurality of frequency dividers.
Selection based on the judgment result of the convergence pattern judgment means
The PLL circuit is characterized in that it comprises a switch for outputting as a clock , and the invention of claim 2 is such that it is read from a disk-shaped recording medium rotating so as to keep the linear velocity constant. PL for generating an error signal by comparing the generated signal with the reproduced clock and controlling the oscillation frequency of the oscillator for generating the reproduced clock by the error signal to generate the reproduced clock in synchronization with the input signal.
In the L circuit, a plurality of frequency dividers that divide the signal from the oscillator to generate signals of different frequencies,
A switch for selecting one of a plurality of signals output from the plurality of frequency dividers and outputting it as a reproduction clock; and a predetermined linear velocity after the rotational linear velocity of the disk-shaped recording medium changes. A linear velocity convergence pattern discriminating means for detecting whether the state converges from a state faster than a predetermined linear velocity or from a state slower than a predetermined linear velocity, and the switch is discriminated by the linear velocity convergence pattern discriminating means. According to a third aspect of the present invention, there is provided a PLL circuit in which switching is performed according to a result. Further, the invention of claim 3 compares a signal read from a rotating disk-shaped recording medium with a reproduced clock so as to keep a linear velocity constant. In the PLL circuit that generates an error signal and controls the oscillation frequency of the oscillator that generates the reproduction clock according to the error signal to generate the reproduction clock in synchronization with the input signal. A plurality of oscillators that oscillate at different frequencies, a switch that selects one of a plurality of signals output from the plurality of oscillators and outputs the selected signal as a reproduction clock, and a rotation line of the disk-shaped recording medium When the linear velocity converges to a predetermined linear velocity after a change in velocity, the linear velocity convergence pattern determining means for detecting whether the linear velocity converges from a state faster than the predetermined linear velocity or from a state slower than the predetermined linear velocity. A PLL circuit is characterized in that the device is switched according to the determination result of the linear velocity convergence pattern determination means, and the invention of claim 4 reads from a disk-shaped recording medium rotating so as to keep the linear velocity constant. Error signal by comparing the recovered signal with the recovered clock,
In a PLL circuit that generates a reproduction clock synchronized with an input signal by controlling the oscillation frequency of an oscillator that generates the reproduction clock with the error signal, the oscillation frequency is controlled with the error signal, and the oscillation frequency variable range switching signal is used. The oscillator in which the oscillation frequency range is controlled, and when the rotational linear velocity of the disk-shaped recording medium changes to converge to a predetermined linear velocity, converge from a state faster than the predetermined linear velocity or from a slow state And a linear velocity convergence pattern discriminating means for detecting whether or not the oscillation frequency variable range switching signal of the oscillator is used as a discrimination result signal of the linear velocity converging pattern discriminating means.
According to a fifth aspect of the present invention, the linear velocity convergence pattern determining means determines the linear velocity of the disk-shaped recording medium is higher or lower than a predetermined speed, and And a timing control unit for instructing the linear velocity determination unit to determine the linear velocity during a transient period until the rotational linear velocity of the disk-shaped recording medium converges to a predetermined linear velocity. Claims 2 to 4
The PLL circuit according to any one of 1 to 3 above.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION First, in order to explain the concept of the present invention, let us consider the linear velocity at the time of seek in a disk having an innermost radius of 15 mm and an outermost radius of 30 mm as an example. Here, it is assumed that the specification of the wide capture PLL is to obtain a clock phase-locked to the RF signal before the CLV control becomes stable even when a seek from the innermost circumference to the outermost circumference and from the outermost circumference to the innermost circumference occurs. . First, consider the case of seeking from the innermost circumference to the outermost circumference as pattern 1. Here, it is assumed that the CLV control is stable and the disk is rotating at a predetermined linear velocity before the seek.
A graph of the change in linear velocity at this time is shown in FIG. In this case, the linear velocity doubles immediately after the seek, and then draws a gentle curve and converges to a predetermined linear velocity.

The frequency with which the PLL circuit must be phase locked (channel clock frequency), ie the VCO
Since the oscillating frequency is also proportional to the linear velocity, it doubles immediately after the seek, and then draws a gentle curve and converges to a predetermined channel clock frequency. Also, pattern 2
Consider the case of seeking from the outermost circumference to the innermost circumference. Here, it is assumed that the CLV control is stable before the seek and the disk is rotating so as to have a predetermined linear velocity.

The change in linear velocity in this case is graphed and shown in FIG. In this case, the linear velocity is halved immediately after the seek, and then a gentle curve is drawn to converge to a predetermined linear velocity. Channel clock frequency, or VCO
Since the oscillating frequency is also proportional to the linear velocity, it halves immediately after the seek, and then draws a gentle curve and converges to a predetermined channel clock frequency.

Even in such a case, in the conventional PLL circuit, in order to quickly obtain the clock phase-locked to the RF signal, the oscillation frequency range fr of the VCO is fr = fch / 2-, where fch is a predetermined channel frequency. 2 fch, the ratio of the lowest frequency to the highest frequency is 4 times,
It was practically difficult.

Here, looking again at pattern 1 and pattern 2, it can be seen that pattern 1 requires a predetermined channel clock frequency or higher, and pattern 2 requires a predetermined channel clock frequency or lower. This applies to these two patterns in any case, even if the CLV control is not stable before seek, pattern 1 from the frequency above the predetermined channel clock frequency to convergence and the pattern 1 below the channel clock frequency. The pattern 2 can be divided into the pattern 2 from the frequency of 1 to the convergence, and these two patterns can be determined immediately after the seek or at the initial stage of the PLL pull-in process.

Therefore, for example, if it is judged that the pattern 1 is used, the output of the VCO is set to 1/1 and the pattern 2 is used.
If it is determined that this is the case, the output of the VCO may be divided in half and used.

That is, the oscillation range of the VCO does not have to cover the entire range, and when the frequency division is 1/1, fr = (fch-α) to 2 (fch + α) 1/2 when the frequency division is fr = (fch- By setting α) / 2 to (fch + α), a sufficiently practical VCO can be used.

Moreover, once the convergence pattern is discriminated and the phase is locked, V is also maintained during the transition period of CLV control.
CO switching does not occur, and continuous reading is possible.

Here, α takes into consideration the fluctuation of the linear velocity when the CLV control is stable, the overshoot at the time of pulling in the PLL, and the like.

Based on the above concept, embodiments of the present invention will be described in detail below with reference to the drawings. First, FIG. 1 shows a first embodiment of the present invention, which is a CLV control circuit and a wide capture P when the present invention is applied to an MD system.
The structure of an LL circuit is shown. In the figure, the same parts as those in the conventional technique are designated by the same reference numerals.

Although not shown, the disk 1 has an absolute address embedded in advance in order to know the absolute position of the recording / reproducing point. A wobbling signal obtained from this address signal is input to the CLV control circuit 4,
Used for CLV control. Since the method of CLV control is the same as the conventional technique, the explanation is omitted here.

Next, the wide capture PLL circuit which is a feature of the present invention will be described. Wide capture PL
A wobbling signal, an RF signal, and a clock signal having a stable frequency output from the crystal oscillator 17 are input to the L circuit 5 as inputs.

Hereinafter, this wide capture PLL circuit 5 will be described.
The configuration of will be described. The wobbling signal and the clock signal are input to the linear velocity discriminator 14. When the EN input is at a high level, the linear velocity discriminator 14 determines whether the linear velocity is higher or lower than a predetermined linear velocity during stable CLV control. The level is output, and when the EN input is at the Low level, the previously determined result is held. The specific configuration of the linear velocity discriminator 14 will be described later.

The output of this linear velocity discriminator 14 is the switch 13
Is connected to the S input of. The switch 13 has a high S input.
When it is, the A input is output from the Y output, and when the S input is Low, the B input signal is output.

On the other hand, the output of the VCO 10 is the 1 / n frequency divider 1
It is input to the 1 and 1 / m frequency divider 12. Where m>
n. The output of the 1 / n frequency divider 11 is input to the A input of the switch 13, and the output of the 1 / m frequency divider 12 is input to the B input of the switch 13.

Therefore, the output of the linear velocity discriminator 14 becomes H.
In case of the high level, the output of the 1 / n frequency divider 11 is selected, and in case of the output of the linear velocity discriminator 14 is the low level, 1
/ M frequency divider 12 output is selected by the switch 13,
It is input to the frequency error detector 6 and the phase error detector 7.

The frequency error detector 6 and the phase error detector 7 operate in the same manner as in the prior art. That is, the frequency error detector 6
Detects the difference in frequency between the output of the switch 13 and the wobbling signal, and the phase error detector 7 detects and outputs the phase difference between the output of the switch 13 and the RF signal.

The timing controller 15 controls the switching timing of the switch 8 and the enable signal of the linear velocity discriminator 14 according to an instruction from the host device.
The output of the switch 8 is input to the charge pump 9, and the output of the charge pump 9 is input to the VCO 10 to form a feedback loop.

Next, the operation of the wide capture PLL circuit having the above configuration will be described with reference to FIGS. First, as shown in FIG. 3B, when a seek occurs, a Low signal is input from the higher-level device to the timing control unit 15 when the seek operation is completed and the focus servo and tracking servo are normally pulled High. In response to this, the timing control unit 15 sets the output A to High for a predetermined period as shown in FIG.

Therefore, the EN input of the linear velocity determining unit 14 becomes High for a predetermined period, and the linear velocity determining unit 14 determines whether the linear velocity during this period is higher or lower than the predetermined linear velocity. It is determined whether the pattern that converges to a predetermined value is the above pattern 1 or pattern 2. That is, the timing control unit 15 and the linear velocity discriminator 14 implement a linear velocity convergence pattern discriminating means.

If the pattern 1 is determined, the linear velocity determiner 14 outputs High as shown in FIG. 3 (d). The switch 13 receiving the High output of the linear velocity determiner 14 selects and outputs the output of the 1 / n frequency divider 11.

Next, the frequency error detector 6 compares the frequency of the output of the switching unit 13 with the wobbling signal and outputs the frequency error. At the same time, the phase error detector 7
Thereby, the output of the switch 13 and the phase of the RF signal are compared, and the phase error is output. As shown in FIG. 3 (e),
Since the output X of the timing control unit 15 outputs Low for a predetermined period (frequency pull-in period) in the initial phase of PLL pull-in, the switch 8 selects and outputs the output of the frequency error detector 6.

Therefore, the frequency of the signal obtained by dividing the output of the VCO 10 by 1 / n converges to a value substantially close to the channel clock frequency of the RF signal. When this frequency pull-in period ends, the output X of the timing control unit 15 becomes High.
Is output, the switch 8 selects and outputs the output of the phase error detector 7.

At this time, since the frequency of the signal obtained by dividing the output of the VCO 10 by 1 / n is within the capture range of the phase lock in the vicinity of the channel clock frequency of the RF signal, the output of the phase error detector 7 is The feedback loop operates so as to output a value indicating "no lead / lag" of the phase, and the RF signal and the output of the switch 13 (one obtained by dividing the output of the VCO by 1 / n) are locked.

At this time, the CLV control is naturally in the transient period, and the linear velocity is higher than the predetermined linear velocity as shown in FIG.
It gradually approaches the prescribed linear velocity. Therefore VCO
When the output of 10 is divided by 1 / n, the oscillation frequency range covers the necessary frequency when the pattern 1 converges, so once the phase is locked, the phase lock is maintained even during the transient period of CLV. Data can be reproduced.

When it is determined that the linear velocity is smaller than the predetermined linear velocity in the linear velocity determination period and the linear velocity convergence pattern is the pattern 2, the output of the VCO 10 is used by 1 / m. The process up to phase lock of the PLL in this case is the same as in the case described above, and will be omitted. When the phase is locked, the CLV control is in the transient period, the linear velocity is slower than the predetermined linear velocity, and gradually approaches the predetermined linear velocity.

Therefore, the oscillation frequency range when the output of the VCO 10 is divided by 1 / m and used is the pattern 2
Since it covers the required frequency when converging with
Once the phase is locked, data can be reproduced while maintaining the phase locked even during the CLV transient period.

In the above configuration, for example, when the specification of the pull-in frequency range of the wide capture PLL is from twice the predetermined linear velocity to 1/2, the ratio of the maximum frequency to the minimum frequency is 4 in the conventional system. However, if the present invention is applied, n = 1 and m = 2 in the above-described configuration.
Then, the oscillation frequency range of the VCO can be double the ratio of the highest frequency to the lowest frequency of the conventional configuration, and it is a practical VCO with C
A wide capture PLL in a disk system using LV control can be realized.

Next, the specific structure of the linear velocity discriminator 14 will be described with reference to FIG. First, the wobbling signal is input from the input (A), and the binarizer 41 outputs
Valued. Next, the rising edge detector 42 detects the rising edge of the binarized wobbling signal and outputs a pulse for one clock.

The output of the rising edge detector 42 is connected to the CLR input of the counter 43 and the latch enable input (EN) of the latch 44. As a result, from the rising edge of the binarized signal of the wobbling signal to the next rising edge, that is, one cycle of the wobbling signal is counted by the clock, and the cycle is measured in clock units and held in the latch 44.

By determining by the comparator 45 whether this is larger or smaller than a predetermined value, it is judged whether the current linear velocity is larger or smaller than the predetermined value. Input (E) to the latch enable input (EN) of the next-stage latch 46.
Since the enable signal input from N) is connected, the determination result is updated only when the enable signal is valid.

Next, FIG. 5 shows a second embodiment of the present invention. In this case, it is almost the same as the first embodiment described above, but instead of switching the frequency division ratio of one VCO, the outputs of VCOa 27 and VCOb 28 are set to the linear velocity determination unit 14 as shown in FIG. The configuration is such that it is switched according to the output of. Thus, for example, the selection range of the center frequency is wide, but the ratio of the lowest frequency to the highest frequency is 2
A wide capture PLL circuit can be realized even when a VCO that can take less than twice the VCO must be used.

For example, when the ratio of the lowest frequency to the highest frequency is 1.5 times as the specifications of the VCO, the VCOa whose oscillation range (fr) is fr = (fch-α) to 1.5fch is selected. If the VCOb is selected so that the oscillation range (fr) is fr = (fch / 1.5) to (fch + α), the pull-in range of the PLL is practically (fch / 1.5) to 1.5fch. , The ratio between the lowest and highest VCO frequencies is 2.2
This is equivalent to the case of 5 times.

Furthermore, a third embodiment of the present invention is shown in FIG. In this case also, although it is almost the same as that of the first embodiment described above, the VCO capable of changing the oscillation frequency range stepwise instead of switching the division ratio of the VCO.
29 is used to switch the oscillation frequency range to determine the linear velocity determination unit 14
The feature is that it is performed by the output of.

Generally, it is difficult for the VCO to widen the continuous frequency variable range by the control voltage, but the oscillation frequency range can be switched over a wide range by switching the internal constants. Therefore, by using this method, the PLL pull-in frequency range can be widened in a practical VCO.

For example, the VCO 29 has a ratio of the lowest frequency to the highest frequency of 1.5, but the switching input (S) is High.
In the case of h, the oscillation range (fr) becomes fr = (fch−α) to (1.5 · fch), and when the switching input (S) is Low, the oscillation range (f
When r) is set to be fr = (fch / 1.5) to (fch + α), the application of the present invention substantially prevents P from occurring.
The pulling range of LL is (fch / 1.5) to (1.5 · fch), and the ratio of the minimum frequency to the maximum frequency of VCO is 2.2.
This is equivalent to the case of 5 times.

Here, FIG. 7 shows a general structure of a VCO capable of switching the frequency stepwise. In FIG. 7, the control voltage is input to a differential integrator 71 including an operational amplifier 75, a resistor, and a capacitor.
Are charged and discharged in a time proportional to the control voltage. The output of the differential integrator 71 is input to the hysteresis comparator 72. When the input exceeds the threshold value, the output of the hysteresis comparator 72 is inverted and the transistor 73 is turned on / off.
F The differential integrator 71 is charged when the transistor 73 is OFF and discharged when the transistor 73 is ON, so that the output of the differential integrator 71 oscillates a triangular wave. Therefore, the output of the hysteresis comparator 72 is output as a square wave clock.

On the other hand, the charging / discharging time, that is, the oscillation frequency is determined by the constants of the capacitor and the resistor. Therefore, the oscillation frequency can be switched by switching the capacitor 76 and the capacitor 77 with the switch 74.

In the above description, the MD system is taken as an example, but the present invention is not limited to this. For example, when applying the synchronization clock extraction at the time of recording / reproducing to a system using a so-called external clock system, which is performed by using clock marks embedded in the disk for the purpose of clock extraction, instead of recording data itself, A clock mark signal may be used instead of the wobbling signal.

The case of CLV control has been described as an example, but Z in which the linear velocity is changed stepwise depending on the radial position is described.
CLV (Zone Constant Linear)
It can also be applied to a system using the Velocity) method. The ZCLV method is a CAV method in the same zone because it is a stepwise CLV for each zone, and the linear velocity changes, but the radius difference in the normal zone is small, so the value of α described above is set to the zone. There is no problem if it is possible to absorb the difference in the linear velocity inside.

In the above embodiment, the frequency range to be covered by the VCO is divided into two ranges.
It is naturally conceivable that the application is not limited to one and is divided into three or more ranges.

As described above, since the present invention has a relatively simple structure, it is possible to realize a PLL circuit having a wide frequency variable range while suppressing an increase in cost.

[0061]

According to the inventions of claim 1, claim 2 and claim 5, the ratio of the minimum frequency to the maximum frequency capable of phase locking can be expanded to more than the capacity of the VCO. It is possible to realize a wide capture PLL circuit having a wide pull-in frequency range with a simple VCO.

According to the third and fifth aspects of the invention, since the pull-in frequency range is covered by a plurality of VCOs, the frequency variable range of each VCO can be narrowed, so that an inexpensive VCO can be used. Furthermore, since the VCO frequency variable range can be used with a margin, it is easy to obtain linear characteristics with respect to the input voltage.

According to the inventions of claims 4 and 5, a wide frequency variable range can be realized while simplifying the circuit structure by using the VCO capable of changing the oscillation frequency range stepwise. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the concept of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the present invention.

FIG. 4 is a block diagram showing a configuration of a linear velocity convergence pattern discriminator of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a VCO whose oscillation frequency range can be switched.

FIG. 8 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

1 disk recording medium, 2 spindle motor, 3 pickup, 4 CLV control circuit, 5 PLL circuit, 6
Frequency error detector, 7 phase error detector, 8 switch,
9 charge pump, 10 VCO, 11 frequency divider, 1
2 frequency divider, 13 switcher, 14 linear velocity convergence pattern discriminator, 15 timing control section, 16 timing control section, 17 crystal oscillator, 18 frequency divider, 19 frequency divider, 20 frequency error detector, 21 phase error Detector, 2
2 changer, 23 charge pump, 24 driver,
25 PLL circuit, 26 VCO, 27 VCO, 28
VCO, 29 VCO, 41 Binarizer, 42 Rising edge detector, 43 Counter, 44 Latch, 4
5 comparators, 46 latches, 71 differential integrators,
72 hysteresis comparator, 73 transistor, 74 switch, 75 operational amplifier, 76 capacitor, 77 capacitor

Claims (5)

(57) [Claims] 1. A frequency changes and then a predetermined frequency is reached.
A PLL circuit that generates an error signal by comparing a converged input signal and a clock, and controls an oscillation frequency of an oscillator that generates a source signal of the clock by the error signal to generate a clock synchronized with the input signal , When the frequency of the input signal changes,
Whether to converge from a large state or from a small state
A converging pattern determining means for determining a plurality of frequency dividers to create a clock having a frequency different from each signal from the oscillator by dividing among the plurality of signals output from the plurality of the frequency divider One of the signals based on the judgment result of the convergence pattern judgment means
A PLL circuit comprising: a switch that selects and outputs as a clock . 2. An error signal is generated by comparing a signal read from a disk-shaped recording medium rotating so as to keep a constant linear velocity with a reproduced clock, and the reproduced clock is generated by the error signal. In a PLL circuit for generating a reproduction clock synchronized with an input signal by controlling the oscillation frequency of an oscillator, a plurality of frequency dividers that divide the signal from the oscillator to create signals of different frequencies, A switch for selecting one of a plurality of signals output from the plurality of frequency dividers and outputting it as a reproduction clock; and a predetermined linear velocity after the rotational linear velocity of the disk-shaped recording medium changes. A linear velocity convergence pattern determining means for detecting whether the convergence is performed from a state faster than a predetermined linear velocity or a state slower than a predetermined linear velocity when converged; PLL circuit and switches the discrimination result of the convergence pattern discriminating means. 3. An error signal is created by comparing a signal read from a disk-shaped recording medium rotating so as to keep a constant linear velocity with a reproduced clock, and the reproduced clock is generated by the error signal. In a PLL circuit that generates a reproduction clock synchronized with an input signal by controlling the oscillation frequency of the oscillator, the plurality of oscillators that oscillate at different frequencies and the plurality of signals output from the plurality of oscillators A switch which selects one signal and outputs it as a reproduction clock, and when the rotational linear velocity of the disk-shaped recording medium changes and then converges to a predetermined linear velocity, whether to converge from a state faster than the predetermined linear velocity. Linear velocity convergence pattern determination means for detecting whether or not convergence is performed from a slow state, and the switching device is used as a determination result of the linear velocity convergence pattern determination means. PLL circuit and switches Ri. 4. An error signal is generated by comparing a signal read from a disk-shaped recording medium rotating so as to keep a constant linear velocity with a reproduced clock, and the reproduced clock is generated by the error signal. In a PLL circuit for generating a reproduction clock synchronized with an input signal by controlling the oscillation frequency of the oscillator, the oscillation frequency is controlled by the error signal, and the oscillation frequency range is controlled by the oscillation frequency range switching signal. When the rotational linear velocity of the disk-shaped recording medium is changed, when the linear velocity is converged to a predetermined linear velocity, a linear velocity convergence pattern discriminating means for detecting whether it converges from a state faster than the predetermined linear velocity or from a slower state than the predetermined linear velocity And that the oscillation frequency range switching signal of the oscillator is used as the discrimination result signal of the linear velocity convergence pattern discrimination means. PLL circuit to be used. 5. The linear velocity convergence pattern determining means determines whether the rotational linear velocity of the disc-shaped recording medium is faster or slower than a predetermined velocity, and the linear linear velocity of the disc-shaped recording medium. 5. The timing control means for instructing the linear velocity determination means to determine the linear velocity during the transition period until the linear velocity converges to a predetermined linear velocity, according to any one of claims 2 to 4. The PLL circuit described in 1.