JPH1064168A - Data recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the access time at the time of recording data, by starting recording when the number of revolutions before attaining the number of revolutions of the zone of a moving destination attains a prescribed per cent of the number of revolutions of the zone of the moving destination. SOLUTION: At the time of executing recording of data, a track number and a sector number are supplied to a CPU 30 from an optical disk controller 36 and are supplied to a memory 2 where these numbers are recorded. The CPU 30 judges the zone by the track number, reads the speed data corresponding to the number of revolutions of the optical disk 1 for the zone out of a table 2a and outputs the data to a motor control circuit 4. Further, the CPU 30 outputs the speed data of ±20% from the target speed data to the latch section of a PLL circuit 16. The circuit 4 changes the number of revolutions of the motor 3 to the number of revolutions adjusted to meet the target speed data supplied thereto. The CPU 30 controls a linear motor control circuit 8 and a tracking control circuit 28 in correspondence to the track number. As a result, the optical head 5 is moved to the corresponding track.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording apparatus such as an optical disk apparatus for recording data on an optical disk composed of a plurality of zones each having a plurality of tracks by rotating at a different number of revolutions for each zone. It relates to a recording device.

[0002]

2. Description of the Related Art In recent years, an optical disc has been divided into a plurality of zones consisting of a plurality of tracks in the radial direction, and the number of sectors per track has been the same for each zone. The numbers are different. When recording data on an optical disk or reproducing recorded data, the optical disk is rotated at a different number of revolutions for each zone to record data or reproduce recorded data by an optical head. It is supposed to do. The optical head moves in the radial direction of the optical disk to record data on a predetermined track or to reproduce recorded data.

[0003] The number of rotations gradually decreases from the inside to the outside of the optical disk. In such an optical disc device, when recording data, the number of rotations of the zone in which the recording is performed has been reached, and the data cannot be recorded unless the rotation is stabilized. That is, mechanically, it took time for the rotation to stabilize.

[0004]

As described above, in the case where data is recorded by rotating at a different rotation speed for each zone, when the data is recorded, the rotation speed of the zone where the recording is performed is reduced. The data can be recorded only after the rotation is stabilized and the drawback that the access time is required can be removed. When moving to a desired zone, the rotation speed of the zone is reached. It is an object of the present invention to provide a data recording apparatus that can perform a recording operation even before the rotation speed is not stable and can shorten an access time when recording data.

[0005]

A data recording apparatus according to the present invention has a groove and a land for recording spiral or concentric data, and includes a header section composed of a fixed length of the groove and the land and composed of address data and a header section. An optical head for recording data on an optical disc having a plurality of recording areas consisting of a data area on which data is recorded, and recording data on an optical disc consisting of a plurality of zones each including a groove and a land; Rotating means for rotating the optical disc at a different number of revolutions for each zone; moving means for moving the optical head to a predetermined zone by moving the optical head in a radial direction of the optical disc;
Storage means for storing speed data corresponding to the number of rotations of each zone of the optical disc; when the optical head is moved by the moving means to perform recording in another zone, the data corresponds to the destination zone; Reading means for reading the speed data from the storage means; processing means for rotating the rotating means with the speed data read by the reading means; first means corresponding to the number of revolutions before reaching the number of revolutions of the destination zone. First generating means for generating a clock signal of the following type, and detecting a header portion by reproducing data reproduced by the optical head in accordance with the first clock signal generated by the first generating means, and generating a header detection signal. Output means for outputting, second generating means for generating a second clock signal corresponding to the interval of the header detection signal output by the output means, and second generating means And a recording means for recording data on the basis of the second clock signal generated by.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an optical disk device. This optical disc apparatus records data on an optical disc 1 using focused light, or reproduces recorded data.

[0007] The optical disc 1 is formed by coating a metal film layer such as tellurium or bismuth in a donut shape on a surface of a circular substrate made of, for example, glass or plastics. This is a phase change type rewritable disc in which data is recorded or recorded data is reproduced using both lands, and address data is recorded at predetermined intervals by recording marks in a mastering step.

[0008] As shown in FIG.
A plurality of zones 1a composed of a plurality of tracks in the radial direction,
It is divided into ... The clock signal for each zone 1a is the same, and the rotation speed (speed) of the optical disc 1 for each zone 1a is different (slower from the inner circumference to the outer circumference). The number of sectors in one track differs for each zone 1a,. The relationship between the speed data as the number of revolutions for each of the zones 1a,... And the number of sectors per track is recorded in the table 2a of the memory 2 as shown in FIG.

[0009] Each zone 1a of the optical disk 1, the ... tracks includes a header portion 1 _1, each address and the like are recorded, ... are previously pre-formatted for each sector.

FIG. 4 shows a format for each sector of each zone 1a,. In FIG. 4, one sector is 2697 bytes (byte).
s) and a 128-byte header area (header part 1
₁ ), a 5-byte mirror mark area, and a 2,564-byte recording area.

The channel bits recorded in the sector have a format in which 8-bit data is modulated into 16-bit channel bits by 8-16 code. The header area is an area where predetermined data is recorded when an optical disc is manufactured. This header area is composed of four address areas PID1, PID2, PID3, and PID4.

Each of the address areas PID1 to PID4 is composed of 46 bytes or 18 bytes, and has a 36-byte or 8-byte synchronization code part VFO (Variable Frequency OID).
scillator), 3-byte address mark AM (Addres
s Mark), 4-byte address part PID (Position Ide)
ntifier), 2-byte error detection code IED (ID Err
or Detection Code) 1 byte postamble PA
(Postambles).

Address areas PID1 and PID3 are 36
It has a byte synchronization code part VFO1 and has an address area P
ID2 and PID4 are an 8-byte synchronization code part VFO2
have.

The synchronization code portions VFO1 and VFO2 are regions for pulling in the PLL. The synchronization code portion VFO1 records a sequence of "010 ..." in channel bits for "36" bytes (646 bits in channel bits). (Recording a pattern at a fixed interval), and the synchronization code portion VFO
Reference numeral 2 denotes a sequence of “010...” Of channel bits recorded for “8” bytes (128 bits of channel bits).

The address mark AM is a "3" byte synchronization code indicating where the sector address starts. As a pattern of each byte of the address mark AM, a special pattern which does not appear in the data portion of "0100100000000100" is used.

The address parts PID1 to PID4 are sector addresses (including ID numbers) as 4-byte address information.
Is an area where is recorded. The ID number is, for example, PI
In the case of D1, it is "1" and is a number representing the number of the overwriting four times in _one header section 11.

The error detection code IED is an error (error) detection code for a sector address (including an ID number).
It is possible to detect the presence or absence of an error in the read PID.

The postamble PA includes a state information necessary for demodulation and has a role of poling as the header portion 1 ₁ is completed by a space. The mirror mark area is
It is used for offset correction of a track difference signal, timing generation of a land / groove switching signal, and the like.

The recording area includes a gap area of 17 to 19 bytes, a VFO3 area of 50 bytes, a data area of 2418 bytes, a guard data area of 30 bytes, and 47 bytes.
It consists of a buffer area of up to 49 bytes.

The gap area is an area where nothing is written. The VFO3 area is also an area for PLL lock,
It is also an area where a synchronization code is inserted in the same pattern to synchronize byte boundaries.

The data area includes a synchronization code, an ECC (Erro
r Collection Code), EDC (Error Detection Cod)
e) An area composed of user data and the like. The guard data area is an area provided in order to prevent terminal deterioration at the time of repeated recording peculiar to the phase change recording medium from reaching the data area.

The buffer region, as the data area does not overlap the next header portion 1 _1, which is an area provided for absorbing and rotation fluctuation of the motor for rotating the optical disc 1.

The reason why the gap area is expressed as 17 to 19 bytes is that a random shift is performed. The random shift is to shift the data write start position in order to reduce the repetitive recording deterioration of the phase change recording medium. The length of the random shift is adjusted by the length of the buffer area located at the end of the data area, and the entire length of one sector is fixed at 2697 bytes.

In FIG. 1, the optical disk 1 is rotated by a motor 3 at a different rotation speed for each zone, for example. The motor 3 is controlled by a motor control circuit 4. Recording and reproduction of data on the optical disk 1 are performed by the optical head 5. The optical head 5 is
The linear motor 6 is fixed to a drive coil 7 constituting a movable portion, and the drive coil 7 is connected to a linear motor control circuit 8.

A speed detector 9 is connected to the linear motor control circuit 8, and the optical head 5 detected by the speed detector 9
Is sent to the linear motor control circuit 8. A permanent magnet (not shown) is provided at a fixed portion of the linear motor 6. When the drive coil 7 is excited by the linear motor control circuit 8, the optical head 5 is moved in the radial direction of the optical disc 1.

The optical head 5 is provided with an objective lens 10 supported by a wire or a leaf spring (not shown). The objective lens 10 can be moved in the focusing direction (the direction of the optical axis of the lens) by driving the drive coil 11, and can be moved in the tracking direction (the direction orthogonal to the optical axis of the lens) by driving the drive coil 12. Is possible.

A laser light beam is emitted from the semiconductor laser oscillator 9 by drive control of the laser control circuit 13.
The laser control circuit 13 includes a modulation circuit 14 and a laser drive circuit 15, and operates in synchronization with a recording clock signal supplied from the PLL circuit 16. The modulation circuit 14 modulates the recording data supplied from the error correction circuit 32 into a signal suitable for recording, that is, 8-16 modulated data. The laser drive circuit 15 drives a semiconductor laser oscillator (or an argon-neon laser oscillator) 19 according to the 8-16 modulation data from the modulation circuit 14.

PLL (Phase Locked Loop) circuit 16
During recording, the basic clock signal generated from the crystal oscillator 17 is divided by a frequency division value set by the CPU 30 or set to a frequency corresponding to the time interval (header interval) at which the header section 11 on the optical disc ₁ is reproduced. The frequency is divided to generate a clock signal for recording, and at the time of reproduction,
A reproduction clock signal corresponding to the reproduced synchronization code is generated. Further, the PLL circuit 16 includes a CPU 30
Control signal from the controller and the binarization circuit 41 of the data reproduction circuit 18
And a clock signal for recording or reproduction is selectively output in accordance with the signal from.

The laser light beam emitted from the semiconductor laser oscillator 19 is irradiated on the optical disk 1 via the collimator lens 20, the half prism 21, and the objective lens 10. The reflected light from the optical disc 1
0, a half prism 21, a condenser lens 22, and a cylindrical lens 23, and are guided to a photodetector 24.

The photodetector 24 includes a four-divided photodetector cell 24.
a, 24b, 24c, and 24d. The output signal of the photodetector cell 24a is supplied to one end of the adder 26a via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26b via an amplifier 25b. The output signal of the light detection cell 24c is
5c is supplied to the other end of the adder 26a. The output signal of the light detection cell 24d is supplied to the other end of the adder 26b via the amplifier 25d.

Further, the output signal of the light detection cell 24a is:
The signal is supplied to one end of the adder 26c via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26d via an amplifier 25b. Photodetection cell 24
The output signal of c is supplied to the other end of the adder 26d via the amplifier 25c. The output signal of the light detection cell 24d is supplied to the other end of the adder 26c via the amplifier 25d.

The output signal of the adder 26a is a differential amplifier OP
2, and the output signal of the adder 26b is supplied to the non-inverting input terminal of the differential amplifier OP. The differential amplifier OP2 outputs a signal related to the focus point according to the difference between the two output signals of the adders 26a and 26b. This output is supplied to the focusing control circuit 27. The output signal of the focusing control circuit 27 is supplied to the focusing drive coil 12. Thus, the laser light beam is controlled to be always just focused on the optical disc 1.

The output signal of the adder 26c is a differential amplifier OP
1, and the output signal of the adder 26d is supplied to the non-inverting input terminal of the differential amplifier OP1. The differential amplifier OP1 outputs a track difference signal according to the difference between the two output signals of the adders 26c and 26d. This output is supplied to the tracking control circuit 28. The tracking control circuit 28 creates a track drive signal according to the track difference signal from the differential amplifier OP1.

The track drive signal output from the tracking control circuit 28 is applied to the drive coil 1 in the tracking direction.
1 is supplied. Further, a track difference signal used in the tracking control circuit 28 is supplied to the linear motor control circuit 8.

By performing the focusing and tracking, each of the light detection cells 24a,
... the sum signal of the output signals of 24d,
The change in the reflectance from the pits (recording data) formed on the track is reflected in the output signal of the adder 26e, which is the addition of the two output signals c and 26d. This signal is supplied to the data reproducing circuit 18. Data reproduction circuit 18
Reproduces recorded data based on a reproduction clock signal from the PLL circuit 16.

The data reproducing circuit 18 includes an adder 26
e, based on the output signal of e and the reproduction clock signal from the PLL circuit 16, to detect the sector mark in the preformat data, and to supply the sector mark 2 supplied from the PLL circuit 16.
Based on the digitized signal and the reproduction clock signal, a track number and a sector number as address information are reproduced from the binarized signal.

The reproduced data of the data reproducing circuit 18 is transferred to the bus 2
9 is supplied to the error correction circuit 32. The error correction circuit 32 outputs an error correction code (EC
C) to correct the error, or add an error correction code (ECC) to the recording data supplied from the interface circuit 35 and output it to the memory 2.

The reproduced data whose error is corrected by the error correction circuit 32 is transmitted to the bus 29 and the interface circuit 3.
5 is supplied to an optical disk control device 36 as an external device. The recording data emitted from the optical disk control device 36 is transmitted to the interface circuit 35 and the bus 29.
Is supplied to the error correction circuit 32 via the.

When the objective lens 10 is moved by the tracking control circuit 28, the linear motor 6, that is, the optical head 5 is moved by the linear motor control circuit 8 so that the objective lens 10 is located near the center position in the optical head 5. Be moved.

The D / A converter 31 includes a focusing control circuit 27, a tracking control circuit 28, a linear motor control circuit 8, and a CPU 30 for controlling the entire optical disk apparatus.
Used to transfer data between and.

The motor control circuit 4, the linear motor control circuit 8, the laser control circuit 15, the PLL circuit 16, the data reproduction circuit 18, the focusing control circuit 27, the tracking control circuit 28, the error correction circuit 32 and the like are connected via a bus 29. It is controlled by the CPU 30. The CPU 30 performs a predetermined operation according to a program recorded in the memory 2.

As shown in FIG. 5, the PLL circuit 16 includes first and second phase comparators 41 and 42 and a selection circuit 4.
3. Smoothing filter unit 44, voltage controlled oscillator 45, first, second and third frequency dividers 46, 47 and 48, counter 4
9, a latch section 50, and an inverter circuit 51. The selection circuit 43, the smoothing filter section 4
4. The voltage controlled oscillator 45 is an analog circuit, and the first and second
Phase comparators 41 and 42, first, second and third frequency dividers 4
6, 47, 48, the counter 49, the latch unit 50, and the inverter circuit 51 are digital circuits. This PL
The L circuit 16 can generate a clock signal for recording and reproduction by one voltage controlled oscillator 45 (VOC). This PLL circuit 16 has a function of adjusting the output frequency of the voltage controlled oscillator 45 to the expected frequency,
Function header portion 1 ₁ of the optical disc 1 is to hold the output frequency of the voltage controlled oscillator 45 in accordance with the time interval to be reproduced (header interval), has the ability to decrypt the clock and data by the binarization signal reproduced .

The first phase comparator 41 is a lock-in type phase comparator, and outputs a binary signal (reproduction signal) from the comparison circuit 61 in the data reproduction circuit 18 and a clock from the voltage controlled oscillator 45. The phase with the signal is compared, and a signal having a pulse width proportional to the compared phase difference is output. The signal from the first phase comparator 41 is output to the selection circuit 43, and data synchronized with the clock signal is output to the data reproduction circuit 43.

The first phase comparator 41 is configured to operate even when the binarized signal from the comparison circuit 61 receives a missing signal whose pulse cycle is not regular. Second
Is a pull-in type phase comparator,
The phase of the signal from the second frequency divider 47 is compared with the phase of the signal from the third frequency divider 48, and a signal having a pulse width proportional to the phase difference and frequency difference is output. The signal from the second phase comparator 42 is output to the selection circuit 43.

The selection circuit 43 selectively supplies the signal from the first phase comparator 41 or the signal from the second phase comparator 42 to the smoothing filter unit 44 in accordance with the read / write signal from the CPU 30. Output. When the read / write signal is "1" (during reproduction), the signal from the first phase comparator 41 is selected and output to the smoothing filter unit 44, and when the read / write signal is "0" (recording). Time), the signal from the second phase comparator 42 is selected and the smoothing filter unit 44 is selected.
Output to When the read / write signal is low level,
The output of the inverter circuit 51 operates the second and third frequency dividers 47 and 48.

The smoothing filter section 44 is composed of a resistor, a capacitor, an inverting amplifier, a diode, etc., and receives a signal from the first phase comparator 41 supplied from the selection circuit 43 or a signal from the second phase comparator 42. Remove signal harmonics. The smoothing filter unit 44 switches the cutoff frequency between data recording and data reproduction according to a control signal from the CPU 30. The smoothing filter unit 44 is of a complete integration type, and when recording a high-frequency corner frequency, the 1 /
By switching to about 10, jitter can be suppressed. The signal from the smoothing filter unit 44 is output to the voltage controlled oscillator 45.

A voltage controlled oscillator (VCO; voltage)
The control oscillator 45 outputs a binary clock signal having a frequency proportional to the voltage value (analog value) of the signal supplied from the smoothing filter unit 44.

The clock signal of the voltage controlled oscillator 45 is output to the first phase comparator 41 and the third frequency divider 48, and is also output to the data reproducing circuit 18 and the laser control circuit 13.

The first frequency divider 46 outputs a frequency-divided signal obtained by dividing the reference clock signal of, for example, 30 [MHz] from the crystal oscillator 17 by a frequency division ratio (1/56). The first frequency divider 46 is triggered by a header detection signal from a header detection signal generation circuit 70 in the data reproduction circuit 18. The frequency-divided signal from the first frequency divider 46 is output to the counter 49.

For example, when the frequency of the reference clock signal from crystal oscillator 17 is 30 [MHz], the period of the 56-frequency-divided signal is 1.87 [μm]. The second frequency divider 47 outputs a frequency-divided signal obtained by dividing the reference clock signal from the crystal oscillator 17 by a frequency division ratio (1 / M; M is a natural number) set by the latch unit 50. The frequency-divided signal from the second frequency divider 47 is output to the second phase comparator 42.

The third frequency divider 48 includes a voltage controlled oscillator 45
Frequency division ratio (1/770 (decimal))
And outputs a frequency-divided signal. This third frequency divider 48
Is output to the second phase comparator 42.

The counter 49 counts the frequency-divided signal from the first frequency divider 46 by using the header detection signal from the header detection signal generation circuit 70 in the data reproduction circuit 18 as a trigger. This is a (10-bit) binary counter. The count value from the counter 49 is output to the latch unit 50.

The latch section 50 has a 10-bit configuration, for example, and has a header detection signal generation circuit 7 in the data reproduction circuit 18.
The counter 49 is triggered by the header detection signal from 0 as a trigger.
And speed data (10 bits; speed data of ± 20% from the target speed data) corresponding to the rotation speed from the CPU 30 is set. In this case, if the current speed is lower than the target speed, -20% speed data is set than the target speed data, and if the current speed is higher than the target speed, + 20% of the target speed data is set. Speed data is set. The current speed is measured by the motor control circuit 4. The latch output (M) of the latch unit 50 is set in the second frequency divider 47 as a frequency division ratio (1 / M). The number of bits of the latch unit 50 and the number of bits of the second frequency divider 47 are the same.

As shown in FIG. 6, the data reproducing circuit 18 includes a binarizing circuit 61, a shift register 62, a demodulating circuit 63, an address mark detecting circuit 64, and a word boundary counter 6.
5, IED check circuit 66, address comparison circuit 67,
And a header detection signal generation circuit 68.

The binarization circuit 61 binarizes the addition signal from the adder 26e. This binarization circuit 6
The binary signal from 1 is supplied to the PLL circuit 16,
It is converted into a data sequence (channel data) synchronized with the reproduction clock signal (channel clock).

A channel clock and channel data as output signals of the PLL circuit 16 are supplied to a shift register 62 having a 16-bit structure. This channel clock is
It is also supplied to a demodulation circuit 63, an address mark detection circuit 64, and a word boundary counter 65.

The shift register 62 converts the supplied channel data into 16-bit parallel data and outputs it. The 16-bit channel data from the shift register 62 is supplied to a demodulation circuit 63 and an address mark detection circuit 64.

The demodulation circuit 63 outputs, as ROM output data, data stored at an address corresponding to 16-bit address data from the shift register 62 when the word boundary signal from the word boundary counter 65 is supplied. A demodulation ROM (not shown) and R from the demodulation ROM
It comprises a parallel-serial converter (not shown) which converts demodulated data as OM output data into serial data according to a data clock generated by dividing the channel clock from the PLL circuit 16 and outputs the data. .

The ROM output data is data obtained by demodulating 16-bit channel bits into 8-bit data based on a predetermined (8, 16) code conversion rule corresponding to the address data. is there.

The demodulated data signal from demodulation circuit 63 is I
It is output to the ED check circuit 66 and the address comparison circuit 67. The data clock generated by the demodulation circuit 63 is output to the IED check circuit 66, the address comparison circuit 67, and the header detection signal generation circuit 68.

The address mark detection circuit 64 is composed of a comparator. Each time a channel clock is supplied from the PLL circuit 16, the 16-bit channel data from the shift register 62 matches the 16-bit address mark. The address mark detection signal is output when they match with each other. The address mark detection signal from the address mark detection circuit 64 is output to a word boundary counter 65, an IED check circuit 66, an address comparison circuit 67, and a header detection signal generation circuit 68.

The word boundary counter 65 counts using an address mark detection signal from the address mark detection circuit 64 as a trigger and outputs a word boundary signal for each fixed-length block code (16 channel bits). The word boundary signal from the word boundary counter 65 is output to the demodulation circuit 63.

After the address mark detection signal from the address mark detection circuit 64 is supplied to the IED check circuit 66, the sector address of the address part PID of 6 bytes supplied from the demodulation circuit 63 and the error detection code IED
Is accepted based on the data clock, and whether or not the sector address is correct is determined based on whether or not the operation result of the accepted sector address with the error detection code IED is “0”.

The check result of the IED check circuit 66 is output to the header detection signal generation circuit 68. After receiving the address mark detection signal from the address mark detection circuit 64, the address comparison circuit 67
A sector address of a 4-byte address part PID supplied from 3 is received based on the data clock, and the ID number in the received sector address is compared with any one of "1" to "4". , And outputs a signal corresponding to the matching ID number. The signal corresponding to the ID number from the address comparison circuit 67 is output to the header detection signal generation circuit 68. For example, if the ID number is "1"
, "00" is output, if the ID number is "2", "01" is output, and if the ID number is "3", "10" is output.
Is output, and when the ID number is "41", "11" is output.

The address comparison circuit 67 outputs the received sector address to the CPU 30 as address data. Header detection signal generation circuit 68
Are the signal corresponding to the ID number supplied from the address comparison circuit 67 when the check result from the IED check circuit 66 is correct, the address mark detection signal from the address mark detection circuit 64, and the data from the demodulation circuit. Depending on the number of bytes counted by the clock,
A header detection signal is generated in response to the end of the mirror mark area, and is, for example, a binary counter that counts the number of bytes after the supply of the address mark detection signal by the data clock from the demodulation circuit. The header detection signal from the header detection signal generation circuit 68 is
Output to the circuit 16 and the CPU 30. For example, when a signal indicating that the check result is correctly “1” as the ID number is supplied, a header detection signal is generated 94 bytes after the address mark detection signal is supplied from the address mark detection circuit 64, and the check result is output. When a signal indicating "2" is correctly supplied as an ID number, a header detection signal is generated 76 bytes after the address mark detection signal is supplied from the address mark detection circuit 64,
When a signal indicating that the check result is correctly “3” as the ID number is supplied, a header detection signal is generated 30 bytes after the address mark detection signal is supplied from the address mark detection circuit 64, and the check result indicates that the ID is correct.
When a signal indicating the number “4” is supplied, a header detection signal is generated 12 bytes after the address mark detection signal from the address mark detection circuit 64 is supplied.

Next, the operation of the above configuration will be described. For example, when data is recorded, the track number and the sector number are transmitted from the optical disk control device 36 to the CPU 30 via the interface circuit 35 and the bus 29.
And the recording data from the optical disk control unit 36 is supplied to the memory 2 via the interface circuit 35 and the bus 29 and stored therein.

The CPU 30 determines a zone based on the track number, reads speed data corresponding to the number of rotations of the optical disk 1 for this zone from the table 2a,
Output to the motor control circuit 4. Further, the CPU 30 outputs + 20% or −20% speed data (10 bits) from the target speed data to the latch unit 5 of the PLL circuit 16.
Output to 0. In this case, if the current speed measured by the motor control circuit 4 is lower than the target speed, the CPU 30 outputs speed data that is -20% lower than the target speed data, and the current speed is lower than the target speed. Is too early,
Outputs + 20% speed data from the target speed data. Thereby, the motor control circuit 4 changes the rotation speed of the motor 3 to the rotation speed according to the supplied target speed data. Further, by setting the speed data of ± 20% from the target speed data latched by the latch unit 50 as the frequency division ratio M in the second frequency divider 47, the crystal oscillator 1
The signal obtained by dividing the reference clock signal from 7 by the dividing ratio M is output from the second frequency divider 47 to the second phase comparator 42.

Further, the CPU 30 outputs a read / write signal indicating recording time to the selection circuit 43 of the PLL circuit 16. As a result, a signal having a pulse width proportional to the phase difference and frequency difference between the signal from the second frequency divider 47 and the signal from the third frequency divider 48 is selected by the second phase comparator 42. 43, a smoothing filter unit 44, and a voltage controlled oscillator 45. As a result, the PLL circuit 16
A clock signal generated by using a pull-in type phase comparator 42 that outputs a signal having a pulse width proportional to the phase difference between the signals from the third frequency dividers 47 and 48 (depending on the speed data from the CPU 30) Is output to the first phase comparator 41, the third frequency divider 48, and the data reproduction circuit 18. On this occasion,
A clock signal corresponding to ± 20% of the speed data from the target speed data from the CPU 30 is output.

The CPU 30 controls the linear motor control circuit 8 and the tracking control circuit 28 according to the track numbers. As a result, the laser beam from the optical head 5 moves to the track corresponding to the track number (access processing).

In this state, the reproduction signal as an output signal from the adder 26e is binarized by the binarization circuit 61, and is outputted to the data reproduction circuit 18 via the first phase comparator 41 of the PLL circuit 16. The data is supplied to the shift register 62. A clock signal from the voltage controlled oscillator 45 of the PLL circuit 16 is also supplied as a channel clock to the shift register 62, the demodulation circuit 63, the address mark detection circuit 64, and the word boundary counter 65 in the data reproduction circuit 18.

The shift register 62 converts the supplied channel data into 16-bit parallel data and supplies it to the demodulation circuit 63 and the address mark detection circuit 64. The address mark detection circuit 64 outputs an address mark detection signal to the word boundary counter 6 when an address mark is detected based on channel data from the shift register 62.
5, IED check circuit 66, address comparison circuit 67,
And a header detection signal generation circuit 68. The word boundary counter 65 counts using the address mark detection signal from the address mark detection circuit 64 as a trigger,
A word boundary signal is output to the demodulation circuit 63 for each fixed-length block code (16 channel bits).

The demodulation circuit 63 converts the 16-bit address data from the shift register 62 into the ROM output data when the word boundary signal is supplied from the word boundary counter 65, and divides the channel clock to create the data. In accordance with the data clock, the demodulated data signal converted to serial
Output to the ED check circuit 66 and the address comparison circuit 67. The data clock generated by the demodulation circuit 63 is transmitted to the IED check circuit 66 and the address comparison circuit 6.
7, and output to the header detection signal generation circuit 68.

After the address mark detection signal from the address mark detection circuit 64 is supplied to the IED check circuit 66, the sector address of the 6-byte address part PID supplied from the demodulation circuit 63 and the error detection code IED
Is determined based on the data clock, and whether or not the sector address is correct is determined based on whether or not the calculation result of the received sector address with the error detection code IED is "0". Output to the generation circuit 68.

After the address mark detection signal from the address mark detection circuit 64 is supplied to the address comparison circuit 67, the address comparison circuit 67 determines the 4-byte sector address of the address part PID supplied from the demodulation circuit 63 based on the data clock. ID in the received sector address
The number corresponding to any one of “1” to “4” is compared, and a signal corresponding to the matching ID number is output to the header detection signal generation circuit 68.

In this state, the address mark cannot be detected by the address mark detection circuit 64 before the rotation speed of the optical disk 1 becomes ± 20% of the speed data from the target speed data. Since the header detection signal is not output from the signal generation circuit 68, the PLL circuit 16 outputs a clock signal corresponding to ± 20% of the target speed data from the CPU 30 described above.

When the number of rotations of the optical disk 1 becomes ± 20% of the speed data from the target speed data, the address mark is detected by the address mark detection circuit 64, so that the demodulation circuit 63 and the word boundary are detected. Counter 6
5, IED check circuit 66, address comparison circuit 67,
And the header detection signal generation circuit 68 is operated, and the header detection signal from the header detection signal generation circuit 68 is supplied to the first frequency divider 46, the counter 49, and the latch unit 50 of the PLL circuit 18.
Output to With this output, the first frequency divider 46 and the counter 49 operate.

Thus, the first frequency divider 46 converts the reference clock signal from the crystal oscillator 17 into the frequency division ratio (1/56).
And outputs the frequency-divided signal to the counter 49. The counter 49 outputs a count value obtained by counting the frequency-divided signal from the first frequency divider 46 to the latch unit 50.

As a result, the count value from the counter 49 is latched in the latch unit 50 by using the header detection signal from the header detection signal generation circuit 70 as a trigger. That is, the interval between the header detection signal and the header detection signal, the count value of words corresponding to the spacing of the header portion 1 ₁ is latched.

[0079] As the latch portion 50 to the latched header portion 1 ₁ of the frequency division ratio M of the count value corresponding to the distance, by being set to the second frequency divider 47, a crystal oscillator 1
The signal obtained by dividing the reference clock signal from 7 by the dividing ratio M is output from the second frequency divider 47 to the second phase comparator 42.

As a result, the second phase comparator 42
The signal having a pulse width proportional to the phase difference and frequency difference between the signal from the frequency divider 47 and the signal from the third frequency divider 48 is transmitted to the selection circuit 43, the smoothing filter unit 44, and the voltage control oscillator 45. Output via As a result, the PLL circuit 16
Is a clock signal (header unit 1) generated using a pull-in type phase comparator 42 that outputs a signal having a pulse width proportional to the phase difference between the signals from the second and third frequency dividers 47 and 48. _{The first} phase comparator 41, the third frequency divider 48, and the data reproducing circuit 1 depend on the count value corresponding to the interval of ₁ ).
8 is output. At this time, a clock signal corresponding to the count value corresponding to the spacing of the header portion 1 ₁ is output.

Thereafter, address marks are detected in the same manner as described above in accordance with the clock signal from the PLL circuit 16. When the rotation speed of the optical disk 1 reaches the target speed, a header detection signal is generated at intervals depending on the speed, so that the count value corresponding to the speed is set in the latch unit 50, and The clock signal corresponding to the speed is output from the PLL circuit 16.

When the number of rotations of the optical disk 1 becomes ± 20% of the speed data from the target speed data, and the address mark is detected by the address mark detection circuit 64, the address data from the address comparison circuit 67 is set to C.
Output to PU30.

Then, the CPU 30 determines whether or not the address data matches the address data for recording the data. If not, the CPU 30 performs the above-described access processing again.

If they match, the CPU 30
The error correction circuit 32 adds an error correction code to the recording data stored in the
3 and output to the modulation circuit 14. Modulation circuit 14
Transmits the synchronization code VFO3 and the recording data to the PLL circuit 16
The signal is modulated by using the clock signal from the CPU and output to the laser drive circuit 15.

When the header detection signal is output from the header detection signal generation circuit 68, the laser drive circuit 15
Controls the driving of the semiconductor laser oscillator 9 based on the recording data supplied from the modulation circuit 14 and the clock signal from the PLL circuit 16.

[0086] Thus, the synchronization code VFO downstream of the recording area of the header portion 1 ₁ of the recording position on the optical disc 1
3 and recording data are recorded. As described above, in the MCLV optical disk device in which the rotation speed of the optical disk differs for each zone, when data is recorded by moving the zone, the rotation speed corresponding to the zone to be recorded is ± 20.
When the number of rotations reaches%, data recording can be performed.

Thus, when moving to a desired zone, the recording operation can be performed before the rotation speed of the zone is reached and the rotation speed is not stable, and the access time for recording data can be improved. Can be shortened.

Further, the rotation speed of the zone to be accessed is ±
An address mark is detected based on a clock signal corresponding to speed data corresponding to a rotation speed of 20%, and a header detection signal is generated based on the detection of the address mark. The data is recorded based on the clock signal generated by. As a result, data recording errors due to rotation speed fluctuations due to eccentricity or the like can be reduced.

[0089]

As described above in detail, according to the present invention, when a user moves to a desired zone, the recording operation is performed before the rotation speed of the zone is reached and the rotation speed is not stable. A data recording device capable of shortening the access time when recording data.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an optical disk device for explaining an embodiment of the present invention.

FIG. 2 is a view for explaining an example of the format of an optical disc.

FIG. 3 is a diagram for explaining a table in which speed data values corresponding to the number of rotations of the optical disk for each zone are stored.

FIG. 4 is a diagram showing a sector format of an optical disc.

FIG. 5 is a block diagram illustrating a configuration of a PLL circuit.

FIG. 6 is a block diagram showing a configuration of a main part of a data reproduction circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Optical disk 1 ₁ ... Header part 2 ... Memory 2a ... Table 13 ... Laser control circuit 14 ... Modulation circuit 15 ... Laser drive circuit 16 ... PLL circuit 17 ... Crystal oscillator 18 ... Data reproduction circuit 30 ... CPU 61 ... Binarization circuit 62 shift register 63 demodulation circuit 64 address mark detection circuit 65 word boundary counter 66 IED check circuit 67 address comparison circuit 68 header detection signal generation circuit

Claims (5)

[Claims] 1. A plurality of recordings having grooves and lands for recording spiral or concentric data, and comprising a header section composed of grooves and lands of a fixed length and composed of address data and a data area in which data is recorded. In a data recording apparatus for recording data on an optical disk having an area and comprising a plurality of zones each having a groove and a land, an optical head for recording data on the optical disk, and a different rotation of the optical disk for each zone Rotating means for rotating by a number, moving means for moving the optical head to a predetermined zone by moving the optical head in a radial direction of the optical disc, and storing speed data corresponding to the number of revolutions for each zone of the optical disc. Storage means, and the optical head is moved by the moving means to perform recording in another zone. Reading means for reading speed data corresponding to the destination zone from the storage means, processing means for rotating the rotating means with the speed data read by the reading means, rotation of the destination zone First generating means for generating a first clock signal corresponding to the number of revolutions before reaching the number, and reproduction by the optical head according to the first clock signal generated by the first generating means. Output means for detecting a header portion based on the reproduced data and outputting a header detection signal; second generation means for generating a second clock signal corresponding to an interval between the header detection signals output by the output means; Recording means for recording data based on a second clock signal generated by the second generating means. 2. The data according to claim 1, wherein the number of revolutions before reaching the number of revolutions of the destination zone is ± 20% of the number of revolutions of the destination zone. Recording device. 3. When the rotation speed of the destination zone is lower than the current rotation speed, the first generating means corresponds to a rotation speed of -20% of the rotation speed of the destination zone. The data recording device according to claim 1, wherein the data recording device generates a first clock signal. 4. The method according to claim 1, wherein when the rotation speed of the destination zone is higher than the current rotation speed, the first generation means corresponds to a rotation speed of + 20% of the rotation speed of the destination zone. 2. The data recording apparatus according to claim 1, wherein one clock signal is generated. 5. The header section includes a synchronization code section, an address mark, an address section, an error detection code, and a postamble, and the recording area includes a gap area, a synchronization code area, a data area, a guard data area, and a buffer. 2. The method according to claim 1, wherein the area is constituted by an area.
A data recording device according to claim 1.