JP4494941B2 - Clock signal generator for data recording - Google Patents

Description

  The present invention is provided in a data recording apparatus for recording data on an optical disc recording medium such as a CD-R / RW, DVD-R / RW, DVD + R / RW, or the like capable of recording data, and for recording data on the optical disc recording medium. The present invention relates to a data recording clock signal generation circuit that generates and outputs a data recording clock signal used to obtain data writing timing.

Conventionally, recording media such as CD-R, CD-RW, DVD-R, and DVD-RAM are known as optical disks having data recording tracks wobbled with a wobble signal having a predetermined frequency component. There have been data recording clock generators that generate recording clock signals that are phase-synchronized with these optical discs (see, for example, Patent Document 1 and Patent Document 2).
An optical disc has a data recording track wobbled with a wobble signal having a predetermined frequency component, and an optical disc recording apparatus for recording data on the optical disc generates a data recording clock signal WCLK synchronized with the wobble signal WBL. A data recording clock signal generation circuit is provided.

FIG. 10 is a block diagram showing a configuration example of a conventional data recording clock signal generation circuit.
In FIG. 10, a data recording clock signal generation circuit 100 is configured by a so-called PLL (Phase Locked Loop) circuit. The phase comparator 101 compares the phases of the wobble signal WBL and the divided clock signal Sfd obtained by dividing the data recording clock signal WCLK by the frequency divider 105 at a predetermined ratio.

  The output from the phase comparator 101 is converted into a voltage signal by the charge pump circuit 102, smoothed by the filter 103, and input to a voltage controlled oscillator (hereinafter referred to as VCO) 104. The data recording clock signal WCLK, which is the output signal of the VCO 104, is subjected to a PLL pull-in operation in which the frequency is controlled by the voltage input to the VCO 104, and a PLL lock state is achieved in which the PLL loop is stable. As a result, the phase of the data recording clock signal WCLK is synchronized with the wobble signal WBL. The charge pump circuit 102 performs current conversion of the output voltage, generates a data recording clock signal WCLK having a frequency corresponding to the converted current, and outputs the current controlled oscillator (ICO) instead of the VCO 104. Also good.

In a conventional optical disk recording apparatus, when a synchronization signal and address information superimposed on a wobble signal are detected and data is recorded on the optical disk, a predetermined modulation process is performed on the data to be recorded in synchronization with the data recording clock signal WCLK. Apply. The intensity of the laser beam emitted to the optical disk is modulated in accordance with the modulated recording data, and as a result, data is recorded on the optical disk in synchronization with the wobble signal of the data recording track.
However, the phase comparator 101 does not perform frequency comparison between the wobble signal WBL and the divided clock signal Sfd, and only a slight PLL lock range is obtained with respect to the frequency difference between the wobble signal WBL and the divided clock signal Sfd. Therefore, as shown in FIG. 11, the frequency comparator 106 is used together.

  In FIG. 11, when the frequency difference between the wobble signal WBL and the data recording clock signal WCLK is large, the signal from the frequency comparator 106 input to the multiplexer 109 via the second charge pump circuit 108 is received. The output is controlled so that the frequency control for the VCO 104 is performed. Further, when the frequency of the data recording clock signal WCLK becomes a frequency within the PLL lock range of the phase comparator 101 under the control of the frequency comparator 106, the multiplexer 109 is passed through the first charge pump circuit 107. Control is performed so that the input signal from the phase comparator 101 is output, and frequency control for the VCO 104 is performed.

On the other hand, as a property of the data rewritable optical disk, if recording is repeated many times in the same place, the recording mark and its periphery may deteriorate due to thermal stress, etc. In order to alleviate this problem, the recording start point is set. There was a device that randomly varies (see, for example, Patent Document 3 and Patent Document 4).
In addition, the wobble signal may be lost due to defects on the optical disk or dust on the surface of the optical disk, and the phenomenon of so-called bit slip, in which the phase of the wobble signal and the recording clock signal is shifted during this loss, There has been a circuit that recovers the phase shift to the correct phase (see, for example, Patent Document 5).
In addition, there is an optical disk in which address information or the like is superimposed on a wobble signal by phase modulation (see, for example, Patent Document 6), and there is a data recording clock signal generator that generates a recording clock signal that is phase-synchronized with the wobble signal. .

On the other hand, a PLL circuit that generates a data recording clock signal provided in an optical disk recording apparatus that records data on an optical disk capable of recording data can achieve both high-precision phase lock during data recording and high-speed pull-in during seek. Is required. For this reason, the following method has been devised.
D / A converter with coarse frequency resolution and D / A converter with fine frequency resolution are processed by frequency control and phase control, and wobble signal can be obtained with sufficient frequency as long as tracking control is applied. There has been an optical disk reproducing apparatus that is used for control and controls the dynamic range of a D / A converter having a coarse frequency resolution and a D / A converter having a fine frequency resolution at a time when there is no problem in data reproduction ( For example, see Patent Document 7.)

Also, in the zone CLV format optical disk, when accessing different zones, the phase of the PLL circuit is compared by the VFO part of the header part by the pull-in phase comparison that compares the frequency of the VFO pattern and the PLL clock by 1: 1, and then the pull-in. There has been an optical disc apparatus that stops phase comparison and switches to lock-in phase comparison (see, for example, Patent Document 8).
Further, the period of the wobble signal, that is, the rotational speed of the disk is detected, and a signal of the pull-in frequency of the PLL block is generated based on the detected rotational speed, and the rotational speed of the disk is defined based on the generated signal. There has been an information recording / reproducing apparatus that generates a PLL clock according to the rotational speed of a disk even when the speed has not been reached (see, for example, Patent Document 9).

Further, the lock / unlock switching control is performed so that the phase error signal formed by the phase comparator and indicating the phase error of the channel clock from the VCO with respect to the reference clock from the reference clock generation circuit is selected at the time of lock-in, Even if the free-running frequency of the VCO is greatly deviated from the target frequency at the time of lock-in, the phase comparator can detect this deviation amount, and the channel clock can drive the VCO according to this amount of deviation. There was a forming apparatus (for example, refer to Patent Document 10).
JP-A-10-293926 JP-A-11-66563 Japanese Patent Publication No. 8-10489 Japanese Patent Laid-Open No. 10-3667 JP 2001-35090 A JP 2001-319428 A Japanese Patent Laid-Open No. 2000-100083 JP 2001-76440 A Japanese Patent Laid-Open No. 2003-7004 Japanese Patent Laid-Open No. 6-24387

  As described above, the phase comparator performs only the phase comparison, and in the case of the phase comparator without the frequency comparison function, the speed difference between the wobble signal WBL and the divided data recording clock signal WCLK, that is, the frequency difference. The lock range was narrow. Therefore, in FIG. 11, a frequency comparator is used in combination for pulling in the PLL, and the frequency control of the signal output from the VCO is performed using the frequency comparator until the frequency reaches a predetermined frequency, and is provided in the frequency comparator. When the frequency detection circuit determines that the frequency within the PLL lock range has been reached, the control is switched to the frequency control to the VCO by the phase comparator.

  However, when the accuracy of the frequency comparator is low, it is difficult to draw it into the narrow PLL lock range of the phase comparator, so that a highly accurate frequency comparator is required. In order to increase the accuracy of the frequency comparator, it is common to use a clock signal having a high frequency or lengthen the period for measuring the frequency. In the former case, it is disadvantageous in terms of power consumption and circuit scale. In the latter case, the frequency change within the measurement period is averaged, so the frequency control of the data recording clock signal WCLK is performed at the time of PLL pull-in. Therefore, even if the frequency detection circuit in the frequency comparator detects the frequency coincidence and immediately switches to the phase comparison, the data recording clock signal WCLK is already out of the PLL lock range at that time. To do. In order to deal with this problem, there is a method of detecting whether or not the frequencies coincide with each other, but there is a problem that it takes time to pull in the PLL.

  The present invention has been made in order to solve the above-described problems. The PLL lock range of the phase comparator is expanded without using a high-precision frequency comparator, and the PLL to the wobble signal can be quickly performed. It is an object of the present invention to obtain a data recording clock signal generation circuit capable of performing pull-in.

The data recording clock signal generation circuit according to the present invention includes data for recording data on the optical disc, wherein the data recording track on the writable optical disc is previously wobbled and phase-synchronized with the recorded wobble signal. In a data recording clock signal generation circuit comprising a PLL circuit that generates and outputs a data recording clock signal used to obtain a write timing,
A frequency dividing circuit for generating and outputting a first frequency-divided clock signal and a second frequency-divided clock signal, respectively, obtained by dividing the data recording clock signal by different predetermined frequency division ratios;
A phase comparison circuit unit that compares the phase of the wobble signal and the first frequency-divided clock signal and generates and outputs a phase control signal indicating the comparison result;
A frequency comparison circuit that compares the frequencies of the wobble signal and the first frequency-divided clock signal and generates and outputs a frequency control signal indicating the comparison result;
From the transition of combinations of signal levels in the first divided clock signal and the second divided clock signal with respect to the time when the wobble signal changes to a predetermined signal level, the phase of the first divided clock signal with respect to the wobble signal is changed. A phase detection circuit unit that performs state detection and generates and outputs a phase state signal indicating the detected phase state;
A data recording clock signal generation circuit unit that generates and outputs the data recording clock signal having a frequency adjusted according to the phase control signal, the frequency control signal, and the phase state signal;
With
The data recording clock signal generation circuit unit adjusts the frequency of the data recording clock signal in accordance with the phase control signal when the frequency difference between the wobble signal and the first divided clock signal is less than a predetermined value. When the phase state signal indicates that the phase of the first frequency-divided clock signal advances from the wobble signal, the degree of decreasing the frequency of the data recording clock signal is increased, and the frequency adjustment is performed. The speed to be performed is changed according to the phase state signal.

  In addition, the data recording clock signal generation circuit unit, when the phase state signal indicates that the phase of the first divided clock signal is delayed from the wobble signal, the frequency of the data recording clock signal Increased the degree of raising

  The data recording clock signal generation circuit unit adjusts the frequency of the data recording clock signal according to the frequency control signal when the frequency difference between the wobble signal and the first frequency-divided clock signal is equal to or greater than the predetermined value. To do.

  Further, the data recording track of the optical disc has a predetermined frequency component and is wobbled with a wobble signal in which address information and a synchronization signal are superimposed by phase modulation at a predetermined timing, and the address information and the synchronization signal are phase-modulated. The phase comparison circuit unit may stop outputting the phase control signal and the phase detection circuit unit may stop outputting the phase state signal during the period superimposed on the wobble signal. .

  Specifically, the phase comparison circuit unit and the phase detection circuit unit receive a predetermined signal from the outside during a period in which address information and a synchronization signal are superimposed on the wobble signal by phase modulation. While the signal is being input, the phase comparison circuit unit stops outputting the phase control signal, and the phase detection circuit unit stops outputting the phase state signal.

  According to the data recording clock signal generation circuit of the present invention, the data recording clock signal generation circuit unit is configured to output the phase control signal when the frequency difference between the wobble signal and the first frequency-divided clock signal is less than a predetermined value. Since the frequency of the data recording clock signal is adjusted according to the frequency and the speed of the frequency adjustment is changed according to the phase state signal, the phase comparison can be performed without using a high-precision frequency comparison circuit. The PLL lock range of the circuit unit can be expanded to quickly and easily pull the PLL into the wobble signal, and the seek access time can be shortened.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a configuration example of an optical disc reproducing / recording apparatus using a data recording clock signal generating circuit according to the first embodiment of the present invention.
In FIG. 1, an optical disk reproducing / recording apparatus 1 performs data recording on an optical disk 2 of CD-R / RW, DVD + R / RW, and DVD-R / RW, and rotates the optical disk 2 by a spindle motor 3. The spindle motor 3 is rotationally controlled by a motor driver 4. The optical pickup 5 that reads and writes data from and to the optical disk 2 includes a semiconductor laser, an optical system, a focus actuator, a track actuator, a light receiving element, a position sensor, and the like (not shown). Data is read and written by irradiating the optical disk 2.

  In an optical disc 2 such as a CD-R / RW, a DVD-R / RW, or a DVD + R / RW, there is a data recording track that is wobbled by a wobble signal having a predetermined frequency component. In the case of performing so-called data reproduction in which data on the optical disk 2 is read, the reproduction signal read by the optical pickup 5 is amplified by the amplifier 6 and binarized. The data decoder 7 decodes the data amplified and binarized by the amplifier 6 by a predetermined method and outputs it as reproduced data.

  When so-called data recording is performed in which data is written on the optical disc 2, the wobble signal on the optical disc 2 is read by the optical pickup 5, and the wobble signal is amplified by the amplifier 6, and in some cases, the wobble signal is binarized and wobbled. Output as signal WBL. The data recording clock signal generation circuit 8 generates and outputs a data recording clock signal WCLK synchronized with the wobble signal WBL. The synchronization detection circuit 9 and the address decoder 10 detect the synchronization signal and address information superimposed on the wobble signal WBL, respectively. The data encoder 11 performs predetermined modulation processing on the recording data in synchronization with the data recording clock signal WCLK, and the LD driver 12 modulates the intensity of the laser beam emitted from the optical pickup 5 in accordance with the modulated recording data. To do. In this manner, data recording is performed in synchronization with the wobble signal of the data recording track of the optical disc 2.

FIG. 2 is a block diagram showing an internal configuration example of the data recording clock signal generation circuit according to the first embodiment of the present invention, and shows an internal configuration example of the data recording clock signal generation circuit 8 of FIG. ing.
In FIG. 2, a data recording clock signal generation circuit 8 forms a so-called PLL (Phase Locked Loop) circuit, and includes a phase comparator 21, a first charge pump circuit 22, a filter 23, a VCO (Voltage Controlled Oscillator) 24, a frequency divider. 25, a frequency comparator 26, a second charge pump circuit 27, a multiplexer 28, a phase detector 29, a phase transition detection circuit 30, a first duty adjustment circuit 31, and a second duty adjustment circuit 32. The phase comparator 21 is a phase comparison circuit unit, the frequency divider 25 is a frequency division circuit unit, the frequency comparator 26 is a frequency comparison circuit unit, and the phase detector 29 and the phase transition detection circuit 30 are phase detection circuit units. Make each. The first charge pump circuit 22, the filter 23, the VCO 24, the second charge pump circuit 27, the multiplexer 28, the first duty adjustment circuit 31 and the second duty adjustment circuit 32 constitute a data recording clock signal generation circuit section.

  The phase comparator 21 compares the phase difference between the wobble signal WBL and the first frequency-divided clock signal Sfd1, which is a signal obtained by frequency-dividing the data recording clock signal WCLK by the frequency divider 25 with a predetermined ratio. For example, the phase comparator 21 compares the rising edges of the wobble signal WBL and the first divided clock signal Sfd1. When the rising edges of the wobble signal WBL and the first divided clock signal Sfd1 are the same, the phase comparator 21 is a down signal obtained by inverting the signal levels of the up signal SPu and the up signal SPu that form a pulse signal with a duty cycle of 50%. Each of the signals SPd is output. Further, when the rising edge of the wobble signal WBL is input prior to the rising edge of the first divided clock signal Sfd1, the phase comparator 21 is in a state where the duty cycle of the up signal SPu is set to 50%. Only the duty cycle of the down signal SPd is reduced and output.

  Further, when the rising edge of the first frequency-divided clock signal Sfd1 is input before the rising edge of the wobble signal WBL, the phase comparator 21 sets the duty cycle of the down signal SPd to 50%. Only the duty cycle of the up signal SPu is reduced and output. The up signal SPu output from the phase comparator 21 is output to the first duty adjustment circuit 31, and the down signal SPd output from the phase comparator 21 is output to the second duty adjustment circuit 32.

The frequency divider 25 generates and outputs a first frequency-divided clock signal Sfd1 from the data recording clock signal WCLK and generates a second frequency-divided clock signal Sfd2 having a frequency twice that of the first frequency-divided clock signal Sfd1. Output. The frequency divider 25 outputs the first divided clock signal Sfd1 and the second divided clock signal Sfd2 in phase with each other.
The phase detector 29 receives the wobble signal WBL, the first divided clock signal Sfd1 and the second divided clock signal Sfd2, respectively. The phase detector 29 receives the wobble signal WBL and the first divided clock signal Sfd1. The phase relationship between and is detected. In other words, the phase of the edge of the wobble signal WBL is detected and output with reference to the first frequency-divided clock signal Sfd1.

FIG. 3 is a timing chart showing an operation example of the phase detector 29. The operation of the phase detector 29 will be described with reference to FIG. FIG. 3 shows an example in which the data recording clock signal WCLK has a frequency 32 times that of the wobble signal WBL.
The phase detector 29 is one of four types of signals from SA to SD according to the states of the first divided clock signal Sfd1 and the second divided clock signal Sfd2 at the time when the signal level of the wobble signal WBL rises. Output one. For example, the phase detector 29 outputs the signal SA if the first frequency-divided clock signal Sfd1 and the second frequency-divided clock signal Sfd2 are at the low level at the rise of the signal level in the wobble signal WBL. If the 1-frequency-divided clock signal Sfd1 and the second-frequency-divided clock signal Sfd2 are each at a high level, the signal SB is output.

Further, the phase detector 29 outputs the signal SC when the first divided clock signal Sfd1 is at the high level and the second divided clock signal Sfd2 is at the low level at the rise of the signal level in the wobble signal WBL. If the divided clock signal Sfd1 is at a low level and the second divided clock signal Sfd2 is at a high level, the signal SD is output.
That is, when the phase detector 29 outputs the signal SA, it indicates that the phase of the first divided clock signal Sfd1 is delayed by 0 ° to 90 ° with respect to the wobble signal WBL. When the signal SB is output, it indicates that the phase of the first divided clock signal Sfd1 is advanced by 0 ° to 90 ° with respect to the wobble signal WBL. Further, when the phase detector 29 outputs the signal SC, it indicates that the phase of the first divided clock signal Sfd1 is advanced by 90 ° to 180 ° with respect to the wobble signal WBL. When the signal SD is output, it indicates that the phase of the first divided clock signal Sfd1 is delayed by 90 ° to 180 ° with respect to the wobble signal WBL.

  When the phase is locked, the phase detector 29 alternately outputs the signal SA and the signal SB for fluctuations specific to feedback control. When the first frequency-divided clock signal Sfd1 is slightly higher in frequency than the wobble signal WBL, the phase detector 29 makes a cyclic transition in the order of the signals SA, SB, SC, SD, and SA and outputs the result. Conversely, when the first frequency-divided clock signal Sfd1 is slightly lower in frequency than the wobble signal WBL, the phase detector 29 makes a cyclic transition in the order of the signals SA, SD, SC, SB, and SA and outputs the result.

  On the other hand, the phase transition detection circuit 30 monitors the transition of the output signal of the phase detector 29, and when the signal SA and the signal SB are alternately output from the phase detector 29, that is, when the phase is locked, The level up signal Sup is output to the first duty adjustment circuit 31 and the low level down signal Sdw is output to the second duty adjustment circuit 32. Further, the phase transition detection circuit 30 outputs the low-level up signal Sup to the first duty adjustment circuit 31 when the output signal from the phase detector 29 is cyclically transited in the order of the signals SA, SD, SC, SB, and SA. And a down signal Sdw of a pulse signal whose duty cycle is a predetermined value less than 50% is output to the second duty adjustment circuit 32.

  Further, the phase transition detection circuit 30 outputs the low level down signal Sdw to the second duty adjustment circuit 32 when the output signal from the phase detector 29 is cyclically shifted in the order of the signals SA, SB, SC, SD, SA. And an up signal Sup of a pulse signal having a predetermined value with a duty cycle of less than 50% is output to the first duty adjustment circuit 31. The phase transition detection circuit 30 adjusts the up signal Sup to the phase of the up signal SPu when outputting the up signal Sup forming the pulse signal, and outputs the down signal Sdw as the down signal when outputting the down signal Sdw forming the pulse signal. It is preferable to match the phase of SPd. The up signal SPu and the down signal SPd are phase control signals, the up signal SFu and the down signal SFd are frequency control signals, and the up signal Sup and the down signal Sdw are phase state signals.

When the up signal Sup having a predetermined duty cycle is input from the phase transition detection circuit 30, the first duty adjustment circuit 31 has a duty of the up signal SPu input from the phase comparator 21 in accordance with the duty cycle of the up signal Sup. The cycle is reduced and output to the first charge pump circuit 22. When the low-level up signal Sup is input from the phase transition detection circuit 30, the first duty adjustment circuit 31 outputs the up signal SPu input from the phase comparator 21 to the first charge pump circuit 22 as it is. .
Similarly, when the down signal Sdw having a predetermined duty cycle is input from the phase transition detection circuit 30, the second duty adjustment circuit 32 receives the down signal input from the phase comparator 21 in accordance with the duty cycle of the down signal Sdw. The duty cycle of SPd is reduced and output to the first charge pump circuit 22. Further, when the low-level down signal Sdw is input from the phase transition detection circuit 30, the second duty adjustment circuit 32 outputs the down signal SPd input from the phase comparator 21 to the first charge pump circuit 22 as it is. .

  The first charge pump circuit 22 has an output terminal in a high impedance state while the input up signal SPu and the down signal SPd are both at a low level, the up signal SPu is at a high level, and the down signal SPd is at a low level. A high level signal is output to the multiplexer 28 for a certain period, and a low level signal is output to the multiplexer 28 while the up signal SPu is at a low level and the down signal SPd is at a high level.

On the other hand, the frequency comparator 26 compares the frequencies of the wobble signal WBL and the first divided clock signal Sfd1.
For example, the frequency comparator 26 compares the rising edge intervals of the wobble signal WBL and the first divided clock signal Sfd1. When the frequencies of the wobble signal WBL and the first divided clock signal Sfd1 are the same, the frequency comparator 26 is a down signal obtained by inverting the signal levels of the up signal SFu and the up signal SFu that form a pulse signal with a duty cycle of 50%. Each of the signals SFd is output. In addition, when the frequency of the wobble signal WBL is higher than the frequency of the first frequency-divided clock signal Sfd1, the frequency comparator 26 calculates only the duty cycle of the down signal SFd with the duty cycle of the up signal SFu being 50%. Output smaller.

Further, when the frequency of the wobble signal WBL is lower than the frequency of the first divided clock signal Sfd1, the frequency comparator 26 calculates only the duty cycle of the up signal SFu with the duty cycle of the down signal SFd being 50%. Output smaller. The up signal SFu and the down signal SFd output from the frequency comparator 26 are output to the second charge pump circuit 27, respectively.
In the second charge pump circuit 27, while the input up signal SFu and the down signal SFd are both at the low level, the output terminal is in a high impedance state, the up signal SFu is at the high level, and the down signal SFd is at the low level. A high level signal is output to the multiplexer 28 for a certain period, and a low level signal is output to the multiplexer 28 while the up signal SFu is at a low level and the down signal SFd is at a high level.

  Here, the frequency comparator 26 constantly detects the frequency difference between the wobble signal WBL and the first frequency-divided clock signal Sfd1, and when the detected frequency difference is equal to or greater than a predetermined value F1, 2 The output voltage of the charge pump circuit 27 is controlled to be output to the filter 23. Further, when the frequency difference between the wobble signal WBL and the first frequency-divided clock signal Sfd1 becomes less than the predetermined value F1, the frequency comparator 26 sends the output voltage of the first charge pump circuit 22 to the filter 23 with respect to the multiplexer 28. Control to output. The filter 23 smoothes the signal input from the multiplexer 28 and outputs it to the VCO 24 as a control voltage Vcnt. The VCO 24 generates a data recording clock signal WCLK having a frequency corresponding to the voltage value of the input control voltage Vcnt. Output. As a result, the phase of the data recording clock signal WCLK is synchronized with the wobble signal WBL.

The operation of the frequency comparator 26 may be as follows.
The frequency comparator 26 compares the rising edge intervals of the wobble signal WBL and the first divided clock signal Sfd1. When the frequencies of the wobble signal WBL and the first frequency-divided clock signal Sfd1 are the same, the frequency comparator 26 outputs both the up signal SFu and the down signal SFd at a low level. In addition, when the frequency of the wobble signal WBL is higher than the frequency of the first frequency-divided clock signal Sfd1, the frequency comparator 26 sets the down signal SFd to a low level in a state where the up signal SFu is output at a predetermined duty cycle. Output. Further, when the frequency of the wobble signal WBL is lower than the frequency of the first divided clock signal Sfd1, the frequency comparator 26 sets the up signal SFu to the low level in a state where the down signal SFd is output at a predetermined duty cycle. Output. The up signal SFu and the down signal SFd output from the frequency comparator 26 are output to the second charge pump circuit 27, respectively.

  As described above, in the data recording clock signal generation circuit according to the first embodiment, the phase detector 29 has the first divided clock signal Sfd1 and the second divided clock signal Sfd2 at the rising edge of the wobble signal WBL. From the order of the signals SA to SD output according to the state of the signal, the phase of the edge of the wobble signal WBL is detected with reference to the first frequency-divided clock signal Sfd1, and the data is determined according to the detection result. The duty cycle of the up signal SPu and the down signal SPd, which are output signals of the phase comparator 21, is adjusted so that the change in the frequency of the recording clock signal WCLK becomes faster. Therefore, the PLL lock range of the phase comparator can be expanded without using a high-accuracy frequency comparator, and the PLL can be quickly pulled into the wobble signal.

Second embodiment.
In the first embodiment, the first charge pump circuit 22 and the second charge pump circuit 27 output pulse signals having signal levels corresponding to combinations of signal levels of the input pulse signals. A current-controlled charge pump that outputs a current in a direction corresponding to the combination of the signal levels of the input pulse signals may be formed. This is the same as the second embodiment of the present invention. To do.
FIG. 4 is a block diagram showing an example of the internal configuration of a data recording clock signal generation circuit according to the second embodiment of the present invention. The diagram showing the configuration example of the optical disk reproducing / recording apparatus using the data recording clock signal generating circuit in the second embodiment of the present invention is the same as that shown in FIG. 1 except that the code of the data recording clock signal generating circuit is changed. Since it is the same as, it is omitted. 4, the same or similar parts as those in FIG. 2 are denoted by the same reference numerals as those in FIG. 2, and description thereof is omitted here, and only differences from FIG. 2 will be described.

  4 differs from FIG. 2 in that the first duty adjustment circuit 31 and the second duty adjustment circuit 32 in FIG. 2 are eliminated, and the first charge pump circuit 22 and the second charge pump circuit 27 in FIG. A current-controlled charge pump that outputs a pulse signal having a signal level corresponding to a combination of signal levels of each pulse signal but outputs a current in a direction corresponding to the combination of signal levels of each input pulse signal. Accordingly, the first charge pump circuit 22 of FIG. 1 is replaced with the first charge pump circuit 22a, and the second charge pump circuit 27 of FIG. 1 is replaced with the second charge pump circuit 27a. The filter 23 of FIG. 1 is replaced with a filter 23a, the phase transition detection circuit 30 of FIG. 1 is replaced with a phase transition detection circuit 30a, and the data recording clock of FIG. And a signal generating circuit 8 to the data recording clock signal generation circuit 8a.

  In FIG. 4, the data recording clock signal generation circuit 8a includes a phase comparator 21, a first charge pump circuit 22a, a filter 23a, a VCO 24, a frequency divider 25, a frequency comparator 26, a second charge pump circuit 27a, and a multiplexer 28. The phase detector 29 and the phase transition detection circuit 30a are provided. The phase detector 29 and the phase transition detection circuit 30a each constitute a phase detection circuit unit, and the first charge pump circuit 22a, the filter 23a, the VCO 24, the second charge pump circuit 27a, and the multiplexer 28 are data recording clock signal generation circuits. Part.

The up signal SPu and the down signal SPd output from the phase comparator 21 are respectively output to the first charge pump circuit 22a.
The phase transition detection circuit 30a monitors the transition of the output signal of the phase detector 29, and outputs an up signal Sup and a down signal Sdw that form flags in accordance with the transition of the output signal. When the signal SA and the signal SB are alternately output from the phase detector 29, the phase transition detection circuit 30a outputs a low level up signal Sup and a low level down signal Sdw to the first charge pump circuit 22a. .

  The phase transition detection circuit 30a outputs the low-level up signal Sup to the first charge pump circuit while the output signal from the phase detector 29 is cyclically transited in the order of the signals SA, SD, SC, SB, and SA. The high level down signal Sdw is output to the first charge pump circuit 22a. In addition, the phase transition detection circuit 30a outputs the low level down signal Sdw to the first charge pump circuit while the output signal from the phase detector 29 is cyclically transited in the order of the signals SA, SB, SC, SD, and SA. The high level up signal Sup is output to the first charge pump circuit 22a.

FIG. 5 is a diagram showing an operation example of the first charge pump circuit 22a. The operation of the first charge pump circuit 22a will be described with reference to FIG.
The first charge pump circuit 22a outputs a current having a predetermined current value i1 when the up signal SPu is high level and the down signal SPd is low level, and when the up signal SPu is low level and the down signal SPd is high level. A current having a predetermined negative current value i2 is output, that is, a current having a current value i2 is sucked. The first charge pump circuit 22a has an output terminal in a high impedance state when both the up signal SPu and the down signal SPd are at a low level. Further, when the high level up signal Sup is input from the phase transition detection circuit 30a, the first charge pump circuit 22a increases the current value i1 to a predetermined value i3 and outputs the same, and the high level from the phase transition detection circuit 30a. When the down signal Sdw is input, the absolute value of the current value i2 is increased to a predetermined value i4 and sucked.

  On the other hand, the second charge pump circuit 27a outputs a current having a predetermined current value i5 when the up signal SFu is at a high level and the down signal SFd is at a low level, and the up signal SFu is at a low level and the down signal SFd is at a high level. When a current having a predetermined negative current value i6 is output, that is, a current having a current value i6 is sucked. Further, the output terminal of the second charge pump circuit 27a is in a high impedance state when both the up signal SFu and the down signal SFd are at a low level. When the PLL is locked, currents of current values i1 and i2 alternately flow for the same time and the absolute values of current values i1 and i2 are equal. Similarly, currents of current values i5 and i6 alternately flow for the same time and current The absolute values of the values i5 and i6 are equal.

  Here, the frequency comparator 26 constantly detects the frequency difference between the wobble signal WBL and the first frequency-divided clock signal Sfd1, and when the detected frequency difference is equal to or greater than a predetermined value F1, Control is performed so that the output terminal of the 2-charge pump circuit 27a is connected to the filter 23a. Further, when the frequency difference between the wobble signal WBL and the first divided clock signal Sfd1 becomes less than the predetermined value F1, the frequency comparator 26 uses the output terminal of the first charge pump circuit 22a as a filter 23a for the multiplexer 28. Control to connect. The filter 23a converts the current input / output via the multiplexer 28 into a voltage, and further smoothes it to output it to the VCO 24 as the control voltage Vcnt.

  As described above, in the data recording clock signal generation circuit according to the second embodiment, the phase detector 29 has the first frequency-divided clock signal Sfd1 and the second frequency-divided when the signal level rises in the wobble signal WBL. From the order of the signals SA to SD to be output according to the state of the clock signal Sfd2, the phase of the edge of the wobble signal WBL is detected with reference to the first frequency-divided clock signal Sfd1, and according to the detection result Therefore, the current value input / output to / from the first charge pump circuit 22a is increased so that the frequency change of the data recording clock signal WCLK becomes faster. From this, the same effect as the first embodiment can be obtained.

Third embodiment.
When address information and synchronization information are superimposed on the wobble signal by phase modulation, the phase of the wobble signal in the phase modulation portion is shifted by 180 ° as shown in FIG. Similarly to the phase comparator 21, the unit 29 cannot detect a correct phase difference. For this reason, in such a phase modulation portion, the phase difference may not be detected by the phase comparator 21 and the phase detector 29. Such a configuration is the same as that of the third embodiment of the present invention. To do.
FIG. 7 is a diagram showing a configuration example of an optical disc reproducing / recording apparatus using a data recording clock signal generating circuit according to the third embodiment of the present invention. 7 that are the same as or similar to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof will be omitted here, and only differences from FIG. 1 will be described.

7 differs from FIG. 1 in that the data recording clock signal generation circuit 8 in FIG. 1 is replaced with the data recording clock signal generation circuit 8b, and the synchronization detection circuit 9 in FIG. 1 generates the phase comparison mask signal Sm. 1 is output to the data recording clock signal generation circuit 8b. Accordingly, the synchronization detection circuit 9 of FIG. 1 is changed to the synchronization detection circuit 9b, and the optical disk reproduction / recording apparatus 1 of FIG. 1 is changed to the optical disk reproduction / recording apparatus. 1b respectively.
In FIG. 7, the synchronization detection circuit 9b generates the phase comparison mask signal Sm and outputs it to the data recording clock signal generation circuit 8b. As shown in FIG. 8, the synchronization signal and address signal are read out from the optical disc 2. The phase comparison mask signal Sm is set to the high level.

FIG. 9 is a block diagram showing an example of the internal configuration of a data recording clock signal generation circuit according to the third embodiment of the present invention, and shows a case having the configuration of FIG. 9, the same or similar parts as those in FIG. 2 are denoted by the same reference numerals as those in FIG. 2, and the description thereof will be omitted here and only the differences from FIG. 2 will be described.
9 is different from FIG. 2 in that the phase comparison mask signal Sm is input from the outside to the phase comparator 21 and the phase detector 29 in FIG. 2 and the phase comparison mask signal Sm is in the high level. The device 21 is such that each output terminal that outputs the up signal SPu and the down signal SPd is set to low level, and the phase transition detection circuit 30 is configured to set the output terminal to low level. Accordingly, the phase comparator 21 shown in FIG. 2 adds the phase comparator 21b, the phase transition detection circuit 30 shown in FIG. 2 to the phase transition detection circuit 30b, and the data recording clock signal generation circuit 8 shown in FIG. 2 for data recording. The clock signal generation circuit 8b is used.

In FIG. 9, the data recording clock signal generation circuit 8b includes a phase comparator 21b, a first charge pump circuit 22, a filter 23, a VCO 24, a frequency divider 25, a frequency comparator 26, a second charge pump circuit 27, and a multiplexer 28. , A phase detector 29, a phase transition detection circuit 30b, a first duty adjustment circuit 31, and a second duty adjustment circuit 32. The phase comparator 21b forms a phase comparison circuit unit, and the phase detector 29 and the phase transition detection circuit 30b form a phase detection circuit unit.
The phase comparison mask signal Sm is input to each of the phase comparator 21b and the phase transition detection circuit 30b. When the phase comparison mask signal Sm becomes high level, the output terminal of the phase comparator 21b and the phase transition detection circuit 30b Each output terminal is at a low level.

  When the output terminal of the phase transition detection circuit 30b becomes a low level, the output terminal of the first charge pump circuit 22 enters a high impedance state. At this time, when the multiplexer 28 is controlled to output the output voltage of the first charge pump circuit 22 to the filter 23, the VCO 24 is a data recording clock having a frequency corresponding to the voltage held by the filter 23. The signal WCLK is output. However, since the time during which the phase comparison mask signal Sm is high is short, even if the VCO 24 outputs the data recording clock signal WCLK having a frequency corresponding to the voltage held by the filter 23 Will not occur.

  In the case of the data recording clock signal generation circuit 8a in FIG. 4, as in the case of FIG. 9, when the phase comparison mask signal Sm becomes high level, the output terminals of the phase comparator 21 and the phase transition detection circuit 30a are Each becomes low level, and the output terminal of the first charge pump circuit 22a enters a high impedance state. At this time, similarly to the case of FIG. 9, when the multiplexer 28 is controlled to output the output voltage of the first charge pump circuit 22a to the filter 23a, the VCO 24 corresponds to the voltage held by the filter 23a. A data recording clock signal WCLK having a predetermined frequency is output.

  As described above, the data recording clock signal generation circuit according to the third embodiment has a phase in which address information and synchronization information are superimposed on the wobble signal by phase modulation in each of the first and second embodiments. Since the phase difference is not detected by the phase comparator and the phase detector in the modulation portion, the same effects as those of the first and second embodiments can be obtained, and the phase comparator can be obtained. In addition, it is possible to prevent erroneous detection of the phase difference between the wobble signal WBL and the first divided clock signal Sfd1 by the phase detector, and to improve the reliability.

1 is a diagram showing a configuration example of an optical disc reproducing / recording apparatus using a data recording clock signal generation circuit according to a first embodiment of the present invention. FIG. 3 is a block diagram illustrating an internal configuration example of a data recording clock signal generation circuit according to the first embodiment of the present invention. 3 is a timing chart showing an operation example of the phase detector 29 in FIG. 2. It is the block diagram which showed the example of an internal structure of the clock signal generation circuit for data recording in the 2nd Embodiment of this invention. FIG. 5 is a diagram showing an operation example of a first charge pump circuit 22a of FIG. It is the figure which showed the example of the wobble signal of a phase modulation part. It is the figure which showed the structural example of the optical disk reproduction | regeneration recording device using the clock signal generation circuit for data recording in the 3rd Embodiment of this invention. It is the figure which showed the example of the phase comparison mask signal Sm. It is the block diagram which showed the example of an internal structure of the clock signal generation circuit for data recording in the 3rd Embodiment of this invention. It is a block diagram showing a configuration example of a conventional data recording clock signal generation circuit. It is the block diagram which showed the other structural example of the conventional clock signal generation circuit for data recording.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1b Optical disk reproduction | regeneration recording / recording apparatus 2 Optical disk 6 Amplifier 8, 8a, 8b Data recording clock signal generation circuit 9, 9b Synchronization detection circuit 21 Phase comparator 22, 22a First charge pump circuit 23, 23a Filter 24 VCO
25 Frequency Divider 26 Frequency Comparator 27, 27a Second Charge Pump Circuit 28 Multiplexer 29, 29b Phase Detector 30, 30a, 30b Phase Transition Detection Circuit 31 First Duty Adjustment Circuit 32 Second Duty Adjustment Circuit

Claims (5)

A data recording clock signal used for obtaining a data writing timing when data is recorded on the optical disk, which is phase-synchronized with a wobble signal recorded by previously wobbling a data recording track on the writable optical disk In a data recording clock signal generation circuit comprising a PLL circuit that generates and outputs
A frequency dividing circuit for generating and outputting a first frequency-divided clock signal and a second frequency-divided clock signal, respectively, obtained by dividing the data recording clock signal by different predetermined frequency division ratios;
A phase comparison circuit unit that compares the phase of the wobble signal and the first frequency-divided clock signal and generates and outputs a phase control signal indicating the comparison result;
A frequency comparison circuit that compares the frequencies of the wobble signal and the first frequency-divided clock signal and generates and outputs a frequency control signal indicating the comparison result;
From the transition of combinations of signal levels in the first divided clock signal and the second divided clock signal with respect to the time when the wobble signal changes to a predetermined signal level, the phase of the first divided clock signal with respect to the wobble signal is changed. A phase detection circuit unit that performs state detection and generates and outputs a phase state signal indicating the detected phase state;
A data recording clock signal generation circuit unit that generates and outputs the data recording clock signal having a frequency adjusted according to the phase control signal, the frequency control signal, and the phase state signal;
With
The data recording clock signal generation circuit unit adjusts the frequency of the data recording clock signal in accordance with the phase control signal when the frequency difference between the wobble signal and the first divided clock signal is less than a predetermined value. When the phase state signal indicates that the phase of the first frequency-divided clock signal advances from the wobble signal, the degree of decreasing the frequency of the data recording clock signal is increased, and the frequency adjustment is performed. A clock signal generating circuit for data recording, wherein a speed to perform is changed according to the phase state signal. The data recording clock signal generation circuit unit increases the frequency of the data recording clock signal when the phase state signal indicates that the phase of the first divided clock signal is delayed with respect to the wobble signal. 2. The data recording clock signal generating circuit according to claim 1, wherein the data recording clock signal generating circuit is increased. The data recording clock signal generation circuit adjusts the frequency of the data recording clock signal according to the frequency control signal when the frequency difference between the wobble signal and the first frequency-divided clock signal is equal to or greater than the predetermined value. 3. The data recording clock signal generation circuit according to claim 1, wherein the data recording clock signal generation circuit is a data recording clock signal generation circuit. The data recording track of the optical disc is wobbled with a wobble signal having a predetermined frequency component and address information and a synchronization signal superimposed by phase modulation at a predetermined timing, and the address information and the synchronization signal are converted by the phase modulation. The phase comparison circuit unit stops outputting the phase control signal and the phase detection circuit unit stops outputting the phase state signal during a period of being superimposed on the wobble signal. 4. A data recording clock signal generation circuit according to any one of 1, 2, or 3. The phase comparison circuit unit and the phase detection circuit unit receive a predetermined signal from the outside and input the predetermined signal while the address information and the synchronization signal are superimposed on the wobble signal by phase modulation. 5. The data recording clock signal according to claim 4 , wherein the phase comparison circuit unit stops outputting the phase control signal and the phase detection circuit unit stops outputting the phase state signal. Generation circuit.

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