JP4618454B2 - Timing signal generator - Google Patents

Description

  The present invention relates to a timing signal generating device, a timing signal generating method, and an optical disc information recording / reproducing device, and in particular, a timing signal generating device capable of recording information at an arbitrary location on an optical disc, and a timing signal generating method. The present invention relates to an optical disc information recording / reproducing apparatus.

  In recent years, digital cameras, DVD (Digital Versatile Disc) players, DVD recorders, and the like are rapidly spreading. Along with this, it has become commonplace for individuals to record or reproduce large volumes of digital data including video data as well as music data. In order to store the video information, inexpensive media such as DVD-R / + R are widely used, and these media can be played back on a DVD player after recording.

  DVD media that can be recorded include DVD-R and DVD + R that can be recorded only once. Furthermore, there are rewritable DVD-RW, DVD + RW, and DVD-RAM. There are roughly three types of information recording methods for these optical discs. The first recording method is a disc-at-once recording method in which the entire surface of the disc is recorded all at once with so-called one-stroke writing. The second recording method is an incremental recording method in which additional recording is performed in a free disk area using a mechanism called multi-border. The third recording method is a packet write recording method that is not compatible with DVD-ROM reproduction but can perform additional recording efficiently. However, the DVD-RAM is not compatible with the DVD-ROM drive because the pre-pit address is embedded on the disc.

  The information reproduction of the optical disc will be described. Concentric or spiral guide grooves (tracks) are formed on the optical disk medium, and minute information pits are formed along the tracks. The optical disk apparatus irradiates a focused laser beam onto a disk medium recording surface that is rotated by a spindle motor. At this time, focusing servo is applied so that the distance between the disc surface and the beam focusing objective lens is constant. Further, tracking servo is applied to the disk radial direction so that the focused beam follows the track. An optical disc information recording / reproducing apparatus detects the brightness and polarization of reflected light, which changes due to minute information pits formed on the disc, as an electrical signal. The optical disk information recording / reproducing apparatus performs a filtering process on the RF (Radio Frequency) signal, extracts a synchronization clock by a PLL (Phase Locked Loop), and identifies the RF signal as digital data at the synchronization timing. Thereafter, music or video information is extracted after performing RLL (Run Length Limited) demodulation and ECC (Error Correction Code) error correction.

  At the time of recording, conversely, ECC parity is added to user information, 8/16 modulation is performed, and information with a special code added to each frame is recorded on the disk in synchronization with the recording clock. At this time, by increasing the laser power, the temperature of the light condensing part rises, and the physical characteristics are reversibly or irreversibly changed to form minute pits.

  Incidentally, there are mainly two types of disk rotation control methods. That is, there are a CLV (Constant Linear Velocity) control method for keeping the linear velocity constant and a CAV (Constant Angular Velocity) control method for keeping the rotation angular velocity constant.

  However, there is a problem with CLV control. Since the spindle rotation speed changes about 2.4 times on the inner and outer circumferences, there is a point that a waiting time for spindle control is applied at the time of random access, and a point that much electric power is consumed. For this reason, an apparatus using the CAV control method is increasing.

  This is because in the CAV method, the spindle is always rotated at a constant speed, so that the waiting time for the rotational speed is shortened and the accessibility is improved. However, when a disc recorded by CLV control is played back by CAV control, the channel rate changes greatly in proportion to the radius.

  The recordable DVD guide grooves meander slightly in the disk radial direction. The meandering period is set to such an extent that the tracking servo cannot follow, and the meandering component can be detected as a wobble signal. This meander period is 32 times the channel clock period for DVD + R / RW and 186 times for DVD-R / RW, and a recording clock can be created by multiplying the meander period. In DVD-R / RW, pits called land pre-pits are formed in the land area at regular intervals, and address information on the disc is embedded. Also, DVD + R / RW has an area called ADIP (Address in Pre-groove) where a wobble signal is phase-modulated at a constant interval, and address information can be read by detecting this modulation. That is, in a recordable DVD excluding DVD-RAM, the recording clock and address information can be read from the wobble signal, so that user information can be recorded from an arbitrary position.

  Now, when information is additionally recorded after an already recorded area, or when information is overwritten on the recorded area, the previous data is erased if the recording position (linking position) is shifted forward. On the contrary, if it is shifted backward, an unrecorded gap area is formed. When a gap is formed, there is a high possibility that the servo will be lost during reproduction in a DVD player that performs tracking servo on the assumption that recording pits are continuous. Therefore, since the reproduction performance is deteriorated regardless of which direction is shifted, it is a problem to improve the accuracy of linking.

  As a cause of deteriorating linking accuracy, first, circuit system delay variation accompanying voltage variation or temperature variation can be cited. In this regard, Patent Document 1 (Japanese Patent Laid-Open No. 2002-319134) describes a solution. FIG. 16 is a block diagram for explaining the configuration of an optical disk information recording / reproducing apparatus according to the invention of Patent Document 1. In the invention disclosed in Patent Document 1, a recording signal input to the laser control unit 107 and an output signal extracted from the reproduction signal processing unit 103 using a laser beam power-modulated by the recording signal as a reproduction signal are delayed. The time is measured by the time measuring means 108. Further, the recording timing control unit 105 adjusts the recording timing based on the measurement result. As a result, the amount of delay can be measured without directly performing trial writing in the disk area, so that the linking position can be adjusted with high accuracy without consuming disk storage capacity.

  Another cause of deterioration in linking accuracy is a phase variation of the recording clock. The recording clock is generally generated by a PLL that is phase-synchronized with the wobble signal. However, when the disk eccentricity is large, the wobble signal is frequency-modulated, and PLL tracking cannot be performed in time, resulting in an error. As a result, it may appear as a phase variation of the recording clock. In particular, in the case of a disc having a low frequency wobble signal such as a DVD-R, the phase of the wobble signal is modulated by the influence of crosstalk from the adjacent track, and the phase of the recording clock generated based on the wobble signal is It is known to fluctuate. In this regard, for example, Patent Document 2 (Japanese Patent Application Laid-Open No. 2003-173535) describes a method of reproducing the immediately preceding recording data to generate an additional recording timing and accurately connecting the head of the additional recording data.

In relation to the above, Patent Document 3 (Japanese Patent Laid-Open No. 2005-182850) discloses an invention relating to a PLL circuit.
The PLL circuit of the invention of Patent Document 3 generates a reproduction clock that is synchronized with a reproduction signal from an optical disk having a synchronous pull-in pattern area and a data area. The PLL circuit includes a reproduction clock generation unit, a phase difference detection unit, and a correction signal generation unit. Here, the reproduction clock generation means is for generating a reproduction clock. The phase difference detecting means is for detecting the phase difference between the reproduction signal and the reproduction clock. The correction signal generation means is for generating a correction signal for correcting the phase difference. The regenerated clock generation means generates a regenerated clock using a signal indicating a phase difference and a correction signal as input signals.

Patent Document 4 (Japanese Patent Laid-Open No. 2006-331514) discloses an invention relating to an optical disk recording / reproducing apparatus.
The optical disk recording / reproducing apparatus of the invention of Patent Document 4 records and reproduces data on an optical disk. The optical disc recording / reproducing apparatus includes a spindle motor, a pickup, a disc distortion detection unit, and a control unit. Here, the spindle motor is for rotating the mounted optical disk. The pickup is for recording or reproducing data on an optical disc. The disc distortion detection unit is for detecting a change amount of the tracking error signal or the focus error signal due to the disc distortion from the reproduction signal of the pickup. The control unit is for controlling the rotation of the spindle motor and the recording or reproducing operation based on the detected change amount of the tracking error signal or the focus error signal. The control unit divides the data recording surface of the optical disc into a plurality of zones in the radial direction, and records or reproduces data by rotating the optical disc at a constant angular velocity from the inner circumference side to the outer circumference side, A change amount of the tracking error signal or the focus error signal is detected by the disk distortion detection unit at the boundary position of the zone. Further, when the amount of change exceeds a predetermined threshold, the control unit sequentially decreases the linear velocity of the optical disc rotation to detect the amount of change in the tracking error signal or the focus error signal, and the line where the amount of change is below the predetermined threshold. The speed is obtained, and the next zone is switched to a condition where the linear speed is constant according to the obtained linear speed, and the optical disk is rotated to record or reproduce data.

Patent Document 5 (Japanese Patent Laid-Open No. 2007-59018) discloses an invention relating to an information signal reproducing apparatus.
The information signal reproduction device of the invention of Patent Document 5 decodes a reproduction signal read from an information recording medium using maximum likelihood detection into a channel bit data string. This information signal reproducing apparatus includes an offset corrector and a maximum likelihood detector. Here, the offset corrector offset-corrects the reproduction signal so that the DC level of the shortest periodic signal included in the reproduction signal matches the central reference level included in the plurality of reference levels in maximum likelihood detection. Is to do. The maximum likelihood detector decodes the reproduction signal corrected by the offset corrector by maximum likelihood detection, and generates a channel bit data string.

Patent Document 6 (Japanese Patent Laid-Open No. 2007-95156) discloses an invention relating to a phase synchronization apparatus.
The phase synchronization apparatus of the invention of Patent Document 6 includes a PLL circuit, a pulse signal generation unit, a maximum sign inversion interval measurement unit, and a first channel frequency signal generation unit. Here, the PLL circuit is for generating a clock signal synchronized with the modulation signal from a modulation signal in which a special pattern including a predetermined run length that is equal to or greater than the upper limit of the run length limit code rule is periodically embedded. It is. The modulated signal is modulated with a run length limited code. The pulse signal generating means generates a pulse signal by pulsing the modulation signal in synchronization with the clock signal. The maximum sign inversion interval measuring means measures the sign inversion interval of the pulse signal when the PLL circuit is out of synchronization, and outputs the maximum value of the code inversion interval within the period longer than the embedding period of the special pattern as the maximum code inversion interval. Is to do. The first channel frequency signal generation means is for estimating the first channel frequency based on the maximum code inversion interval. When the PLL circuit is in an asynchronous state, the center frequency is set to the first channel frequency.

JP 2002-319134 A JP 2003-173535 A JP 2005-182850 A JP 2006-331514 A JP 2007-59018 A JP 2007-95156 A

  As described above, additional recording can be performed without gaps or overlaps by reproducing the recorded area and starting recording immediately thereafter. In this case, it is necessary to consider both the delay of the information reproduction processing unit and the delay until the recording information is converted into laser power and irradiated onto the disk as an offset. This delay includes a portion proportional to the channel clock period and a portion that occurs in a fixed manner. However, in the case of CAV recording, since the channel frequency changes about 2.4 times on the inner and outer circumferences, the recording timing is shifted due to the influence of the fixed delay portion. The delay variation caused by temperature and voltage variation is not so large. In consideration of this, it is considered that the factor that affects the linking accuracy when recording is performed by CAV control is mainly caused by the influence of the reproduction signal processing and the fixed delay of the recording signal processing unit.

  Let Tr be the delay time from when the laser light applied to the disk is reflected by the photodetector to when the synchronization timing is generated through the reproduction system circuit. Also, Tw is a delay time from when this synchronization timing is received until the laser power is modulated. There is a delay Tr_syn that is proportional to the channel clock period with respect to Tr, and a fixed delay Tr_asyn that does not depend on the channel clock. Tr_syn mainly corresponds to the delay of the binarization circuit synchronized with the read clock. Similarly, Tw has a delay Tw_syn that is proportional to the channel clock period and a fixed delay Tw_asyn that does not depend on the channel clock. When generating the additional recording timing, the delay corresponding to the sum Trw of Tr and Tw is taken into consideration, and it is necessary to output the additional recording start timing earlier by Trw than the synchronization timing.

Trw = Tr + Tw = Tr_syn + Tr_asyn + Tw_syn + Tw_asyn = Trw_syn + Trw_asyn (1)
Trw is divided into a fixed delay Trw_asyn and a channel clock synchronous proportional delay Trw_syn as shown in equation (1). If the channel clock period is T, Trw_syn / T = N (constant). Therefore, when generating the write-once timing, Trw_syn can be corrected without any problem even if the channel frequency changes by counting the channel clock and correcting the gate timing. However, Trw_asyn / T is a function of the channel clock frequency. FIG. 13 is a graph showing changes in the internal delay amount depending on the reproduction radius during CAV reproduction. On the inner circumference, the amount of delay in terms of T is small and increases on the outer circumference.

  For this reason, even if the method of Patent Document 2 is used, if recording is performed in accordance with the additional recording timing in accordance with the inner peripheral condition, a gap occurs at the linking position due to an increase in delay at the additional recording of the outer periphery. FIG. 11 is a diagram for explaining a case where a gap is generated at the linking position during additional recording on the optical disc. Conversely, if recording is performed in accordance with the outer peripheral conditions, an overlap occurs inside. FIG. 12 is a diagram for explaining a case where overlap occurs at the linking position during additional recording on the optical disc.

  On the other hand, in order to measure the delay amount using the method of Patent Document 1, it is necessary to perform measurement in an unrecorded area or generate a laser power that is somewhat high. This is because the reflected light from the recorded pits becomes noise. In general, a disc has a margin for preventing a recorded mark from being deformed or erased even if the reproduction power is slightly increased. However, performing delay measurement many times in the recorded area has a high risk of damaging the recorded area. Therefore, in order to construct a safe system, it is necessary to perform measurement after seeking to an unrecorded area and seek again to a recorded area, and a reduction in throughput is inevitable. In particular, when recording is performed by CAV control in which the channel frequency changes with the disk radius, the delay amount changes due to the influence of the fixed delay of the circuit system, so that there is a problem that the frequency of measurement increases and the throughput is greatly reduced. .

  An object of the present invention is to provide an optical disc information recording / reproducing apparatus that ensures linking accuracy without lowering throughput during additional recording even in CAV spindle control.

The timing signal generation apparatus according to the present invention includes synchronization detection means, correction amount calculation means, and timing correction means. Here, the synchronization detection means inputs an arbitrary input signal having a channel frequency from the optical disc , generates a predetermined frequency value proportional to the channel frequency, and a synchronization timing signal of the input signal, and outputs it. . The correction amount calculation means calculates and outputs a delay correction amount based on the frequency value. The timing correction means generates and outputs a correction timing signal based on the synchronization timing signal and the delay correction amount. The delay correction amount corrects the variable delay amount depending on the reading position on the optical disc and the fixed delay amount derived from the circuit system. The correction timing signal is corrected so that the phase relationship between the input signal and the correction timing signal is constant even when the channel frequency changes.

In the timing signal generation method according to the present invention, (a) an input signal having a channel frequency is input from an optical disc in the synchronization detection means, a predetermined frequency value proportional to the channel frequency, a synchronization timing signal of the input signal, (B) a correction amount calculating step for calculating and outputting a delay correction amount based on the frequency value, and (c) a timing correction unit for generating a synchronization timing. And a timing correction step of generating and outputting a correction timing signal based on the signal and the delay correction amount. The delay correction amount corrects the variable delay amount depending on the reading position on the optical disc and the fixed delay amount derived from the circuit system. The correction timing signal is corrected so that the phase relationship between the input signal and the correction timing signal is constant even when the channel frequency changes.

  The radius dependence of Trw_asyn in FIG. 13 depends on the circuit configuration and can be predicted without any elements that fluctuate other than the input frequency. That is, since the delay amount is a function of the channel frequency, the delay amount to be corrected can also be calculated from the channel frequency as shown in FIG. Therefore, the correction amount shown in FIG. 13 is calculated based on the oscillation frequency value of the PLL (41 in FIG. 1), and the timing is corrected by the timing correction means (6 in FIG. 1) using this. By doing so, it is possible to generate a write-once start timing signal that does not depend on the radius or the channel frequency as shown in FIG. That is, even if the input channel frequency fluctuates greatly, the write-once recording start timing is automatically corrected, so that occurrence of gaps and overlaps at the linking portion can be suppressed.

  The best mode for carrying out the timing signal generating apparatus according to the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of an optical disc information recording / reproducing device for explaining the operation of the timing signal generating device according to the first embodiment of the present invention. This optical disk information recording / reproducing apparatus includes an optical head 2, an amplifier 3, a synchronization detection unit 4, a correction amount calculation unit 5, a timing correction unit 6, a recording signal generation unit 7, and a laser control unit 8. To do. The synchronization detector 4 includes a PLL 41, binarization means 42, and a synchronization detector 43.

  The optical head 2 is connected to the amplifier 3. On the other hand, the amplifier 3 is connected to the synchronization detection means 4. In the synchronization detection means 4, the binarization means 42 is connected to the synchronization detector 43. On the other hand, the synchronization detector 43 is connected to the timing correction means 6. The PLL 41 of the synchronization detection unit 4 is connected to the correction amount calculation unit 5. On the other hand, the correction amount calculation means 5 is connected to the timing correction means 6. On the other hand, the timing correction means 6 is connected to the recording signal generation means 7. On the other hand, the recording signal generating means 7 is connected to the laser control means 8. On the other hand, the laser control means 8 is connected to the optical head 2.

  The spindle motor controls the rotation of the optical disk medium 1. In the head 2, a servo circuit (not shown) accurately controls the distance between the disk surface and the objective lens and the radial positional relationship between the disk guide groove and the focused spot.

  The focused spot is applied to the information mark recorded on the disc. Reflected light from the reflecting surface of the optical disk changes in reflectivity or polarization depending on the presence or absence of an information mark, and is converted into an electric signal by a photodetector (not shown) to obtain a reproduction signal.

  In the reproduction signal, the presence / absence of a recording mark is obtained as amplitude information. Since the reproduction signal is weak, it is amplified by the RF amplifier 3 and input to the synchronization detection means 4.

  The PLL 41 in the synchronization detection means 4 generates a recovered clock signal synchronized with the channel frequency. Further, the binarization circuit 42 generates binarized data synchronized with the reproduction clock signal.

  The synchronization detector 43 demodulates the binarized data, detects address information embedded in the data, and generates a synchronization timing signal for starting additional recording. The timing correction circuit 6 corrects the timing of the synchronization timing signal. As the correction amount, a value calculated by the delay amount calculation means 5 by reading the oscillation frequency value of the PLL 41 is used.

  The corrected timing signal (recording gate signal) is input to the recording signal generating means 7, and the recording signal generating means 7 controls the additional recording start timing. In response to the output from the recording signal generation means 7, the laser control means 8 controls the laser power in the optical head, and records additional information on the disk by temperature control.

  The delay amount calculation means 5 may be configured by a circuit, or may be realized by software by firmware. The delay amount calculation means 5 may arrange timing correction before the synchronization detector 43. However, in that case, it is necessary to have a FIFO (First In First Out) memory for holding the binarized data, resulting in an increase in circuit scale.

  Further, if the conversion function from the oscillation frequency to the correction value is a linear function with respect to the frequency, the asynchronous fixed delay in the recording system circuit path from the reproduction can be corrected, but a higher order function may be used.

  The spindle rotation control does not need to be CAV, and may be CLV. When additional writing is performed by CLV control, the reproduction PLL can be synchronized before the spindle speed reaches a constant speed after seeking. Therefore, it becomes possible to start additional recording before the rotation of the optical disk medium reaches a constant speed rotation, and the recording throughput is improved.

  Although the case where the reproduction signal of the optical disk is used as the input signal of the present invention has been described so far, a read signal from an information recording medium such as a magnetic disk or a magnetic tape may be used.

  FIG. 2 is a block diagram showing a configuration example when the reproduction signal processing circuit of the information recording / reproducing apparatus according to the first embodiment of the present invention is digitized. Digital signal processing such as PRML (Partial Response Maximum Likelihood) is indispensable for reproducing information recorded at high density. Therefore, digitizing the reproduction signal processing circuit including the PLL is effective from the viewpoint of miniaturization and improvement in yield.

  The reproduction signal processing circuit according to the present embodiment includes a PLL 41, a PRML circuit 421, and a synchronization detector 43. The PLL 41 includes an A / D (Analog / Digital) converter 411, a digital filter circuit 412, a phase comparator (PC) 413, a loop filter 414, and an NCO (Numerically Controlled Oscillator, numerically controlled oscillator) 415. It comprises. The phase comparator 413 includes a resampler 4131 and a decoder 4132.

  The A / D converter 411 is connected to the digital filter circuit 412. On the other hand, the digital filter circuit 412 is connected to the resampler 4131. On the other hand, the resampler 4131 is connected to the decoder 4132 and the PRML circuit 421. The decoder 4132 is connected to the loop filter 414. On the other hand, the loop filter 414 is connected to the NCO 415. On the other hand, the NCO 415 is connected to the resampler 4132, the PLML circuit 421, and the synchronization detector 43. On the other hand, the PRML circuit 421 is connected to the synchronization detector 43.

  The reproduction signal is converted into digital information having a bit width of about 4 to 8 bits by the A / D converter 411. Sampling clock SCLK is a system clock asynchronous to the channel clock.

  The signal output from the A / D converter 411 includes DC fluctuation, amplitude fluctuation, nonlinear distortion, and the like. In order to remove these, filter circuits 412 such as HPF (High Pass Filter), AGC (Auto Gain Control), and asymmetry correction are required. Since the filter circuit 412 is asynchronous to the channel clock, the asynchronous fixed delay including the A / D converter 411 is concentrated on this circuit portion.

  The phase of the output signal from the filter 412 is corrected by the resampler 4131. Note that both the resampler 4131 and the decoder 4132 are included in the phase comparator 413.

  The phase error output from the phase comparator 413 is integrated by the loop filter 414 to generate frequency information. Although this frequency information depends on the lock range, for example, the bus width is about 16 to 20 bits.

  This frequency information is integrated by the NCO 415 and fed back as a resample phase signal φ for the resampler 4131. That is, a PLL loop is configured including the resampler.

  As a result, the same information as that obtained by punching out at the timing synchronized with the reproduction channel clock is obtained as the resample output. This information is input to PRML 421 to generate binarized data by maximum likelihood detection.

  A configuration in which a D / A converter is provided after the LPF 414, a VCO (Voltage Controlled Oscillator) is provided instead of the NCO 415, and the A / D 411 is operated by the VCO output clock is also possible. In that case, however, the PLL loop delay increases and a D / A converter is required. Considering these, the configuration of FIG. 2 is the best.

  The binarization circuit does not need to be the PRML 421, and other configurations may of course be used.

  In the present invention, PLL oscillation frequency information is required. In the case of an analog PLL, processing such as measurement of the PLL clock cycle or A / D conversion of the VCO input value is necessary, but this is not necessary in the digital circuit shown in FIG.

(Second Embodiment)
FIG. 7 is a block diagram showing a configuration example of an optical disc information recording / reproducing device for explaining the operation of the timing signal generating device according to the second embodiment of the present invention. This optical disk information recording / reproducing apparatus includes an optical head 2, an amplifier 3, a PLL 41, a correction amount calculating means 5, a timing correcting means 6, a multiplying PLL 9, a recording signal generating means 7, and a laser control means 8. It has.

  The optical head 2 is connected to the amplifier 3. On the other hand, the amplifier 3 is connected to the PLL 41. On the other hand, the PLL 41 is connected to the correction amount calculation means 5 and the timing correction means 6. On the other hand, the correction amount calculation means 5 is connected to the timing correction means 6. On the other hand, the timing correction means 6 is connected to the multiplication PLL 9. On the other hand, the multiplication PLL 9 is connected to the recording signal generating means 7. On the other hand, the recording signal generating means 7 is connected to the laser control means 8. On the other hand, the laser control means 8 is connected to the optical head 2.

  The spindle motor controls the rotation of the optical disk medium 1. In the head 2, a servo circuit (not shown) accurately controls the distance between the disk surface and the objective lens and the radial positional relationship between the disk guide groove and the focused spot.

  The focused spot is irradiated to the guide groove on the disk. The optical disk guide groove is wobbled in the radial direction at a constant frequency that cannot be followed by servo control. This wobbling state can be detected by a difference signal (wobble signal) of the photodetector output obtained by dividing the reflected light in the radial direction.

  Based on the wobble signal amplified by the amplifier 3, the PLL 41 generates a wobble synchronous clock signal. The timing corrector 6 receives the wobble synchronization clock signal and corrects the clock phase. On the other hand, the correction amount calculation means 5 inputs the oscillation frequency value output from the PLL 41 and outputs a correction value. The timing output from the timing corrector 6 is controlled by this correction value.

  The multiplication PLL 9 receives the output of the timing corrector 6 and generates a recording clock. In synchronization with the recording clock, the recording signal generator 7 converts user data into a laser power control signal. The laser control circuit 8 inputs this signal and modulates the laser power of the optical head 2 to record information. Thereby, when information is continuously recorded continuously by CAV control, it is possible to prevent the information from being gradually shifted and recorded as the linear velocity changes.

  The delay amount calculation means 5 may be configured by a circuit or may be realized by software using firmware.

  Further, if the conversion function from the oscillation frequency to the correction value is a linear function with respect to the frequency, the asynchronous fixed delay in the recording system circuit path from the reproduction can be corrected, but a higher order function may be used.

  The timing corrector 6 may be arranged at the subsequent stage of the multiplication PLL 9, but there is an advantage that it is easier to make a digital circuit by controlling at a low frequency before the multiplication.

  FIG. 8 is a block diagram showing a configuration example when the PLL circuit 41 of the timing generation device according to the second embodiment of the present invention is digitized.

  The PLL circuit 41 according to the present embodiment includes an A / D converter 411, a digital filter circuit 412, a phase comparator 413, a loop filter 414, and an NCO 415. The phase comparator 413 includes a resampler 4131 and a decoder 4132.

  The A / D converter 411 is connected to the digital filter circuit 412. On the other hand, the digital filter circuit 412 is connected to the resampler 4131. On the other hand, the resampler 4131 is connected to the decoder 4132. The decoder 4132 is connected to the loop filter 414. On the other hand, the loop filter 414 is connected to the NCO 415. On the other hand, the NCO 415 is connected to the resampler 4132.

  The A / D converter 411 receives a reproduction signal, converts it into digital information having a bit width of about 4 to 8 bits, and outputs the digital information. The sampling clock SCLK supplied to the A / D converter 411 and the digital filter circuit 412 is a system clock asynchronous to the channel clock.

  The output signal from the A / D converter 411 includes DC fluctuation, amplitude fluctuation, and the like. In order to remove these, a filter circuit 412 such as a BPF (Band Pass Filter) or AGC is required. Since the filter circuit 412 is asynchronous to the channel clock, asynchronous fixed delays including the A / D converter 411 are concentrated on this circuit portion.

  The resampler 4131 receives the output signal from the filter 412, corrects the phase thereof, and outputs it. The phase comparator 413 includes a resampler 4131 and a decoder 4132. The loop filter 414 integrates the phase error that is the output signal from the phase comparator 413 to generate frequency information. Although this frequency information depends on the lock range, for example, a bus width of about 16 to 20 bits may be used.

  The NCO 415 integrates this frequency information and feeds it back to the resampler 4131 as a resample phase signal φ. That is, a PLL loop including the resampler 4131 is configured.

  In addition, for example, a configuration in which a D / A converter is provided after the LPF 414, a VCO is provided instead of the NCO 415, and the A / D converter 411 operates with a VCO output clock is also conceivable. However, in this case, the PLL loop delay increases and a D / A converter is required. Therefore, considering these, the configuration of FIG. 8 is the best.

  In the case of an analog PLL, processing such as measurement of the PLL clock cycle or A / D conversion of the VCO input value is necessary, but this is not necessary in the digital circuit shown in FIG.

  FIG. 9 is a block diagram illustrating a configuration example of a timing corrector in the timing signal generation device according to the second embodiment of the present invention. The timing corrector includes a phase comparator 61, an adder 62, a loop filter 63, and an NCO 64.

  The phase comparator 61, the adder 62, the loop filter 63, and the NCO 64 are sequentially connected in this order. Further, the NCO 64 is also connected to the phase comparator 61 on the other side, and forms a loop circuit as a whole.

  Delay correction is performed during recording. Therefore, when there is a sudden clock phase fluctuation, there is a possibility that the reproduction PLL does not follow in time when the recorded disk is reproduced, and synchronization is lost. Therefore, it is necessary to change the phase slowly so that the reproduction PLL can follow. For this request, it is effective to form a loop with a DLL (Delay Locked Loop) or PLL.

  The phase comparator 61 receives the wobble synchronization clock and the NCO 64 output clock, calculates the phase error, and outputs it.

  The adder 62 adds a correction value to the phase error and offsets the phase. The NCO 64 is slowly controlled through the loop filter 63 so that the result becomes zero.

  In the case of a DVD-RAM, address information is arranged as a pre-pit (CAPA: Complementary Allocated Pit Address) at the head of the sector. In order to read the information of the CAPA part, first, the appearance position of the next CAPA part is predicted from the reproduction timing of the previous CAPA. Then, an operation such as changing the cutoff frequency of the HPF at the head of the CAPA unit or performing high-speed pull-in of the PLL is required. Therefore, a control gate signal for reproduction signal processing is required.

  In DVD-RAM, a wobble signal having the same frequency as DVD-R / RW is obtained. Therefore, a recording clock is generated from this, the recording clock is counted from the previous CAPA reproduction timing, and a control gate for reproducing the next CAPA section is generated.

  When this disc is played back by CAV control, the delay amount based on the channel clock period changes depending on the channel clock frequency due to the asynchronous internal delay of the playback system. Therefore, the predicted gate position is also shifted.

(Third embodiment)
FIG. 10 is a block diagram showing a configuration example of an optical disc information recording / reproducing apparatus for explaining the operation of the timing signal generating apparatus according to the third embodiment of the present invention. However, here, the purpose is mainly to generate a prediction gate of a DVD-RAM.

  The optical disk information recording / reproducing apparatus of this embodiment includes an optical head 2, an amplifier 3, a synchronization detection unit 4, a correction amount calculation unit 5, and a timing correction unit 6. The synchronization detector 4 includes a PLL 41, binarization means 42, and a synchronization detector 43.

  The optical head 2 is connected to the amplifier 3. On the other hand, the amplifier 3 is connected to the synchronization detection means 4. In the synchronization detection means 4, the binarization means 42 is connected to the synchronization detector 43. On the other hand, the synchronization detector 43 is connected to the timing correction means 6. The PLL 41 of the synchronization detection unit 4 is connected to the correction amount calculation unit 5. On the other hand, the correction amount calculation means 5 is connected to the timing correction means 6. On the other hand, the timing correction means 6 is connected to the synchronization detection means 4.

  The spindle motor controls the rotation of the optical disk medium 1. In the head 2, a servo circuit (not shown) accurately controls the distance between the disk surface and the objective lens and the radial positional relationship between the disk guide groove and the focused spot.

  The focused spot is applied to the information mark recorded on the disc. Reflected light from the reflecting surface of the optical disk changes in reflectivity or polarization depending on the presence or absence of an information mark, and is converted into an electric signal by a photodetector (not shown) to obtain a reproduction signal.

  In the reproduction signal, the presence / absence of a recording mark is obtained as amplitude information. Since the reproduction signal is weak, it is amplified by the RF amplifier 3 and input to the synchronization detection means 4.

  The PLL 41 in the synchronization detection means 4 generates a recovered clock signal synchronized with the channel frequency. Further, the binarization circuit 42 generates binarized data synchronized with the reproduction clock signal.

  After the binary data is demodulated, the synchronization detector 43 detects the address information embedded in the data and generates a subsequent sector head timing signal. The timing of this timing signal is corrected by the timing correction circuit 6. As the correction amount, a value calculated by the delay amount calculating means 5 by reading the oscillation frequency value of the PLL 41 is used.

  The corrected timing signal is fed back to the synchronization detection means 4 to perform control such as temporarily increasing the loop gain of the PLL 41 or HPF (not shown).

  The delay amount calculation means 5 may be configured by a circuit or may be realized by software using firmware.

  Further, if the conversion function from the oscillation frequency to the correction value is a linear function with respect to the frequency, the asynchronous fixed delay in the reproduction circuit delay can be corrected, but a higher-order function may be used.

  The spindle rotation control does not need to be CAV, and may be CLV. When additional writing is performed by CLV control, the reproduction PLL can usually be synchronized after seek and before the spindle speed reaches a constant speed. Therefore, address information can be acquired before rotating at a constant speed, and throughput during reproduction or recording is improved.

  FIG. 3 is a state transition diagram for explaining the operation of the timing correction means 6 of FIG. 1 in the timing generator according to the first embodiment of the present invention. FIG. 4 is a time chart for explaining the operation of the timing correction means 6 of FIG. 1 in the timing generation apparatus according to the first embodiment of the present invention.

  The timing correction means 6 generates a recording gate signal by delaying the synchronization timing signal d generated by the synchronization detector 43 by the correction value dly.

  In order to realize the timing correction means 6, a sequencer having four states is prepared. Here, these four states are referred to as S0, S1, S2, and S3, respectively.

  The initial state in this sequencer is S0. In the initial state S0, the state does not change during the period of the synchronization timing signal d = “0”. When the synchronization timing signal d = “1”, the state of the sequencer changes to S1.

  When entering the state S1, the counter operates and the state S1 is held until the count value matches dly. If the count value matches dly, the state moves to S2.

  In the state S2, the state does not change during the synchronization timing signal d = “1”. In the state S2, the counter is cleared to zero. When the synchronization timing signal d = "0" in the state S2, the state shifts to the state S3.

  When entering the state S3, the counter starts to operate. The state S3 is maintained until the count value matches dly, and when the count value matches, the state shifts to the state S0 and returns to the initial state. The counter is also initialized.

  In this way, the sequencer state transitions from S0 → S1 → S2 → S3 → S0. Here, when the states S2 and S3 are decoded, a desired delayed gate timing signal can be generated. The state sequencer is 2 bits wide and the counter depends on the internal delay amount, but it can be realized with a compact circuit of about several bits wide. The sequencer and counter are operated by a recording clock.

  FIG. 5 is a time chart for explaining the operation of the phase comparator 413 in FIG. Here, an output when a signal having a continuous 2T mark space is input to the phase comparator 413 is shown.

  The phase comparator 413 corrects the sign of the amplitude value in the vicinity of the edge based on the sampled data string, and outputs it. Since the phase difference returns to + π when it reaches −π, the detection range is in the range of ± π.

  In this phase comparator 413, since the output amplitude changes depending on the input amplitude, the loop characteristics may change due to amplitude fluctuation when a PLL loop is formed. In order to prevent this, an AGC may be arranged before the phase comparator 413.

  FIG. 6 is a timing chart for explaining the operation of the resampler 4131 in FIG. Here, the input signal is a signal having a continuous 2T mark space, but is sampled at a fixed frequency SCLK that is slightly higher than the channel clock.

  At this point, of course, the input signal is not synchronized with the channel signal. However, when the timing is controlled based on the phase error from the continuous sample signal sequence and the resample value is generated, an output as if the PLL control is performed by the analog VCO is obtained.

  The resample phase φ is a sawtooth waveform. The enable signal once becomes zero when the change in the resample phase φ becomes discontinuous. The recovered clock signal is generated by gating SCLC with an enable signal. Resampling is interpolated. The interpolation function may be a high-order function, but usually a linear function is not a problem.

  The first effect of the present invention is that the occurrence of gaps and overlaps in the linking portion can be minimized in the entire area even when CAV spindle control and additional writing with a constant linear density are performed. This is because the additional recording start timing is controlled by the timing correction amount calculated from the oscillation frequency value of the PLL.

  The second effect of the present invention is that it is possible to suppress a decrease in throughput of the entire system because an operation such as seeking to another area is unnecessary for measuring the correction amount.

  As described above, the present invention is suitable for information recording / reproduction of an optical disc, particularly for CAV recording / reproduction.

FIG. 1 is a block diagram showing a configuration example of an optical disc information recording / reproducing device for explaining the operation of the timing signal generating device according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration example when the reproduction signal processing circuit of the information recording / reproducing apparatus according to the first embodiment of the present invention is digitized. FIG. 3 is a state transition diagram for explaining the operation of the timing correction means in the timing generation device according to the first embodiment of the present invention. FIG. 4 is a time chart for explaining the operation of the timing correction means in the timing generation device according to the first embodiment of the present invention. FIG. 5 is a time chart for explaining the operation of the phase comparator. FIG. 6 is a timing chart for explaining the operation of the resampler. FIG. 7 is a block diagram showing a configuration example of an optical disc information recording / reproducing device for explaining the operation of the timing signal generating device according to the second embodiment of the present invention. FIG. 8 is a block diagram showing a configuration example when the PLL circuit of the timing generator according to the second embodiment of the present invention is digitized. FIG. 9 is a block diagram illustrating a configuration example of a timing corrector in the timing signal generation device according to the second embodiment of the present invention. FIG. 10 is a block diagram showing a configuration example of an optical disc information recording / reproducing apparatus for explaining the operation of the timing signal generating apparatus according to the third embodiment of the present invention. FIG. 11 is a diagram for explaining a case where a gap is generated at the linking position during additional recording on the optical disc. FIG. 12 is a diagram for explaining a case where overlap occurs at the linking position during additional recording on the optical disc. FIG. 13 is a graph showing changes in the internal delay amount depending on the reproduction radius during CAV reproduction. FIG. 14 is a graph showing changes in the correction delay amount depending on the recording radius. FIG. 15 is a graph for explaining the case where the additional recording start timing signal does not depend on the radius or the channel frequency. FIG. 16 is a block diagram for explaining the configuration of an optical disk information recording / reproducing apparatus according to the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 Optical disk medium 2,102 Optical head 3 Amplifier 4 Synchronization detection means 41 PLL
411 A / D converter 412 Digital filter circuit 413, 61 Phase comparator 4131 Resampler 4132 Decoder 414, 63 Loop filter 415, 64 Numerically controlled oscillator (NCO)
42 Binarizing means 421 PRML circuit 43, 104 Synchronization detector 5 Correction amount calculating means 6, 105 Timing correcting means 62 Adder 7, 106 Recording signal generating means 8, 107 Laser control means 9 Multiplication PLL
72 Adder 103 Reproduction signal processing circuit

Claims (14)

Synchronization detection means for inputting an arbitrary input signal having a channel frequency from an optical disc , and generating and outputting a predetermined frequency value proportional to the channel frequency and a synchronization timing signal of the input signal;
A correction amount calculating means for calculating and outputting a delay correction amount based on the frequency value;
Timing correction means for generating and outputting a correction timing signal based on the synchronization timing signal and the delay correction amount;
The delay correction amount corrects a variable delay amount depending on a reading position on the optical disc and a fixed delay amount derived from a circuit system,
A timing signal generation device that generates the correction timing signal so that a phase relationship between the input signal and the correction timing signal is constant even when the channel frequency changes. The timing signal generator according to claim 1,
The synchronization detection means includes
An A / D converter for digitizing and outputting the input signal asynchronously to the channel frequency;
A digital filter circuit unit that receives the output of the A / D converter and corrects and outputs the fluctuation of the input signal;
A digital PLL (Phase Locked Loop) circuit unit that outputs a digital PLL oscillation frequency value based on the output of the digital filter circuit unit;
A timing signal generation device that uses the digital PLL oscillation frequency value as the frequency value. The timing signal generator according to claim 1,
Using a read signal from the optical disc as the input signal,
The synchronization detection means includes
A PLL circuit unit that generates and outputs a channel clock signal synchronized with the input signal and the channel frequency;
Binarization means for detecting and outputting the input signal as a binary data signal in synchronization with the channel clock signal;
Synchronization signal generating means for generating and outputting the synchronization timing signal based on the binary data signal;
A timing signal generation device that uses the correction timing signal as a write-once recording start timing signal on the optical disc. The timing signal generation device according to claim 3,
The PLL circuit section is
An A / D converter for digitizing and outputting the input signal asynchronously with the channel clock signal;
A digital filter that receives the output signal of the A / D converter and corrects the fluctuation of the input signal, and outputs the corrected signal;
A timing signal generation device comprising: a digital PLL circuit unit that receives the digital filter output as an input and outputs the frequency value. The timing signal generator according to claim 1,
Using the wobble signal from the optical disc as the input signal,
The synchronization detection means includes
A PLL circuit unit that generates and outputs a wobble clock signal synchronized with the input signal and the wobble frequency;
Using the wobble clock signal as the synchronization timing signal,
A multiplier PLL circuit unit for multiplying and outputting the correction timing signal;
A timing signal generation device that uses an output signal of the multiplication PLL circuit section as a recording clock signal in the optical disc. The timing signal generation device according to claim 5,
The timing correction means includes
PLL
A timing signal generating device comprising: The timing signal generation device according to claim 5,
The timing correction means includes
DLL (Delay Locked Loop)
A timing signal generating device comprising: The timing signal generator according to claim 1,
Using a read signal from the optical disc as the input signal,
The synchronization detection means includes
A PLL circuit unit that generates and outputs a channel clock signal synchronized with the input signal and the channel frequency;
Binarization means for detecting and outputting the input signal as a binary data signal in synchronization with the channel clock signal;
Synchronization signal generating means for generating and outputting the synchronization timing signal based on the binary data signal;
Using the correction timing signal as the next sector head prediction timing signal in the optical disc,
A timing signal generation device that supplies the correction timing signal to control the state of the synchronization detection means. (A) Synchronization in which an arbitrary input signal having a channel frequency is input from the optical disc , and a predetermined frequency value proportional to the channel frequency and a synchronization timing signal of the input signal are generated and output in the synchronization detection means A detection step;
(B) a correction amount calculating step for calculating and outputting a delay correction amount based on the frequency value in the correction amount calculating means;
(C) the timing correction means comprises a timing correction step of generating and outputting a correction timing signal based on the synchronization timing signal and the delay correction amount;
The delay correction amount corrects a variable delay amount depending on a position where the arbitrary input signal is read on the optical disc and a fixed delay amount derived from a circuit system,
A timing signal generation method for generating the correction timing signal so that a phase relationship between the input signal and the correction timing signal is constant even when the channel frequency changes. The timing signal generation method according to claim 9,
The synchronization detection step (a)
(A-1) In the A / D converter, the step of digitizing and outputting the input signal asynchronously to the channel frequency;
(A-2) In the digital filter circuit unit, receiving the output of the A / D converter, correcting the variation of the input signal, and outputting,
(A-3) In a digital PLL (Phase Locked Loop) circuit unit, outputting a digital PLL oscillation frequency value based on the output of the digital filter circuit unit,
A timing signal generation method using the digital PLL oscillation frequency value as the frequency value. The timing signal generation method according to claim 9,
Using a read signal from the optical disc as the input signal,
The synchronization detection step (a)
(A-4) In the PLL circuit unit, generating and outputting a channel clock signal synchronized with the input signal and the channel frequency;
(A-5) In the binarization means, detecting and outputting the input signal as a binary data signal in synchronization with the channel clock signal;
(A-6) including a step of generating and outputting the synchronization timing signal based on the binary data signal in the synchronization signal generation means;
A timing signal generation method using the correction timing signal as a write-once recording start timing signal on the optical disc. The timing signal generation method according to claim 11,
The step (a-4) includes
(A-4-1) In the A / D converter, the step of digitizing and outputting the input signal asynchronously with the channel clock signal;
(A-4-2) in the digital filter, receiving the output signal of the A / D converter, correcting the fluctuation of the input signal, and outputting the corrected signal;
(A-4-3) In the digital PLL circuit unit, a step of outputting the frequency value with the digital filter output as an input. A timing signal generation method. The timing signal generation method according to claim 9,
Using the wobble signal from the optical disc as the input signal,
The synchronization detection step (a)
(A-7) The PLL circuit unit includes a step of generating and outputting a wobble clock signal synchronized with the input signal and the wobble frequency,
Using the wobble clock signal as the synchronization timing signal,
(D) In the multiplying PLL circuit unit, the method further includes the step of multiplying and outputting the correction timing signal,
A timing signal generation method using an output signal of the multiplication PLL circuit unit as a recording clock signal in the optical disc. The timing signal generation method according to claim 9,
Using a read signal from the optical disc as the input signal,
The synchronization detection step (a)
(A-8) generating and outputting a channel clock signal synchronized with the input signal and the channel frequency in the PLL circuit unit;
(A-9) in the binarization means, detecting and outputting the input signal as a binary data signal in synchronization with the channel clock signal;
(A-10) including a step of generating and outputting the synchronization timing signal based on the binary data signal in the synchronization signal generation means;
Using the correction timing signal as the next sector head prediction timing signal in the optical disc,
A timing signal generation method for supplying the correction timing signal to control the state of the synchronization detection means.

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