JPH0877715A - Demodulation device for digital recording/reproducing device - Google Patents

Abstract

PURPOSE: To provide an inexpensive and minaturizable demodulation device which facilitates the formation of an LSI. CONSTITUTION: In an exclusive OR circuit 1, an exclusive OR is obtained between a signal s1 as an address modulation signal and a frequency divided signal s2 outputted from PLL 2 and a phase difference signal s3 is produced, in which the frequency fluctuation of the signal s1 against the frequency divided signal s2 appears as a duty ratio change. The phase difference signal s3 is inputted to a '1' level counter 3 and a '0' level counter 4 and the high level and low level periods of the phase difference signal s3 are counted. The counted values are compared by a digital comparator 5 and a binarized signal s6 based on the comparison result thereof is outputted. Thus, the entire demodulation device is composed of digital circuit elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a mini disc (MD;
In a MD device or the like that performs a recording / reproducing operation with respect to a recording medium such as a Mini Disk) on which compressed information is recorded, ADIP
The present invention relates to an ADIP demodulation device that demodulates an (Address in Pregroove) signal.

[0002]

2. Description of the Related Art As shown in FIG. 7, a magneto-optical disk capable of recording and reproducing data such as an MD is used as a guide groove 20 called a pre-groove in a step of injection molding a disk substrate 20a.
b is formed. The guide groove 20b has a light spot 20c.
Tracking control and speed control of a spindle motor that rotates a magneto-optical disk. The guide groove 20b is slightly meandering so that a sine wave signal of about 22.0 5 kHz can be added to the tracking error signal. Further, the guide groove 20b is repeatedly given a local shape change so that the address signal indicating the recording / reproducing position on the magneto-optical disk can be superimposed on the sine wave signal.

An address signal which is modulated according to a predetermined rule in order to be superimposed on this sine wave signal is called an ADIP signal. This ADIP signal is demodulated by an ADIP demodulation device into an address signal indicating a recording / reproducing position every 13.3 ms, for example.

As shown in FIG. 5, a general ADIP demodulator has an exclusive OR circuit (Excl.
usive-OR; hereinafter abbreviated as EXOR) 21, PLL (Ph
aseLocked Loop) 22 and low pass filter (Low Pass
Filter; hereinafter referred to as LPF) 23, a comparator 24, and a bi-phase decoder 25.

Next, the connection relationship of each circuit element will be described based on various signals input and output between each circuit element. First, the ADIP signal s11 is input to the EXOR 21 and the PLL 22 in the subsequent stage receives the ADIP signal s11. The output divided signal s12 is input. The phase difference signal s13 output from the EXOR21 is from the EXOR21 to the PLL22 and L.
Each is input to the PF 23, and the comparator 24
The low frequency signal s14 output from the LPF 23 is input. Further, the PLL 22 is provided in the bi-phase decoder 25.
The VCO output signal s16 which is another signal output from the
The binarized signal s15 is also input. Bi-phase decoder 2
From 5, the desired demodulated signal s17 is output.

Next, the operation of each circuit element for generating the various signals will be described with reference to FIGS. 6 (a) to 6 (g).

First, the PLL 22 includes a digital VCO (Voltage Controlled Oscilator) (not shown), and the VCO output signal s16 (FIG. 6).
(See (f)) is the phase difference signal s input to the PLL 22.
It is output from the digital VCO so as to follow the frequency fluctuation of 13 (see FIG. 6C). Further, the VCO output signal s16 is divided into a frequency of, for example, 1/2 by a frequency divider (not shown) included in the PLL 22, as shown in FIG. 6B, and becomes a divided signal s12.

In the EXOR 21, the exclusive OR of the input ADIP signal s11 and the divided signal s12 is obtained, and the phase difference signal s13 is generated. That is, the phase difference signal s13 is AD as shown in FIGS.
Both the IP signal s11 and the divided signal s12 are 0 or 1
When it is, it becomes 0, and when either one of the ADIP signal s11 and the divided signal s12 is 0 and the other is 1, it becomes 1.

Since the LPF 23 cuts off the high frequency components of the phase difference signal s13, an analog low frequency signal s14 is generated as shown in FIG. 6 (d). Where AD
When the frequency of the IP signal s11 changes to the low frequency side with respect to the frequency of the frequency-divided signal s12, the duty of the phase difference signal s13 increases, so that the low frequency signal s14 changes to the reference voltage r.
exceeds ef. On the other hand, the frequency of the ADIP signal s11 is
When the frequency of the frequency-divided signal s12 fluctuates toward the high frequency side, the duty of the phase difference signal s13 becomes low, so that the low frequency signal s14 becomes lower than the reference voltage ref.

The comparator 24 compares the input low frequency signal s14 with the reference voltage ref, and as shown in FIG. 6 (e), when the low frequency signal s14 exceeds the reference voltage ref, it is 1 or less. 2 if 0
The binarized signal s15 is generated.

In the bi-phase decoder 25, the input VCO output signal s16 is counted from the rising edge and the falling edge of the binarized signal s15,
When the count value reaches a predetermined value, the binarized signal s1
A combination of every 5 samples of 1s or 0s is determined. When the combination of the levels of the two samples of the binarized signal s15 is (0,0) or (1,1), it is 0.
Then, the demodulated signal s17 which is bi-phase demodulated so as to be 1 in the case of (1, 0) or (0, 1) is output. 6 (e) to 6 (g) show a case where the demodulated signal s17 in which 0 is output first becomes 1 by the combination of two samples of the binarized signal s15, that is, (1, 0). There is.

[0012]

However, in the circuit configuration of the conventional ADIP demodulation device described above, since analog circuit elements such as the LPF 23 and the comparator 24 are used, the ADIP demodulation device is integrated into an LSI (Large Scale Integrat).
ed Circuit; large scale integrated circuit), analog circuit elements and digital circuit elements must be mixed. This complicates the LSI manufacturing process and increases the cost. Furthermore, when an analog circuit element is used, an external component is required, which hinders miniaturization of the LSI, and the conventional ADIP demodulation device has various problems.

The present invention has been made in order to solve the above-mentioned problems, and by configuring the ADIP demodulation device with only digital circuit elements, the LSI can be easily implemented, and as a result, the cost can be reduced and the size can be reduced. A new ADIP demodulator is provided.

[0014]

In order to solve the above-mentioned problems, a demodulating device of a digital recording / reproducing apparatus according to a first aspect of the present invention has a guide groove formed on a recording medium (for example, a mini disk). Address modulated signal (for example, ADIP signal) read by detecting the shape change
In a demodulating device of a digital recording / reproducing device that demodulates into an address signal indicating a recording / reproducing position on a recording medium,
(1) A clock signal generating means (for example, PLL) that generates a clock signal that is phase-synchronized with the input signal, and (2) generates a pulse signal in which the phase difference of the address modulation signal with respect to the clock signal appears as a change in duty. A phase difference detecting means (for example, an exclusive OR circuit) which is supplied to the clock signal generating means as the input signal, and (3) the pulse signal is inputted to detect a change in duty, and digital demodulation is performed in accordance with a predetermined rule. And a duty detecting means (for example, "1" level counter, "0" level counter and digital comparator) that outputs a binary signal according to the detection result (for example, bi-phase demodulation is performed). It is characterized by that.

In a demodulator of a digital recording / reproducing apparatus according to a second aspect of the present invention, in order to solve the above-mentioned problems, the duty detecting means according to the first aspect has a high level period and a low level period of the pulse signal. Counting means (for example, a "1" level counter and a "0" level counter) for counting the first count value and the second count value, respectively, and a first count value and a second count value.
It is characterized by including a comparing means (for example, a digital comparator) for comparing the count values.

[0016]

According to the structure of claim 1, the duty change of the pulse signal output from the phase difference detecting means indicates whether the phase of the address modulation signal is ahead of or behind the phase of the clock signal. The phase difference corresponds to the frequency variation of whether the frequency of the address modulation signal is changing to the high frequency side or the low frequency side with respect to the frequency of the clock signal. The method of demodulating the address signal by extracting the information of the frequency fluctuation as a binary signal and subjecting the binary signal to digital demodulation according to a predetermined rule is the same as the conventional method.

On the other hand, the fact that the duty detecting means detects the duty change of the pulse signal and outputs a binary signal according to the detection result means, for example, a change in the high level period with respect to the period of the pulse signal or a low level period. Is detected and the binary signal corresponding to the detection result is output. Therefore, for example, a digital counter can be used to measure the period of the pulse signal, the high-level period, or the low-level period, and the change of the high-level period can be detected by
For example, since a digital comparator can be used, it becomes possible to configure the duty detection means entirely by digital circuits.

That is, it is possible to replace the conventional use of the analog filter and the analog comparator to extract the information of the frequency fluctuation as a binary signal with a digital circuit. Known digitalized PLLs and exclusive OR circuits can be used for the clock signal generating means and the phase difference detecting means, which are the other constituent elements. Therefore, the demodulating device of the digital recording / reproducing apparatus according to the present invention can be used. All can be configured with digital circuit elements. As a result, it is possible to provide a demodulator that is easy to integrate into an LSI and is inexpensive and can be further downsized.

According to the second aspect of the present invention, the counting means constituting the duty detecting means counts the high level period and the low level period of the pulse signal, respectively. Therefore, for example, the first digital counter and the second digital counter are provided.
Can be used as the counting means. Further, the comparison means is configured to use the first count value and the second count value.
Since the count values are compared, for example, a digital comparator can be used as the comparison means. Therefore, it is possible to achieve the same effect as the effect of the configuration of claim 1.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following will describe one embodiment of the present invention with reference to FIGS.

As shown in FIG. 1, the ADIP demodulator of this embodiment has an exclusive OR circuit (Ex
exclusive-OR; hereinafter abbreviated as EXOR) 1, PLL (Ph
aseLocked Loop) 2, "1" level counter 3,
"0" level counter 4 and digital comparator 5
And a bi-phase decoder 6, and all circuit elements are completely digitized. In addition, conventional A
By changing the LPF as an analog circuit element used in the DIP demodulator to a counter as a digital circuit element, it is possible to replace the analog comparator with a digital comparator. In addition, replacing the conventional LPF with a digital filter having equivalent characteristics makes it possible to simplify the configuration and reduce the cost by replacing the LPF with a digital counter.

The EXOR1 and PLL2 are
A "1" level counter 3, which corresponds to the phase difference detecting means and the clock signal generating means according to claim 1, respectively.
The "0" level counter 4 and the digital comparator 5 correspond to the duty detecting means according to claim 1,
Further, of these, the "1" level counter 3 and the "0" level counter 4 correspond to the counting means described in claim 2, and the digital comparator 5 claims
It corresponds to the comparison means described in.

Next, the connection relationship of each circuit element will be described based on various signals input / output between each circuit element. First, the EXOR1 has an AD as an address modulation signal.
The IP signal s1 is input, and the divided signal s2, which is one of the two signals output from the PLL2 in the subsequent stage, is input. The divided signal s2 corresponds to the clock signal described in claim 1.

The phase difference signal s3 output from EXOR1 is input to each of EXOR1 to PLL2, "1" level counter 3 and "0" level counter 4, and digital comparator 5 includes each counter 3
The count signals s4 and s5 output from 4 are input. The phase difference signal s3 corresponds to the pulse signal described in claim 1.

Further, the bi-phase decoder 6 has a P
The VCO output signal s7 that is the other signal output from LL2 is input, and the binarized signal s6 output from the digital comparator 5 is also input. A desired demodulated signal s8 is output from the bi-phase decoder 6. The binarized signal s6 corresponds to the binary signal described in claim 1, and the demodulated signal s8 corresponds to the address signal described in claim 1.

Next, the operation of each circuit element for generating the various signals will be described with reference to FIGS. 2 (a) to 2 (h), FIG. 3 and FIG.

First, the PLL 2 comprises a digital VCO (Voltage Controlled Oscilator) (not shown). The ADIP signal s1 (see FIG. 2 (a)) input to the EXOR1 includes a phase change caused by a rotation fluctuation of an optical disc such as an MD (mini disc), and as a result, a phase difference output from the EXOR1. The signal s3 (see FIG. 2C) also includes a phase change.
Therefore, the PLL 2 instantaneously follows the phase change of the phase difference signal s3 by controlling the digital VCO based on the error voltage corresponding to the phase difference between the phase difference signal s3 and the output of the digital VCO and the frequency difference. VCO
The output signal s7 (see FIG. 2 (g)) is generated.

Further, the VCO output signal s7 is divided into a frequency of, for example, ½ by a frequency divider (not shown) included in the PLL 2, as shown in FIG.
Becomes

In EXOR1, the exclusive OR of the input ADIP signal s1 and the divided signal s2 is obtained, and the phase difference signal s3 is generated. That is, as shown in FIGS. 2A to 2C, the phase difference signal s3 becomes 0 when both the ADIP signal s1 and the divided signal s2 are 0, or both are 1 and the ADIP signal s1 and the divided signal are It becomes 1 when one of s2 is 0 and the other is 1.

Further, the duty of the phase difference signal s3 becomes high when the frequency of the ADIP signal s1 fluctuates toward the low frequency side with respect to the frequency of the frequency-divided signal s2.
When the frequency of 1 fluctuates toward the high frequency side with respect to the frequency of the divided signal s2, the duty becomes low. That is, the phase difference signal s3 includes the information indicating the frequency fluctuation of the ADIP signal s1, that is, the address information recorded by the shape change of the guide groove formed on the optical disc, as the duty change.

Further, in the "1" level counter 3, FIG.
As shown in (c) and (d), the input phase difference signal s for the cycle cut out at the rising edge of the phase difference signal s3.
The period in which 3 becomes the level of 1 is counted, and in the "0" level counter 4, the phase difference signal s3 becomes the level of 0 in the same cycle as described above, as shown in FIGS. The period is counted. In each counter 3 and 4,
The number of pulses of a stable clock signal with a period divided by the master clock is counted. Note that FIG. 2 (d)
Since the count value shown in (e) is latched, it corresponds to the phase difference signal s3 with a delay of one cycle.

The digital comparator 5 compares the magnitudes of the two input count results. Then, as shown in FIGS. 2D to 2F, when the count value of the "1" level counter 3 is larger than the count value of the "0" level counter 4, it becomes 1 and when it is smaller, it becomes 0. The binarized signal s6 is generated. When the count value of the "1" level counter 3 and the count value of the "0" level counter 4 are equal, the current level of the binarized signal s6 is held.

In the bi-phase decoder 6, the input VCO output signal s7 is counted from the rising edge and the falling edge of the input binarized signal s6. For example, when the count value counted from the rising edge of the binarized signal s6 reaches a predetermined value (for example, 7 falling edges of the VCO output signal s7), the value of the binarized signal s6 (see FIG. In f), 1) is latched, and when the count value counted from the next falling edge of the binarized signal s6 reaches the predetermined value again, the value of the binarized signal s6 at that time (FIG. 2). In (f), the combination of 0) and the previously latched value, that is, 1, is determined. In short, the combination of every two samples in the binarized signal s6 is determined.

When the combination of the levels of the two samples of the binarized signal s6 is (0,0) or (1,1), it becomes 0, and when the combination is (1,0) or (0,1). 1
The demodulated signal s8 that is bi-phase demodulated so that 2F to 2H show a case where the demodulated signal s8 in which 0 is output first becomes 1 by the combination of 2 samples (1, 0) of the binarized signal s6.

In this way, AD as an address modulation signal
The IP signal s1 is demodulated into a demodulation signal s8 as an address signal indicating the recording / reproducing position on the MD.

In the above embodiment, the binarized signal s6
Is 1 when the count value of the "1" level counter 3 is larger than the count value of the "0" level counter 4, and is 0 when the count value is smaller. In other words, the frequency of the ADIP signal s1 is , The case where the frequency of the frequency-divided signal s2 fluctuates to the low frequency side is "1", and the fluctuation to the high frequency side is "0".
It may be configured so that it changes to "0" when it fluctuates to the low frequency side, and "1" when it fluctuates to the high frequency side.

Even in this case, the bi-phase decoder 6 can properly output the demodulated signal s8, the reason for which will be described in detail below with reference to FIGS. 3 and 4.

First, as shown in FIG. 3A, the binarized signal s for one sector output from the digital comparator 5
Reference numeral 6 is composed of a leading synchronization pattern and a biphase-modulated address signal pattern for the sector. If the width of the shortest period pulse is 1T, 1T, 2
It is composed of three types of pulse widths of T and 3T. More specifically, the synchronization pattern has a pulse width of 1T and 3T, while the address signal pattern has a pulse width of 1T and 2T.

The bi-phase decoder 6 has 1T and 2
The bi-phase demodulation processing is performed only on the address signal pattern configured with the pulse width of T. At this time, the bi-phase decoder 6 sets the level of the binarized signal s6 to 1
Sampling is performed for each pulse width of T, and the combination of the values of the two samples is determined. The sampling timing at this time is given by the time when the count value of the VCO output signal s7 reaches a predetermined value (the predetermined value is 2 as described above with reference to FIGS. 2F and 2G). From the edge of the binarized signal s6, T / 2, 3T /
It is a value corresponding to time such as 2, 5T / 2). FIG. 3B shows a comparison result for each two samples by the bi-phase decoder 6.

Here, the binarized signal s6 shown in FIG.
As shown in FIG. 4A, when the polarity is inverted, for example, the combination of two samples (1, 1) of the binarized signal s6 becomes (0, 0), and the two samples (0, 1) The combination is (1, 0), but as is clear from comparing FIG. 3 (b) and FIG. 4 (b), the comparison result does not change in both cases, and the same demodulated signal s 8 is obtained. Will be done.

A demodulation device was manufactured based on the configuration of FIG.
When actually evaluated, the frequency fluctuation of the ADIP signal superimposed on the 22.05 kHz sine wave signal is ± 1 kHz.
It was possible to detect in the range of z, and it was possible to confirm performance equal to or higher than that of the configuration using the conventional analog filter and analog comparator. And that the circuit elements (“1” level counter 3, “0” level counter 4 and digital comparator 5) digitized in the present invention do not affect the PLL 2,
Further, the binarized signal s6 output from the digital comparator 5 has sufficient signal quality such that the biphase decoder 6 can determine "0" or "1" even if its edge is slightly deviated. However, this is one of the reasons why such excellent performance was obtained.

[0042]

As described above, the demodulator of the digital recording / reproducing apparatus according to the invention has the clock signal generating means for generating the clock signal phase-synchronized with the input signal, and the address modulation signal for the clock signal. Phase difference detecting means for generating a pulse signal whose phase difference appears as a change in duty and supplying it as the input signal to the clock signal generating means, and detecting the change in duty by inputting the pulse signal, according to a predetermined rule. The duty detection means outputs a binary signal that is digitally demodulated according to the detection result.

Therefore, the digital circuit element is suitable for the operation of detecting the duty change of the pulse signal and outputting the binary signal according to the detection result. Therefore, in addition to the clock signal generating means and the phase difference detecting means which have conventionally used the digital circuit element, the duty detecting means can be configured by the digital circuit element. As a result, the whole demodulator can be easily integrated into an LSI. It is possible to provide an inexpensive demodulator that can be further downsized.

In the demodulator of the digital recording / reproducing apparatus according to the second aspect of the present invention, as described above, the duty detecting means counts the high level period and the low level period of the pulse signal, and the first count value. And a counting means for outputting the second count value and a comparing means for comparing the first count value and the second count value.

Therefore, since the counting means can be composed of the first digital counter and the second digital counter and the comparing means can be composed of the digital comparator, the same effect as that of the structure of claim 1 can be obtained. Produce an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a demodulation device according to the present invention.

FIG. 2 is a timing chart showing the operation of the demodulator according to the waveform of the signal input / output between the circuit elements of the demodulator of FIG.

3 (a) and 3 (b) are timing charts showing demodulation processing for one sector by the bi-phase decoder of FIG.

4A and 4B are timing charts showing demodulation processing for one sector by the bi-phase decoder of FIG. 1 when the polarity of the binarized signal shown in FIG. 3A is inverted. is there.

FIG. 5 is a block diagram showing a configuration example of a conventional demodulation device.

6 is a timing chart showing the operation of the demodulator according to the waveform of the signal input / output between the circuit elements of the demodulator of FIG.

FIG. 7 is a perspective view showing a guide groove formed in advance in a conventional magneto-optical disk.

[Explanation of symbols]

1 EXOR (Phase Difference Detection Means) 2 PLL (Clock Signal Generation Means) 3 “1” Level Counter (Duty Detection Means and Count Means) 4 “0” Level Counter (Duty Detection Means and Count Means) 5 Digital Comparator (Duty Detection) 20b guide groove s1 ADIP signal (address modulation signal) s2 frequency division signal (clock signal) s3 phase difference signal (pulse signal) s6 binarization signal (binary signal) s8 demodulation signal (address signal)

Claims (2)

[Claims] 1. A digital recording / reproducing apparatus for demodulating an address modulation signal read by detecting a change in shape of a guide groove formed on a recording medium into an address signal indicating a recording / reproducing position on the recording medium. In the demodulator, a clock signal generating means for generating a clock signal phase-locked with an input signal, and a pulse signal in which a phase difference of the address modulation signal with respect to the clock signal appears as a change in duty, Phase difference detection means supplied as an input signal, and inputting the pulse signal to detect a change in duty,
A demodulator of a digital recording / reproducing apparatus, comprising: a duty detecting means for outputting a binary signal which is digitally demodulated according to a predetermined rule in accordance with a detection result. 2. The duty detecting means counts a high level period and a low level period of the pulse signal, respectively, and outputs a first count value and a second count value, and a first count value and a second count value. The demodulator of the digital recording / reproducing apparatus according to claim 1, further comprising: a comparing unit that compares the count values.