JP2659586B2 - Recorded data playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a recorded data reproducing apparatus, and more particularly to an apparatus for reproducing data recorded on a recording medium on which data is recorded and reproduced by a sampled servo method.

BACKGROUND ART In recent years, read-only and write-once optical disks have been put to practical use, and rewritable optical disks are about to be put into practical use. In any of these types of optical disks, the track pitch is very narrow, about 1 to 2 μm, so that concave or convex pits or grooves are formed on the disk in advance so that the reading light follows the tracks. The tracking servo makes the beam spot follow the track by detecting the relative position of the track and the beam spot for information reading in the disk radial direction by diffraction of the light illuminated and reflected on the disc by these pits or grooves. Can be done. Further, pits are also used for information for generating a clock necessary for recording or reproducing data, information for dividing a sector, information for accessing a sector, information for dividing the inside of a sector into blocks, and the like. These various kinds of information are read by the light diffraction by the pits. The pits formed in advance on the disk and intended to obtain information by light diffraction as described above are called embossed pits.

An example of the arrangement (so-called format) of the embossed pits on the disc is shown in FIGS.

In the format shown in FIGS. 4 to 6, tracks formed virtually in a spiral on the disk have one track.
It is divided into 1376 equiangular segments per rotation. One sector is constituted by 43 consecutive segments. Therefore, one round of track (one track)
Is composed of 32 sectors.

FIG. 4 is a diagram showing a segment configuration in one sector. All segments consist of a 2-byte servo area and a 16-byte header area or data area, for a total of 18 bytes. The first segment has a 16-byte header area, and the second to 43rd segments have a 16-byte data area. Note that all bytes of the servo area, header area, and data area have one byte divided into 15 channel bits.

FIG. 5 is a diagram showing a configuration of a servo area. The servo area of one segment is composed of 2 bytes. Each byte constituting the servo area is called a first servo byte and a second servo byte, respectively. Two emboss bits are formed in the first servo byte. These are formed so as to be shifted from the virtual track center by about 1/4 track pitch in directions opposite to each other in the disk radial direction. The first wobbled pit PW1 is formed at the position of the third or fourth channel bit while switching every 16 tracks, and the second wobbled pit PW2 is formed at the position of the eighth channel bit. With these two wobbled pits, a tracking error signal can be generated once per segment by sampling. That is, when the beam spot passes through the center of the virtual track, it passes through the middle of the two wobbled pits, so that the degree of diffraction in each of the wobbled pits is equal, and the reflected light is also equal. Therefore, the tracking error signal obtained by taking the difference between the signals obtained by photoelectrically converting the reflected light amounts is zero (no error).
Becomes Further, when the beam spot is shifted from the center of the virtual track, a difference occurs in the reflected light from the two wobbled pits, so that a tracking error signal corresponding to the direction and amount of the shift is obtained. Since there are 1,376 segments during one rotation, a tracking error signal obtained by sampling in each servo byte is almost equivalent to that obtained continuously, and tracking servo can be performed.

In the second servo byte, one emboss pit is formed just on the center of the virtual track at the position of the twelfth channel bit. This is called a clock pit PC. Since there is one clock pit PC in each segment at a fixed position in each servo byte, a clock having a channel bit rate frequency is generated by synchronizing a PLL with a signal reproduced at a constant interval from this pit. can do. When recording data, modulation is performed by this clock, and when data is reproduced, demodulation is also performed by this clock.

Since a mirror surface is provided between the PW2 and the PC, a stable focus error that is not affected by the presence or absence of a pit can be generated in a sampling manner.

Also, since the interval between PW2 and PC is an interval (19 channel bits) that cannot appear in the 4/15 modulation method described later, segment synchronization can be performed by detecting this interval. is there.

FIG. 6 is a diagram showing a configuration in the header area. In the first byte, a sync mark is formed by emboss pits. The sync mark has pits formed in the second, seventh, eighth, and ninth channel bits, and is a special pattern that does not correspond to any NRZ data in a conversion table of a 4/15 modulation method described later. Therefore, by detecting this, sector synchronization can be performed. Second
The byte is formed by a sector address in one track, and the third to seventh bytes are formed by a track address in the disk by emboss pits. These are modulated according to the 4/15 modulation method described later for each byte. The 8th to 13th bytes are reserved areas for which use is not determined, and have a mirror surface without embossed pits. The 14th to 16th bytes are the laser power control area. Initially it has a mirror surface without embossed pits. When recording or erasing data on or from a disc, it is desirable to use an appropriate optical power. In this area, however, it is permitted to output test or write power from an optical pickup on a trial basis and correct the output power based on the power. Have been.

The data area has a length of 16 bytes, and has a mirror surface without emboss pits in an unrecorded state. NRZ
The data is modulated one byte at a time by the 4/15 modulation method described later and recorded in this area. In the case of a write-once image (write-once type), recording involves physical changes such as holes in the recording film. In the case of a rewritable disk utilizing the magneto-optical effect (hereinafter referred to as a magneto-optical disk), such a physical change does not accompany, but a change such that the direction of the magnetic field of the recording film is reversed.

The data area in one sector has 16 × 42 = 672 bytes, which are composed of user data, error correction codes, and the like, but details thereof will not be described here.

Next, the 4/15 modulation method will be described with reference to FIG. In the 4/15 modulation method, one byte is converted into 15 channel bits, and from these 15 locations, the original 256 NRZ data correspond one-to-one with a conversion table.
A mark is recorded at a location (two odd-numbered locations and two even-numbered locations, except for the 15th channel bit). That is, in the case of the write-once type, an operation such as making a hole in the recording film is performed, and in the case of a magneto-optical disk, the direction of magnetization of the recording film is reversed. As in the example shown in FIG. 7, marks may be adjacent to each other (channels 12, 13, and 14), but marks that are not adjacent to each other (channels 9 and 12).
During this period, there is always a space of at least two channel bits (the tenth and eleventh channel bits). However, as an exception, there is a case where the 14th channel bit of a certain byte and the 1st channel bit of the next byte serve as a mark, and only one channel bit (the 15th channel bit) is left between them. Since the channel bit does not become a mark, there is no harm at the time of demodulation.

Next, demodulation of data by the 4/15 modulation scheme will be described. FIG. 7 shows a reproduced waveform corresponding to the mark. In the case of perforated recording, the reflected light at the mark position is darker than the reflected light at the position without a mark (mirror surface), and the opposite change occurs in some non-perforated media. There is. However, the 4/15 modulation method can demodulate if there is a difference between the mark position level and the mirror level,
Therefore, the reproduced waveform in FIG. 7 does not mean that the upper part in the figure is bright, but merely indicates the voltage level at a certain point in the demodulation circuit. In the case of a magneto-optical disk, this is not the mirror level but the erase level. For demodulation, it is only necessary to be able to specify the positions of two odd-numbered marks and two even-numbered marks among the first to fourteenth channel bits of a certain byte. Therefore, for example,
By performing A / D conversion at the bit center of the 14 channel bits and comparing the obtained digital data in magnitude, the position of the mark can be specified. For example, in the example of FIG.
Of the 3,5,7,9,11,13 channel bits, the 13th channel bit has the highest level, and the ninth channel bit has the second highest level. (In this example, since there is a mark in the 14th channel bit and the 1st channel bit of the next byte, the
Although the level of the 15th channel bit may be higher than the level of the ninth channel bit, the 15th channel bit does not become a mark and thus is not subjected to magnitude comparison.
Therefore, it does not adversely affect demodulation. That is, it can be seen that among the odd numbers, the marks are present at the ninth and thirteenth channel bits. Similarly, it can be seen that among the even-numbered channel bits of the second, fourth, sixth, eighth, tenth, twelfth, and fourteenth, there is a mark in the twelfth and fourteenth channel bits. From these four marks, the original NRZ data can be demodulated by the conversion table.

In short, in the demodulation of the 4/15 modulation method, it is fundamental to compare the reproduction levels at the center of each channel bit.

FIG. 8 shows a conventional apparatus for reproducing data recorded on a disk by the sampled servo method as described above.

In FIG. 8, a so-called RF (high frequency) signal which is a read signal output from a pickup (not shown) is supplied to the waveform shaping circuit 1. The waveform shaping circuit 1 has a state transition point, that is, a rising edge or a falling edge.
It is configured to generate a pulse synchronized with the peak level point of the RF signal. The output pulse of the waveform shaping circuit 1 is supplied to a selector 6 after being sequentially delayed by delay lines 2, 3, 4, and 5. Each output of the delay lines 2, 3, and 4 is also supplied to the selector 6. Selector 6
Is configured to selectively output one of the delay lines 2 to 5 according to the switching control signal output from the switching control signal generation circuit 7. The switching control signal generating circuit 7 is configured to output a signal corresponding to a 2-bit code set by, for example, a manual switch as a switching control signal.

The output of the selector 6 is supplied to a phase locked loop (hereinafter, referred to as a PLL) 8. The PLL circuit 8 is configured to generate a pulse of a predetermined frequency having a rising or falling edge synchronized with a rising or falling edge of an output pulse of the selector 6.

The output pulse of the PLL circuit 8 is supplied to the A / D conversion circuit 9 as a reproduction clock. In the A / D conversion circuit 9, the instantaneous level of the RF signal is sampled at the rising edge of the reproduced clock, and digital data corresponding to the obtained sample position is generated. The output data of the A / D conversion circuit 9 is supplied to a 4/15 demodulation circuit 10 and subjected to demodulation processing.

In the A / D conversion circuit 9 having the above configuration, if the instantaneous level of the peak level point of the RF signal, that is, the point corresponding to the center of the channel bit is not sampled,
15 The demodulation circuit 10 performs erroneous demodulation. Therefore, the output from the PLL circuit 8 and the A / D conversion circuit 9
It is necessary to adjust the phase of the reproduction clock in advance so that the point of occurrence of the rising edge of the reproduction clock supplied to the RF signal coincides with the peak level point of the RF signal. This phase adjustment of the reproduction clock can be performed by switching control of the selector 6.

In other words, one of a plurality of pulses obtained by delaying the output pulse of the waveform shaping circuit 1 by different times by the delay lines 2 to 5 is selectively output from the selector 6. The delay time of the output pulse of the waveform shaping circuit 1 output from the selector 6 changes, so that the phase of the pulse supplied from the selector 6 to the PLL circuit 8 changes, and the phase of the reproduced clock output from the PLL circuit 8 changes. Adjustments are made.

However, in the conventional apparatus as described above, the minimum variable width of the delay time of the output pulse of the waveform shaping circuit 1 is:
The delay time is determined by the delay time of each of the delay lines 2 to 5, and the delay time changes stepwise. For this reason, in the conventional apparatus, there is a problem in that it is not possible to make a highly accurate adjustment of the phase of the reproduced clock, and it is not possible to improve the error rate. Further, since the delay line is an expensive component, there is a problem that the manufacturing cost is high.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a recording data reproducing apparatus capable of adjusting the phase of a reproduction clock with high accuracy and having a low manufacturing cost. And

A recording data reproducing apparatus according to the present invention includes a pre-PLL circuit that receives a read signal obtained from a recording medium and generates a free-running clock signal having a predetermined frequency based on clock information in the read signal; A phase adjustment PLL circuit that adjusts the phase of the free-running clock signal to be a clock signal for data reproduction so that a predetermined time relationship occurs between a state transition point and a peak level point of the read signal. An oscillator that oscillates at a frequency according to a control signal, and a phase difference generator that generates a phase difference signal between the output of the oscillator and the free-running clock signal. Signal generating means, and error adding means for supplying a signal obtained by adding an error signal of a predetermined level to the phase difference signal as a control signal to the oscillating means,
The output of the oscillating means is output as a clock signal for data reproduction.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3. FIG.

In FIG. 1, a waveform shaping circuit 1, an A / D conversion circuit 9 and a 4/15 demodulation circuit 10 are connected in the same manner as in the apparatus of FIG. However, in this example, the output of the waveform shaping circuit 1 is directly supplied to the PLL circuit 8. The output pulse of the PLL circuit 8 is supplied to a PLL circuit 12 as a phase adjusting means.

In the PLL circuit 12, the output pulse of the PLL circuit 8 is supplied to the phase comparison circuit 13. In the phase comparison circuit 13, the PLL
The output pulse of the circuit 8 is compared with the phase of the output pulse of the VCO (voltage controlled oscillator) 14, and a phase difference signal corresponding to the phase difference between the two signals is generated. The phase difference signal is added to the addition circuit
It is supplied to one of the 15 input terminals. The voltage input to the slider of the variable resistor 16 is applied to the other input terminal of the adder circuit 15. The resistor of the variable resistor 16 is connected between the power supply and the ground, and a voltage corresponding to the position of the slider on the resistor is led out to the slider. The voltage led to the slider of the variable resistor 16 is added by the adding circuit 15 to the phase difference signal output from the phase comparing circuit 13 as an error signal. The output of the adding circuit 15 is supplied to a control input terminal of the VCO 14 via a low-pass filter (hereinafter, referred to as LPF) 17. The output pulse of VCO14 is A
/ D conversion circuit 9 and 4/15 demodulation circuit 10.

In the PLL circuit 12 having the above configuration, the PLL circuit 8
The error signal generated by the variable resistor 16 is added to the phase difference signal corresponding to the phase difference between the output pulse of the VCO 14 and the output pulse of the VCO 14 and supplied to the control input terminal of the VCO 14 to control the oscillation frequency of the VCO 14 . For this reason, the output pulse of the VCO 14 has a phase difference corresponding to the voltage level of the error signal with respect to the output pulse of the PLL circuit 8. Since the voltage level of the error signal changes continuously by manually changing the position of the slider on the resistor of the variable resistor 16, the output pulse of the VCO 14, that is, the phase adjustment of the reproduced clock is performed with high accuracy. You can do it.
Therefore, the point of occurrence of the rising edge of the reproduced clock supplied to the A / D conversion circuit 9 can be accurately matched with the peak level point of the RF signal, and the error rate can be improved. In addition, since an expensive delay line is unnecessary, the manufacturing cost can be reduced.

FIG. 2 is a block diagram showing a disk drive that uses the storage data reproducing apparatus according to the present invention and is configured to be able to record and reproduce data with both a magneto-optical disk and a write-once disk. . In FIG. 2, reference numeral 20 denotes a pickup, which incorporates a semiconductor laser 21 as a light source and light receiving elements 22, 23 for receiving light of both channels of a differential optical system and performing photoelectric conversion. . The light receiving elements 22 and 23 are, for example, a semiconductor laser 2
The laser light emitted from 1 and reflected by the disk 25 is detected via an analyzer. When a magneto-optical disk is mounted as the disk 25, one of the light receiving elements 22 and 23 detects a positive component of the Kerr rotation angle, and the other detects a negative component of the Kerr rotation angle.

The disk 25 is rotated at a predetermined speed by a spindle motor 26 driven and controlled by a spindle servo circuit (not shown). The pickup 20 further has a built-in focus actuator and tracking actuator, and is driven by a focus servo circuit and a tracking servo circuit. With these servo circuits and the like, laser light emitted from the semiconductor laser 21 is accurately converged on the recording surface of the disk 25 to form a beam spot, and this beam spot accurately follows the track. And the like are not particularly required for the explanation, and are omitted in this drawing.

The outputs of the light receiving elements 22 and 23 are supplied to the differential amplifier 29 and the addition amplifier 30 via the head amplifiers 27 and 28, respectively.
In the differential amplifier 29, the RF signal a obtained by the magneto-optical effect is formed by subtracting one of the outputs of the light receiving elements 22 and 23 from the other. In addition, in the addition amplifier 30, the outputs of the light receiving elements 22 and 23 are added and synthesized to form an RF signal b corresponding to a hole formed by a recording signal in an emboss pit or a write-once disc.

The RF signal a is supplied to one input terminal of the changeover switch 33 after being delayed by the delay circuit 31 by a time equal to the signal delay time in the variable gain amplifier. Also, RF
The signal b is supplied to the other input terminal of the changeover switch 33 via the variable gain amplifier 34. A control circuit (not shown) or the like supplies a control input terminal of the variable gain amplifier 34 with a disk identification signal c indicating whether a magneto-optical disk or a write-once disk is mounted. The variable gain amplifier is configured to amplify the input signal with a gain according to the disc identification signal c. The amplitudes of the RF signals a and b supplied to the changeover switch 33 by the variable gain amplifier 34 become equal.

A switching command signal d output from the control circuit (not shown) or the like when the beam spot passes over the data area when the magneto-optical disk is mounted is supplied to a switching control input terminal of the switch 33. The changeover switch 33 is configured to selectively output the RF signal b when the switching instruction signal d does not exist, and selectively output the RF signal a when the switching instruction signal d exists.

The RF signal output from the changeover switch 33 is applied to the waveform shaping circuit 1 via the low-pass filter 35 and the clamp amplifier 36.
And supplied to the A / D conversion circuit 9.

In the waveform shaping circuit 1, the RF signal is supplied to a delay circuit 41 and a differentiating circuit. In the differentiating circuit 42, when an RF signal as shown in FIG. 3A is supplied, as shown in FIG. 3B, while the instantaneous level of the RF signal changes from a predetermined level to a peak level, a positive pulse Is generated, and a negative-polarity pulse is generated while the instantaneous level of the RF signal changes from the peak level to the predetermined level again.

The output of the differentiating circuit 42 is supplied to a comparator 43. The comparator 43 compares the output of the differentiating circuit 42 with the ground level, and outputs a high-level signal when the output of the differentiating circuit 42 exceeds the ground level. FIG. 3C shows the operation of the differentiating circuit 42 and the comparator 43.
As shown in the figure, a pulse which rises at the start of the change of the instantaneous level of the RF signal and falls at the timing corresponding to the peak level point P of the RF signal is generated. The output pulse of the comparator 43 is supplied to the clock input terminal of the JK flip-flop 44.

On the other hand, the signal delay time of the delay circuit 41 is set equal to the signal delay time of the differentiating circuit. The output of the delay circuit 41 is supplied to a comparator 45. The comparator 45 compares the output of the delay circuit 41 with a predetermined level, and outputs a high-level signal when the output of the delay circuit 41 exceeds a predetermined level. The output of this comparator 45 is supplied to the J and K terminals of a JK flip-flop 44 via an exclusive OR gate 46 connected to act as a buffer gate.

As a result, the Q output of the JK flip-flop 44 is inverted every time a peak level point appears in the RF signal.

The Q output of the JK flip-flop 44 is supplied to one input terminal of an exclusive OR gate 47 and a delay circuit
After being delayed by a predetermined time by 48, it is supplied to the other input terminal of the exclusive OR gate 47. Accordingly, a positive pulse having a time width equal to the signal delay time in the delay circuit 48 is output from the exclusive OR gate 47 every time the Q output of the JK flip-flop 44 is inverted, that is, each time a peak level point appears in the RF signal. Is done. This exclusive OR gate 47
Is supplied to the PLL circuit 8 as an output of the waveform shaping circuit 1.

In the PLL circuit 8, a pulse of a predetermined frequency synchronized with the edge of the output pulse of the waveform shaping circuit 1 is generated in the same manner as in the apparatus of FIG. The output pulse of the PLL circuit 8 is supplied to the PLL circuits 12 and 50. The PLL circuit 12
The configuration is the same as that in the apparatus shown in the figure. This PL
The output pulse of the L circuit 12 is supplied to the A / D converter 9 and the 4/15 demodulation circuit 10 as a reproduction clock, similarly to the apparatus of FIG.

The PLL circuit 50 has the same configuration as the PLL circuit 12. The output pulse of the PLL circuit 50 is supplied to the 4/15 modulation circuit 51. The 4/15 modulation circuit 51 is configured to modulate data supplied from an external device (not shown) or the like according to the 4/15 modulation method. The output of the 4/15 modulation circuit 51 is supplied to a drive circuit 52. The drive circuit 52 constantly outputs a constant level signal having an amplitude corresponding to the low-level laser power for reading information, and corresponds to the laser power at the time of recording according to the recording signal output from the 4/15 modulation circuit 51. A pulse signal having a constant amplitude is superimposed on a constant level signal and output. The output of the drive circuit 52 is supplied to the semiconductor laser 21 of the pickup 20 as a drive signal.

In the above configuration, the rising edge of the reproduction clock supplied to the A / D conversion circuit 9 by the PLL circuit 12 is generated regardless of whether a magneto-optical disk or a write-once disk is mounted as the disk 25. The phase of the reproduced clock can be adjusted so that the time coincides with the peak level point of the RF signal.

Further, the recording data is written to the disk by the reproduction clock. Since the written data is also read by the reproduction clock, the optical system from the recording surface of the disk to the light receiving element, head amplifier, differentiation circuit, PL
It is necessary to adjust the delay time of the L circuit, the recording system circuit, and the like, and the delay time from the irradiation of light to the formation of a data mark. The adjustment of the delay time is performed by the PLL circuit 50.

As described in detail above, in the recording data reproducing apparatus according to the present invention, a read signal obtained from a recording medium is input and a free-running clock signal having a predetermined frequency is generated based on clock information in the read signal. The phase of the PLL circuit, the phase of the free-running clock signal is adjusted so that a predetermined time relationship occurs between the state transition point of the free-running clock signal and the peak level point of the read signal, and the phase becomes the clock signal for data reproduction. An adjustment PLL circuit is provided. The phase adjustment PLL circuit includes an oscillation unit that oscillates at a frequency corresponding to the control signal,
Phase difference signal generating means for generating a phase difference signal according to the phase difference between the output of the oscillation means and the free-running clock signal;
Error adding means for supplying a signal obtained by adding an error signal of a predetermined level to the phase difference signal as a control signal to the oscillating means, and using the output of the oscillating means as a clock signal for data reproduction.

Therefore, in the recording data reproducing apparatus according to the present invention, the output phase of the oscillating means can be continuously changed according to the level of the error signal, and the phase adjustment of the data reproducing clock can be performed with high accuracy. You can do it. In addition, since an expensive delay line is unnecessary, the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG.
4 to 6 are diagrams showing an example of a recording format of a recording disk, and FIG. 7 is a diagram showing a recording state of a data area and a waveform of a read signal. FIG. 8 is a block diagram showing a conventional recording data reproducing apparatus. Explanation of Signs of Main Parts 1 ... Waveform shaping circuit 8, 12, 50 ... PLL circuit 9 A / D conversion circuit 10 4/15 demodulation circuit

Claims (1)

(57) [Claims] 1. A pre-PLL circuit for receiving a read signal obtained from a recording medium and generating a free-running clock signal having a predetermined frequency based on clock information in the read signal, and a state transition point of the free-running clock signal. A phase adjustment PLL circuit that adjusts the phase of the free-running clock signal to be a clock signal for data reproduction so that a predetermined time relationship occurs between the phase adjustment and the peak level point of the read signal. PLL circuit for oscillating means oscillating at a frequency according to the control signal, and a phase difference signal generating means for generating a phase difference signal according to the phase difference between the output of the oscillating means and the free-running clock signal, Error adding means for supplying a signal obtained by adding an error signal of a predetermined level to the phase difference signal as a control signal to the oscillating means, wherein the output of the oscillating means is a clock signal for data reproduction. A recorded data reproducing apparatus for outputting the recorded data.