JPS59111422A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain a periodic signal regenerating circuit of a CD system DAD reproducer operated stably in response to a pulse signal having irregular period. CONSTITUTION:A signal having waveform (g) as shown in Figure is obtained at an output terminal 33 and the leading is synchronized with the time of polarity inversion of an EFM (eight to fourteen modulation) signal (refer to Fig. (a)), and the leading is synchronized with the trailing of a control pulse signal (refer to Fig. (b)) outputted first after the polarity inversion of the EFM signal (a). On the other hand, when a signal as shown in Fig. (f) is applied to a D FF30, a signal (h) delaying the input signal (f) by 1/2 period is obtained at an output terminal Q of the said circuit 30. Since frquency increasing and decreasing pulse signals as shown by (g), (j) in Fig. are not generated closely with each other in the constitution above, the accurate phase locked circuit is obtained without any interference as a conventional circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a phase synchronization system suitable for use in, for example, synchronized clock reproduction of a CD (optical continuous disc) type DAD (digital audio disc) reproduction device. Regarding loop circuits.

[Technical background of the invention and its problems]

As is well known, the total phase ratio of n input pulse signals obtained from a reproduction system etc. and n control pulse signals obtained from a VCO (voltage controlled oscillator) is determined, and the phase difference signal is used to calculate the above vC.
A phase-locked loop that matches the phase of a control pulse signal with the phase of an input pulse signal by controlling the oscillation frequency of O is generally constructed as shown in FIG. That is, the phase comparator 13 compares the phases of the input pulse signal supplied to the input terminal 11 and the control pulse signal output from the VCO 12 . This phase comparator 1
3 outputs frequency increasing and decreasing pulse signals U and Dt corresponding to the phase delay n and phase advance of the control pulse signal with respect to the input pulse signal. These pulse signals U and D for increasing and decreasing the frequency are supplied to the VCO 12 via the charge pump circuit 14 and the loop filter circuit 15, and the oscillation frequency of the VCO 12 is controlled. The phase of the control pulse signal is made to match the phase of the control pulse signal. In addition,
The control pulse signal outputted from the VCO 12 is outputted via the output terminal 16f and subjected to further processing.

Here, the charge pump circuit 14 and the loop filter circuit 15 are connected to a diode D l as shown in FIG.
pD 2 , resistors R1, R2, and operational amplifier 17,
It is generally composed of a constant voltage source E1, a resistor R3, and a capacitor C1.

By the way, the conventional phase comparator 13 used in the above phase-locked loop is integrated circuit (IC) as shown in FIG. , an input terminal 19 to which a control pulse signal outputted from the VCOl 2 is supplied, and an input terminal 20 to which an input pulse signal outputted from a reproduction system (not shown) is supplied, and the above-mentioned Two output terminals 21 and 22 are provided for outputting a signal corresponding to a phase difference component between the control pulse signal and the input pulse signal.

Then, input terminal 19.20 has i 4 [&l (a)
, Assuming that the control pulse signal and the input pulse signal are supplied as shown in (b), first, if the phase of the control pulse signal is delayed by p than the phase of the input pulse signal, then the phase As shown in FIG. 4(C), the comparator main body 18 generates an L (loaf level frequency increasing pulse signal Ut-) corresponding to the phase delay n of the control pulse signal with respect to the input pulse signal, as shown in FIG. 4(C) from its output terminal 21. The oscillation frequency of the VCO 12 is controlled to be high.Furthermore, when the phase of the control pulse signal is also ahead of the phase of the input pulse signal, the phase comparator main body 18
As shown in Figure (d), an H (high) level frequency lowering pulse signal Di corresponding to the phase advance of the control pulse signal with respect to the input pulse signal is generated, and the oscillation frequency of the VCO 2 is controlled to be lowered. , where the control pulse signal and the input pulse signal are matched in phase.

However, in the conventional phase comparator 13 such as the upper B pin, when the period of the control pulse signal and the period of the input pulse signal are approximately equal, n frequency increasing and decreasing pulse signals are generated from the output terminals 21 and 22. U and D are signals corresponding to the phase difference, and are meaningful because they are used to align the phases of the phase-locked loop. However, for example, if the period of the input pulse signal is irregular compared to the period of the control pulse signal, In such a case, a pulse waver U for increasing and decreasing the frequency is generated from the output terminals 21 and 22.

There is a problem that D does not correspond to the phase difference and is meaningless since it cannot be used for phase adjustment of loose phase synchronization.

In this regard, recently, in the field of audio equipment, digital recording and reproducing methods that fully utilize PCM (Pulse Code Modulation) technology are being adopted in order to achieve high-fidelity reproduction as much as possible.

This technology is called digital audio, and the audio characteristics do not depend on the characteristics of the recording medium and are significantly superior to those using conventional analog recording and playback methods. This is because it is established in principle that it is true.

In this case, a system that uses a disk (disk) as a recording medium is called the Yamada system, and optical, electrostatic, and mechanical recording and reproducing methods have been proposed. In other words, if we take an optical type as an example, the diameter is 12 CCm'3 and the thickness is 1.2
The specified EFM (Eig
ht to Fourteen Modulation
) A disk is made of a disk entirely coated with a metal thin film that has pits (irregularities with different reflectances) corresponding to the PCM and digitized data of the audio signal to be reproduced in the form of K tone and interleaving. CLV (constant linear velocity)
The disc is rotated at a variable rotational speed of approximately 500 to 200 [:r, p, m] and reproduced in a tracking manner.

By the way, at this time, in order to convert the digitized data obtained from the optical pickup into the original audio signal, a phase-locked loop is used to convert the digitized data to the original audio signal.
It is designed to reproduce a synchronous clock signal synchronized with the . In this case, the phase comparator of the phase-locked loop compares the phase of the control pulse signal (which becomes a synchronized clock signal) output from the VCO of the phase-locked loop with the digitized data, and This is used to match the phase of the control pulse signal obtained from the digitized data with the phase of the digitized data. However, since the digitized data is EFM modulated, as is well known, the polarity reversal interval varies from a minimum of 3 pits to a maximum of 11 bits, assuming that one cycle of the control pulse signal is all 1 bit. , it has a very irregular period compared to the period of the control pulse signal, and such a phase-locked loop requires a phase comparator like the one shown in Fig. 3 above. It cannot be used.

Therefore, recently, as a phase comparator that can be used in a phase-locked loop for reproducing a synchronized clock of a CD-based DAD reproducing device,
The system shown in Figure 5 has been developed.

That is, 23 is an input terminal to which digitized data obtained from the optical pickup and subjected to 7'L and 6EFM modifications (hereinafter referred to as EFM signal) is supplied.

This input terminal 23 is a D type flip-flop (b).
It is connected to the input NaD of the circuit (hereinafter referred to as the DEF circuit) 24, and is also connected to one input end of the exclusive OR circuit (hereinafter referred to as the EXOR circuit) 25.And,
The output terminal Q of the DFF circuit 24 is connected to the other ``DFF'' circuit 2.
The output terminal Q of this DFF circuit 26 is connected to the other input terminal of the EX-OR circuit 25. Further, each of the clock input terminals C of the DFF circuits 24 and 26 are input terminals 2 to which a control pulse signal (which becomes a synchronized clock signal) outputted from a VCO (not shown) is supplied.
Connected to 7.

Here, the output terminal of the EX-OR circuit 25 is connected to the input terminal DIIC of the DFF circuit 28, and is also connected to one input terminal of the NAND circuit 29.

Further, the output terminal Q of the DFF circuit 28 is connected to the input terminal of another DFF circuit 30, and the AND circuit 3
1 is connected to one end of the input.

Furthermore, the inverted cutting edge Q of the DFF [g circuit 28 is
It is connected to the other input end of the NAND circuit 29. Further, the clock input terminal C of the DFF circuit 28 is connected to the input terminal 27 through the NOT circuit 32 in the opposite direction.
ing. Further, the DFF circuit 30 has its inverting input terminal Q connected to the other input terminal of the AND circuit 31, and its clock input terminal C connected to the input terminal 27. The respective output terminals of the NAND circuit 29 and the AND circuit 31 are connected to each other via the respective output terminals "33.34".
It is connected to a charge pump circuit, a loop filter circuit, a VCO, etc. (not shown).

In the phase comparator configured as described above, the sixth
The entire operation will be explained with reference to the timing diagrams shown in FIGS. (a) to (i). First, when the EFXA signal and control pulse signals shown in FIGS. 6(a) and 6(b) are supplied to the input terminals 23 and 27, the control EFM signal at the rising edge of the pulse signal?
The latched signal shown in the sixth factor (CJ) is output. Then, from the end Q of the DFFlFF circuit 26, the signal shown in FIG. 6(C) is delayed by one cycle of the control pulse signal ( The signal shown in dJ is outputted. Therefore, from the output terminal of the EX-OR circuit 25, the signal shown in FIG. 6(e), which is the exclusive OR of the signals shown in FIG. The signal shown is output.

That is, the signal shown in FIG. 6(e) rises 1 in synchronization with the polarity reversal of the EFM signal (see FIG. 6(a)).
The signal falls in synchronization with the polarity reversal of the signal shown in FIG. 6(d).

Further, by outputting the signal shown in FIG. 6(e) from the EX OR circuit 25, the output terminal Q of the DFF circuit 28 is
Then, the signal shown in FIG. 6(e) is converted into a control pulse signal (6th
(see figure (b)).
After the polarity of the signal shown in e) is inverted, the polarity is inverted in synchronization with the falling edge of the control pulse signal that occurs first.
The signal shown in f) is output. At this time, DFF circuit 2
From the inverted output terminal Q of 8, the signal tl- shown in FIG.
The polarity-inverted signal 4 is output, and this polarity-inverted signal and the output signal of the EX OR circuit 25 (see FIG. 6(e))
is supplied to the NAND circuit 29, and as a result, the signal shown in FIG. 6(g) is outputted to the output terminal 33. The falling edge of the signal shown in FIG. 6(g) is synchronized with the polarity reversal of the EFM signal (see FIG. 6(a)), and its rising edge occurs at the beginning of the polarity inverted wave of the EF'M signal. This is synchronized with the falling edge of the control pulse signal (see FIG. 6(b)).

On the other hand, by supplying the signal W shown in FIG. 6(f) above, the signal shown in FIG. (1)))), and the signal shown in Figure 6(f) is delayed by 1/2 period of the control pulse signal, and the polarity is inverted. The signal shown in FIG. 6(h) is output.The signal shown in FIG. 6(h) and the signal shown in FIG.
As a result, the signal shown in FIG. 6(i) is output to the output terminal 34. The rising edge of the signal shown in FIG. 6(g) is synchronized with the rising edge of the signal shown in FIG. 6(g),
After the rising edge of the signal shown in FIG. 6(g), the rising edge of the control pulse signal (see FIG. 6(b)) that is first generated, that is, the rising edge of the signal shown in FIG. The control pulse signal is delayed by a full 1/2 period after the start and is synchronized with the other point in time.

Here, we will explain the signals shown in FIG. 6 (g) that are output from the output terminals 33 and 34. That is, the signal shown in FIG. 6 (g) is based on the polarity of the EFM signal. The signals shown in FIG. It rises in synchronization with the rising edge of the signal shown in g), and thereafter rises in synchronization with the rising edge of the first control pulse signal generated.
), (Considering the difference in the pulse width of the signal shown in ri,
This difference also corrects the EFM signal and control pulse input.
It can be seen that this corresponds to the phase difference with No. Moreover, the reason why the <g signal shown in FIG. 6(g) is at L level, and then the signal shown in FIG.
This is performed only when the polarity of G1-5Ef is reversed. In other words, n is %EFr'+/L The above phase difference is generated only when the polarity of the shoulder is reversed.

For this reason, the signals shown in Figure 6(g) are used to raise and lower the frequency of the VCO.
By using it as D, the phase of the control pulse signal can be changed to an EF having a period more irregular than the period of the control pulse signal.
It is possible to synchronize with the phase of the fVI signal and perform stable synchronous clock reproduction.

However, in the phase comparator shown in FIG. 5, the frequency increasing and decreasing pulse signals 0. D are output close to each other. In other words, Figure 6(g).

Since the rises of the signals shown in (i) are at the same time, the input of the operational amplifier 17 of the loop filter circuit 15 shown in FIG. The interference signals U and D interfere with each other, resulting in a failure in which accurate phase alignment cannot be performed as a phase-locked loop.

[Purpose of the invention]

The present invention was made in consideration of the above circumstances, and is capable of stably and accurately aligning the phases of pulse signals with irregular periods with a simple configuration. It is an object of the present invention to provide an extremely good phase-locked loop circuit which is suitable for use in, for example, synchronized clock regeneration of a CD type DAD main device.

[Summary of the invention]

That is, the present invention compares the entire phase of a first pulse signal output from a voltage controlled oscillator with a second pulse signal input from the outside, and outputs the phase difference component through a charge pump circuit and a loop filter circuit. By controlling the oscillation frequency of the voltage controlled oscillator, the phase of the second pulse signal changes to the phase of the first pulse signal. In the phase-locked loop circuit, the second pulse (i) is generated in synchronization with the polarity reversal of the pulse signal (i), and its generation is stopped in synchronization with the first pulse signal. a first phase difference signal generation means for outputting a first phase difference signal, and a first phase difference signal outputted from the first phase difference signal generation means is generated in an NFC state in which generation is stopped; a second phase difference signal generation means for fully outputting a second phase difference signal whose generation is stopped in synchronization with the first pulse signal in a state in which a nucleus is generated; control means for controlling the phase difference signal so that a predetermined time interval is provided between when the first phase difference signal stops being generated and when the second phase difference signal is generated; The present invention is characterized in that the difference between the generation periods of the first and second phase difference signals is the entire phase difference output of the first and second pulse signals.

[Embodiments of the invention]

The following is a drawing of an embodiment of the fc field applied to the synchronous clock regeneration of an all-CD type DAD reproducing device according to the present invention.
This will be explained in detail with reference to the following. In FIG. 7, parts that are the same as those in FIG. 5 are indicated with the same - symbol, and only the different parts will be described here. That is, the DFF [i21
The output terminal Q of the circuit 30 is connected to the input terminal D6C of another DFF circuit 35.
It is also connected to one input end of the AND circuit 31. Then, the clock input terminal C of this DFF circuit 35 is connected to the input terminal 2 through a NOT circuit 36t'' in the opposite direction.
Connect to 7. Further, the inverted output terminal Q of the DFF circuit 35 is connected to the other input terminal of the AND circuit 31.

In the above configuration, the following Figures 8(a) to (j
The operation will be explained with reference to the timing diagram shown in ).

However, the signals shown in FIGS. 8(a) to (j) are generated at points (a) to (j) in FIG. 7, respectively. Then, first, as mentioned earlier, the output terminal 33 receives
A signal shown in FIG. 8(g) is generated. This figure 8 (g
As mentioned above, the falling edge of the signal shown in ) is synchronized with the polarity reversal of the EFM signal (see FIG. 8(a)), and its rising edge is generated first after the polarity reversal of the EFM signal. It is synchronized with the falling edge of the control pulse signal (see FIG. 8(b)).

On the other hand, by supplying the signal shown in FIG.
From the output terminal Q of the DFF circuit 3o, as shown in FIG.
The f signal is latched at the rising edge of the control pulse signal (see Fig. 8 (b)), and the signal shown in Fig. 8 (f) is delayed by 1/2 period of the control pulse signal (h ) is output. Therefore, from the output terminal Q of the DFF circuit 35, the signal shown in FIG. 8(h) is launched at the rising edge of the control pulse signal, and the polarity is inverted, and the signal shown in FIG. 8(h) is output. A signal vil delayed by 1/2 cycle of the control pulse signal and a signal shown in FIG. 8(i) with inverted polarity are output. By supplying the signal shown in FIG. 8(h) and the signal shown in FIG. 8(i) to the AND circuit 31, the output terminal 34VC is output as shown in FIG.
The signal shown in j) is output. The rise of the signal shown in FIG. 8(j) is synchronized with the time when the control pulse signal is delayed by 1/2 cycle after the rise of the signal shown in FIG. 8(g), Control pulse signal 'i'y k
It is synchronized at a point delayed by 1/2 period.

Here, output terminals 33 and 34 are output.
The values shown in Fig. 8<g) and (j) have the same properties as the signals shown in Fig. 6(g) and (ri) without any correction, and the pulses of both signals are The difference in width corresponds to the phase difference between the EFM signal and the control pulse signal.

Therefore, the phase of the control pulse signal can be changed by using the signal shown in FIG. , the phase of the EFM signal can be adjusted to the phase of the EFM signal, which has a period more irregular than the period of the control pulse signal, and whose period is an integral multiple of the control pulse signal.

The frequency increasing and decreasing pulse signals U and D shown in Fig. 8 (g) and (j) are generated close to each other, and the signal shown in Fig. 8 (g) rises. After that, the signal shown in FIG. 8(j) rises at a time interval (off time) equal to 1/2 period of the control pulse signal, so that the frequency increasing and decreasing pulse signals U and D are mutually separated as described above. Since they do not interfere with each other, accurate phase alignment can be performed as a phase-locked loop circuit.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, it is possible to perform stable and accurate phase alignment for pulse signals with irregular periods with a simple instruction, and for example, it is possible to perform stable and accurate phase alignment for pulse signals with irregular periods. It is possible to provide an extremely good phase-locked loop circuit suitable for use in synchronized clock regeneration, etc.

[Brief explanation of drawings]

Figure 1 is a block configuration diagram for explaining the entire phase-locked loop, Figure 2 is a block circuit diagram specifically showing the charge pump circuit and loop filter circuit in the phase-locked loop, and Figures 3 and 4. (a) to (d) are block configuration diagrams and timing diagrams thereof showing a conventional phase comparator used in the same phase locked loop; FIGS. 5 and 6 (a) to (i) Other conventional phase comparator main body block circuit diagrams and timing diagrams of each part thereof, FIGS. 7 and 8 (a) to U) It is a block circuit configuration diagram showing an example of a loop circuit and a timing diagram of each part thereof. 11... Input terminal, 12... VCo, 1B... Phase comparator, 14... Charge pump circuit, 15...
Loop filter circuit, 16... Output terminal, 17...
Operational amplifier, 18... Phase comparator main body, 19.20.
...Input terminal, 21.22...Output terminal, 23...
Input terminal, 24...DFF circuit, 25...EX OR circuit, 26...DFF circuit, 27...Input terminal, 2
8...DFF circuit, 29...NAND circuit, 30...
・DFF circuit, 31...AND circuit, 32...NOT circuit, 33.34...Output terminal, 35...DFF
Circuit, 36...knot circuit. Applicant's agent Patent attorney Takehiko Suzue 1 Inquiry official 2 Illustration official 3 @ 8 No. 45! ! (d)

Claims (1)

[Claims] A first pulse signal outputted from the voltage controlled oscillator and a second pulse signal input from the outside are phase-compared, and the phase difference component is outputted to the voltage controlled oscillator via a total charge pump circuit and a loop filter circuit. The phase-locked loop circuit is configured to control one oscillation frequency of the voltage-controlled oscillator to match the phase of the first pulse signal with the phase of the second pulse signal. a7) A first phase difference signal that is generated in synchronization with the polarity reversal of the second pulse signal; a signal generating means, and a first phase difference signal outputted from the first phase difference signal generating means is generated in a state in which generation is stopped, and in a state in which a nucleus is generated, the first phase difference signal is outputted from the first pulse signal. a second phase difference signal generation means for outputting a n:6 second phase difference signal that is generated and stopped in synchronization; and the first phase difference signal is generated in response to the first and second phase difference signals. and a control means for controlling a predetermined time interval between when the first and second phase difference signals are stopped and when the second phase difference signals are generated; The difference in the period of occurrence of
and a second pulse signal.