JPS6062241A - Phase control circuit - Google Patents

Abstract

PURPOSE:To eliminate the influence of variation in the output amplitude of a Miller integrating circuit upon control characteristics by supplying the output of the Miller integrating circuit to an AGC circuit, and applying the output of the AGC circuit to a phase shifting circuit. CONSTITUTION:The Miller integrating circuit 16 inputs a clock reproduced by a phase-locked loop from a restored data signal and its output signal is supplied to the AGC circuit 17. The output of the circuit 17 is sent to the phase shifting circuit 19 and the clock signal is sent to the circuit 19 as well to output the composite output of the both. Consequently, the influence of variance in the output amplitude of the Miller integrating circuit upon control characteristics is eliminated, and the circuit scale is reduced.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a phase control circuit included in all the components of an integrating circuit, and in particular to clock phase control of a digital signal and a phase control suitable for integrating the circuit into an IC. It is related to circuits.

[Background of the invention]

Video tape recorders (VTRs) in recent years are becoming smaller due to improvements in magnetic recording density.

Along with this, the running speed and recording track width of magnetic tapes are decreasing.

As a result, in the method of recording audio signals with a fixed head using the high frequency bias method, the reduction rate of the frequency bandwidth reproduction S/
This will result in deterioration of reproduced sound quality such as deterioration of N and wow/flutter characteristics.

One way to prevent these deteriorations is to convert the audio signal into a PCM signal and record it in the overlap area (the period in which multiple heads scan the magnetic tape at the same time) using a rotating head. Are known. One of the modulation methods for the Pct■ signal in this recording method is the biphase mark modulation method.

This pi-phase mark modulation method is described, for example, in Nikkei Electronics J, December 1978 issue, p.

As described in 128, this is a method in which the magnetization reversal interval is set at a minimum of 1/2 of the bit period (T) and at a maximum equal to the bit period. Therefore, clock reproduction and data demodulation are easy. It has the characteristic of being.

FIG. 1 shows the waveform of a bi-phase merge signal obtained by this modulation method. In the figure, (1) shows a serial data string with a bit period T of a PCM signal, and (2) shows a signal biphase mark modulated based on this serial data string.

As shown in this figure, the biphase mark modulation method always inverts the state at the data boundary, and for data '1', the state inverts when the time is 0.5T behind the data boundary. It is a method.

FIG. 2 shows an example of a reproduction circuit for restoring a signal magnetically recorded using this biphase mark modulation method to an original biphase mark signal. In addition, Figure 1 (3)
to (5) show approximate waveforms of various parts when a signal is reproduced by the reproduction circuit of FIG.

In FIG. 2, a signal reproduced from the magnetic tape 1 by the magnetic head 2 is amplified by a reproduction amplifier 3, and waveform-equalized by a reproduction equalizer 4, resulting in a waveform shown in (6) in FIG. This is because the impulse component corresponding to the edge E+ + E2 +... of the recorded signal shown in (2) in Figure 1 becomes smooth due to the differential characteristics and band limit characteristics in the reproduction process of the magnetically recorded signal. It is something that

This signal (3) is integrated by the integrating circuit 5, which has a characteristic opposite to the differential characteristic, and becomes an output signal as shown in (4) in FIG. The output signal (4) of the integrating circuit 5 is amplified to the limit by the limiter 10, and as shown in (5) in FIG. 1, becomes a pi-phase mark signal corresponding to the recording signal shown in (2) in FIG. will be restored.

However, this restored pi-phase mark signal (5)
is affected by code amount interference and jitter noise, so
It is necessary to re-identify the signal (5) at the best data identification point (a point delayed by 0.25 T or 0.75 T from the data boundary) and reproduce the data.

Experimental results have been obtained that in the above data identification, if the actual data identification point deviates from the best identification point of the restored signal (5), the data bit error rate is significantly degraded.

Therefore, in the data identification circuit that performs data regeneration, the phase of the clock signal that is regenerated by the phase-locked loop (hereinafter referred to as PLL) is inputted into the restored circuit at the input stage of the circuit that actually performs data identification. It is necessary to synchronize the phase of the data signal (5).

For this reason, a data identification circuit including a phase control circuit for synchronizing the phase of the reproduced clock signal with the data signal (5) has been considered.

FIG. 3 shows an example of the above data identification circuit.

In FIG. 3, a restored data signal 50 input from an input terminal 100 is amplified to a limit by a limiter 10, and data pulses 51, l! : Naru.

This data pulse 51 is input to a phase detection circuit 12 and is compared in phase with an output signal 56 of a voltage controlled oscillator (hereinafter referred to as ■CO) 14.

The detected output 54 of this phase detection circuit 12 has high frequency components attenuated by a low pass filter (hereinafter referred to as LPF) 16, and is inputted to the VCO 14 as a control signal.

The above phase detection circuit 12. LPF13. VCO14
1''j:, PLLk configuration, and reproduces a clock based on the data pulse 51.

On the other hand, the other phase detection circuit 30 detects the data pulse 5.
1 and a clock pulse 60, and the phase detection circuit 6 compares the phases of both pulses.
After the high frequency component of the detection cuff 0 of 0 is attenuated by the LPF 31, it is inputted to the phase shift circuit 1B as a control signal 71.

The phase shift circuit 18 is a D-type flip-flop (hereinafter referred to as
At the input stage of the data identification circuit 20, in which the data pulse 51 and the clock pulse 60 are synchronized, the phase of the clock 56 reproduced by the PLL is shifted. .

The above phase detection circuit 30. LPF31. The phase shift circuit 18 constitutes a clock phase control circuit as described above.

The limiter 19 amplifies the clock 59 whose phase has been shifted by the above-mentioned phase control circuit to a limit and generates the above-mentioned clock pulse 60. Identification circuit 200 output 62 is a regenerated data pulse.

FIG. 4 shows a general example of a phase shift circuit constituting the phase control circuit in the data strobe circuit described above.

In FIG. 4, a portion surrounded by a broken line 18 is a phase shift circuit. The parts other than this phase shift circuit are the same as the explanation of the phase control circuit used in FIG. 6 above, and the explanation here will be omitted.

The clock 56 regenerated by the PLL in FIG. 3 is input from the input terminal 113 in FIG. . The inverter 33 inverts the phase of the reproduced clock 56 and inputs the inverted clock 72 to the vector addition circuit 32.

The Miller integration circuit 16 generates a delayed clock 57 whose phase is delayed by 90 degrees from the reproduced clock 56, and applies its output signal to the vector addition circuit 32 as a second signal.
i k Input to inverter 34 2) Inverter 64
Then, the phase of the delayed clock 57 is inverted and the delayed inverted clock 73f is inputted to the vector addition circuit 62.

The vector addition circuit 32 uses the phase detecting cuff 1 described in FIG. 3 to perform phase shifting of the four clocks, each having a phase difference of 90 degrees, by applying a force p*' vectorwise.

As a specific example, the operation of the vector addition circuit 62 will be explained using the signal vector diagram shown in FIG. In FIG. 5, the arrows indicate the vectors (that is, the phases and amplitudes) of each of the clocks and their combined signals, and the phase of the reproduced clock 56 is taken as the zero degree of the reference phase.

1. If the amplitudes of the clock 56 and the delayed inverted clock 76 are equal, 1. <, assuming that the vector additions are equal, the combined signal will be the vector i in FIG. 5(1). Further, the combination of the clock 56 and the delayed clock 57 becomes a vector e in the figure. In this case, the phase θ1. θ2 is 45 degrees,
It will be -45 degrees.

Note that vectors a, b, and c in (1) of the same figure are clock 56.
．． Delayed inverted clock 73. A vector of the delayed clock 57 is shown.

The above-mentioned composite signal d with a phase shift of 45 degrees and composite signal e with a -45 degree phase shift have an addition ratio (1-P) determined by the control signal 71.
:P (0≦P≦1), resulting in a vector h shown in FIG. 5(2). A solid line 1 in FIG. 5(2) shows the locus of the vector h as the addition ratio is changed. If P is 025, the addition ratio is 0.75:0.25
Therefore, the phase shift amount θ is approximately 26 degrees.

The above is an example of a vector addition type phase shift circuit, but phase shift circuits using these Miller integration circuits have the following problems.

Due to variations in the capacitor and resistance that determine the time constant of the Miller integration circuit 16, the output amplitude of the Miller integration circuit will vary. For this reason, the amplitudes of the delayed clock 57 and the delayed inverted clock 7B input to the vector addition circuit 32 vary, and the output amplitude and possible phase shift range of the phase shift circuit 18 are not determined.

In particular, when the Miller integration circuit 16 is configured using elements within an IC, the variation in the integration time constant becomes extremely large.

Therefore, in the phase control circuit using the phase shift circuit 18 described above, the phase control range and the variation range of the output amplitude will not be constant. As a result, the identification points vary when identifying data, which has the drawback of increasing the data bit error rate.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and its purpose is to provide a phase control circuit with a small circuit scale in which variations in output amplitude in the Miller integration circuit do not affect control characteristics. It's about doing.

[Summary of the invention]

To achieve the above object, the present invention provides a Miller integrator circuit which receives a clock signal regenerated by a PLL from a restored data signal, and a Miller integrator circuit to which the clock signal is applied as a first signal. At least a phase shift circuit to which an output signal is applied as a second signal and which synthesizes and outputs the first signal and the second signal according to a control signal created based on the data signal. In the phase control circuit, the above Miller integrating circuit is
An automatic gain control circuit (hereinafter referred to as (Described as AGC circuit.)
This eliminates the influence of variations in the output amplitude of the Miller integrator circuit in the phase shift circuit, keeps the phase control range of the phase control circuit constant and the output amplitude variation range, and allows the clock to be used for data identification. The feature is that it eliminates variations in phase synchronization between and data.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. 6th
The figure is a block diagram of an embodiment of the present invention, and the same reference numerals as in FIG. 3 represent the same or equivalent parts.

FIG. 6 shows an example of a data strobe circuit used for reproducing audio signals magnetically recorded by the pi-phase mark modulation method to which the present invention is applied, and the portion surrounded by a broken line is an IC configuration.

In FIG. 6V, the restored data signal 50 is inputted from the input terminal 100 and is amplified by the limiter 10 to become a data pulse 51. This data pulse 51
is input to the delay circuit 11 and becomes the delayed data pulse 52 delayed by the time τ.

This delayed data pulse 52 and the data pulse 51
is input to the exclusive OR circuit (hereinafter referred to as E
It is written as an x-OR circuit. ) 25 produces an edge pulse 53 having phase information of the data pulse 51.

The sample-and-hold circuit 12 as a phase detection circuit is
The output signal 55 of VC'014 passed through the buffer 15,
The edge pulse 56 is sampled and held, and the phase of the delayed data pulse 52 and the output signal 56 of the buffer 15 is substantially detected.

An amplifier 13 to which the output 54 of this sample-and-hold circuit 12 is input, resistors R1 and R2 connected to this amplifier 13, capacitors CI and C2 connected to output terminals 101 and 102, and a resistor R loop. Configuring the filter.

The phase detection output (output of the sample-and-hold circuit) in which high frequency components are attenuated by this loop filter is input to the VC014 as a control signal.

V C014 in this embodiment is connected to output terminals 103 and 104.
This is an LC oscillator using a tank circuit consisting of a capacitor C3 and a coil L1 connected to the LC oscillator. The frequency is controlled by using the Miller integration circuit 16 and the phase shift method explained in FIG.
This is controlled based on control signals.

Sample and hold circuit 12 above. loop filter,
The LC vector addition type VCO 14 has a complete PLL configuration l~, and reproduces a clock based on the data pulse 51.

The Miller integration circuit 16 receives the VCO1 which has passed through the buffer 15.
4, that is, integrating the reproduced clock 56, the phase is delayed by 290 degrees from VC. This Miller integration circuit 1
The output 57 of 6 is fed back to the LC vector addition type VCO 14 and is also input to the AGC circuit 17 .

The AGC circuit 17 suppresses variations in the amplitude of the output 57 of the Miller integration circuit 16 due to variations in the integral constant, maintains a constant amplitude, and inputs it as a second signal 58 to the vector addition type phase shift circuit.

Now, using the circuit explained in FIG. 4 as the vector addition type phase shift circuit 18, the effect of the AGC circuit 17 will be explained using FIG. 7 when the variation in the integral constant of the Miller integration circuit 16 is set to +6 dB. .

(1) in FIG. 7 shows that the output amplitude of the Miller integration circuit 16 is
The vector locus of the output signal of the phase shift circuit 18 is shown when the amplitude of the reproduced clock 56 is +6 (1B).

On the other hand, FIG. 2 (2) shows a case where the output amplitude of the Miller integration circuit 16 is -6 dB compared to the amplitude of the reproduced clock 56.

In FIG. 7, a indicates the reproduced clock 56 which is the output of the VCO i4, bl and b2 indicate the delayed clock 57 which is the output of the Miller integrating circuit 16, and cl and c2 indicate the delayed inverted clock 73. dl and d2 are bl, a and b
2 and a are synthesized, and el and e2 are synthesized by cl and a and c2 and a'5.

The output signal 59 of the phase shift circuit 18 is the same as the above dl and 0.
1, d2, and e2 are vector-added according to the control signal 71, and the vector trajectory of the output signal 59 is as shown in FIG. 7 (1) and (2) at 11° 2.

In this way, if the output of the Miller integrator circuit 16 varies by +6 (1B), the phase shift range will be +63.4°, and the fluctuation in the output amplitude will affect 7 dl(2). In the case of a variation of 16 dB, the phase shift range is ±266° and the amplitude variation is 2d13.

However, AGCI! :+] If the variation in the output amplitude of the Miller integration circuit 16 is suppressed by the path 17, the phase shift range of the phase shift circuit 18 will be ±45°, as shown by the dotted lines in FIG. 7 (1) and (2). In other words, the output amplitude variation can be kept at 3d13.

In this embodiment, a Miller integrating circuit is used as the integrating circuit, but it is clear that similar effects can be obtained even when other equinox circuits are used.

Next, the phase detection circuit for the delayed data pulse 52 and clock pulse 60 will be explained using the input/output waveform diagram of FIG. 8.

The clock pulse 60 is a clock pulse (referring to the output 56 of the VCCN 4) reproduced by the PLL, phase-shifted by the phase shift circuit 18, and then limit-amplified by the limiter 19 to become a rectangular wave.

In FIG. 8, (1) shows the serial data string of the pit period of the PCM signal, and (2) to (11) in the same figure,
The waveforms of the input and output signals of each block making up the phase detection circuit are shown.

Note that the control signals 65 and 66 of the phase shift circuit 18 are obtained by integrating the output of this phase detection circuit.

This phase detection circuit is shown as D-F and F' in FIG.

20.21, an Ex-OR circuit 24.25, and an inverter 26V.

-4t'', delayed data pulse 52 and clock pulse 60
A case will be explained in which the phases of V and V are completely synchronized and the phase shift is zero.

The states of the delayed data pulse 52 and lock pulse 60 in this case are (3) and (2) in Figure 8, and these signals are input to DF' and F.

The output 62 of the lock pulse 60 becomes a signal whose phase is synchronized with the rising edge of the lock pulse 60 as shown in FIG. 8(6).

The output 63 of the Ex-OR circuit 24 to which this output 62 and the delayed data pulse 52 are input is (7) in FIG.
) is the signal shown.

As shown in (10) in FIG. , 20
(7) The output 62 is a signal delayed by T/4 (T is the bit period). The output 61 of the D-F, F, 21 and the output 64 of the Ex-OR circuit 25 to which the delayed data pulse 62 is input become the signal shown in (11) in FIG.

The output 64 of this Ex-OR circuit 25 is
It is a signal obtained by delaying the output 66 of the circuit 24 by T/4. Therefore, if these signals 63.6/l- are integrated by resistors R4 and R5 and capacitors C5 and C6 connected to output terminals 107 and 106, they become equal voltages.

Next, a case in which the delayed data pulse 52 lags behind the clock pulse 6o and a case in which it leads the clock pulse 6o will be explained.

In FIG. 8, states (2) and (4) are the above-mentioned delayed cases, and states (2) and (5) are the advanced cases.

In this way, the clock pulse 6o and the delayed data pulse 52
If the phase is shifted from that, the output 63 of the Ex-OR circuit 24 changes depending on the amount of phase shift.

For example, if the signal is delayed as described above, the pulse width becomes narrower as shown in (8) in FIG. 8, and if the signal is delayed, the pulse width becomes wider as shown in (9).

Therefore, if this signal 63 is integrated by the resistor R4 and the capacitor C5 connected to the output terminal 107, the integrated signal 65 becomes a low voltage if it is delayed as described above, and a high voltage if it is ahead. .

On the other hand, the output 64 of the Ex-OR circuit 25 becomes a signal with a constant pulse width as shown in (11) in FIG. 8, regardless of the phase shift between the clock pulse 60 and the delayed data pulse 52. Therefore, the signal 66 obtained by integrating this signal 64 by the resistor R5 and the capacitor C6 connected to the output terminal 106 is the output 6 of the EX-OR circuit 24.
This serves as a reference signal for the signal 65 obtained by integrating 5.

The phase detection circuit described above and the vector addition type phase shift circuit 18 constitute a phase control circuit, which controls the phase of the clock pulse 60 so as to be phase synchronized with the delayed data pulse 52.

The output 62 of the D-F, F, 20 used in the phase detection circuit is a data reproduction signal in which data of the delayed data pulse 52 is identified based on the clock pulse 60.

This data reproduction signal 62 and the clock pulse 60 which is in phase synchronization with this data reproduction signal 62 are input to the output circuit 22, amplified to the required level, and outputted from the output terminals 109 and 108 as a PCM signal. output to a demodulation circuit (not shown).

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the following effects are achieved.

(1) There is no need to adjust for variations in the integral constant in the integrating circuit.

(2) The phase shift range of the phase shift circuit and the variation amount of the output amplitude can be made constant, and the control characteristics of the phase control circuit can be made constant.

(3) When integrated into an IC, it is difficult to achieve absolute accuracy for the capacitance and resistance that determine the integration time constant, and the design margin increases.

(4) Since the above-mentioned integrating circuit is also used as the integrating circuit used in the CO, the number of elements is reduced and the circuit configuration is simplified.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing waveforms in the reproduction process of a biphase mark signal and a magnetically recorded biphase mark signal, and FIG. 2 is a block diagram showing a reproducing apparatus for a magnetically recorded biphase mark signal. Figure 6 is a block diagram of a data strobe circuit for transmitted digital signals, Figure 4 is a block diagram of a clock phase control circuit used in the data strobe circuit, and Figure 5 explains a vector addition type phase shift circuit. Figure 6 is a block diagram of a data strobe circuit to which the phase control circuit of the present invention is applied. Figure 7 shows the output signal of the phase shift circuit when the output of the Miller integration circuit varies. The vector diagram shown in FIG. 8 is a waveform diagram showing the input and output waveforms in each block configuring the phase detection circuit used for clock phase control. 1. Tape 2. Head 3. Regenerative amplifier 4. Reproduction, etc. Converter 5...Integrator circuit 10. H'...Limiter 12.
50... Phase detection circuit 13.31 Low pass filter 14... Voltage controlled oscillator 15... Buffer 16. Miller dregs separation circuit 17 Automatic gain control circuit 18. Vector Kaga type phase shift circuit 1 Figure; Engineering: Sagi 2 Fig. r) 3rd old) 00 no dew S: Hiro l Fig. 5 (2), qo' -9σ 19σ -6σ Rabbit 7 Fig. (2) 190°----7: ------- −−−−”: =9σ

Claims (4)

[Claims] (1) Regenerated from the recovered data signal in a phase-lock druz manner. an integrating circuit that inputs a clock signal;
The clock signal is applied as a first signal, the output signal of the integrating circuit is applied as a second signal, and the first signal and the second signal are controlled according to a control signal created based on the data signal. In a phase control circuit equipped with at least a phase shift circuit that synthesizes and outputs the
A phase control circuit comprising: an automatic gain control circuit that inputs the output signal of the integration circuit; and a configuration in which the output signal of the automatic gain control circuit is applied as the second signal to the phase shift circuit. . (2) A patented control circuit characterized in that the M-minute path is also used as an integrating circuit used in a phase-locked loop. (3) The first signal is an output signal of a voltage controlled oscillator configured to provide positive feedback of a vector-combined signal of the first signal and the second signal. 1. The phase control circuit according to item 1. (4) The phase control circuit according to claim 1, wherein the integrating circuit is a Miller integrating circuit.