JPH02306720A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To segment a data at an optimum point at all times by controlling a phase error between a delay input signal and a recovered clock signal so that the error is always eliminated. CONSTITUTION:A signal (e) of a voltage controlled oscillator (VCO) of a 1st phase locked loop circuit (PLL circuit) 19 is inputted to a 2nd phase comparator 20 via a duty ratio variable circuit 7, the signal is phase-compared with a delay input signal (b) from a delay device, and its phase error output l is inputted to a control terminal T5 of the duty ratio variable circuit via a 2nd low pass filter (LPF). The duty ratio of a VCO signal (f) being an output of the duty ratio variable circuit varies with the phase error output l varies with the phase error output l to constitute the PLL circuit 21 and the phase error output lbetween the delay input signal (b) and the VCO signal (f) being the output of the duty ratio variable circuit is controlled with high accuracy by the characteristic of the negative feedback system of the PLL circuit so that the error output is eliminated at all times. Thus, the complete automation of the data optimum segmenting point is attained.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a phase-locked loop circuit (hereinafter referred to as "phase-locked loop circuit") capable of extracting a clock signal from an input pulse signal having an arbitrary repetition period (for example, IT to 4T). This is related to a PLL circuit (called a PLL circuit).

(Prior Art) Conventionally, as a PLL circuit that needs to detect the edge of an input signal in order to extract a clock signal from an input pulse signal having an arbitrary repetition period, the one shown in Fig. 3 has been put into practical use. has been done.

In FIG. 3, 1 is an input signal source, 2 is a delay device for delaying the input signal, and 3 is an exclusive OR (hereinafter referred to as EX-
4 is an analog switch, 18 is a phase comparator composed of the above-mentioned 2, 3, and 4, 5 is a low-pass filter (hereinafter referred to as LPF) for smoothing the output of the phase comparator 18, 6 is a voltage controlled oscillator (hereinafter referred to as VCO) 16 whose oscillation frequency is controlled by the output obtained from the phase comparator 18 via an LPF;
17 is an inverter, and 17 is an NRZ converter for converting the NRZI signal, which is the delayed input signal (b) output from the delay device 2, into an NRZ signal using the recovered clock (e) at the T4 output terminal.

FIG. 4 is a time chart of FIG. 3.

Next, the operation of the PLL circuit configured as described above will be explained below with reference to FIGS. 3 and 4. First, the input pulse signal (a) shown in FIG. 4 having an arbitrary repetition period is input to the input terminal T1, and the input pulse signal (a) is a signal (a) directly input to the EX-OR gate 3. , a delayed input signal (b) delayed through the delay device 2, and a delayed input signal (c). The delayed input signal (c) is delayed from the input signal (a) by a delay time (T/2) determined by a delay device 2,
It is input to EX-OR gate 3. The above delayed input signal (
The signal b) is delayed from the input signal (a) by T/4, which is the delay time determined by the delay device, and is input to the signal input terminal of the NRZ converter 17. The output of the EX-OR gate 3 is the EX- of the input signal (a) and the delayed input signal (e).
As shown in FIG. 4, the OR operation result has a fixed time width T W
It is output as the output pulse control voltage in (d). The H section of the above fixed time width T W (d) is the phase comparator ° The analog switch 4 is turned on and the phase difference between the reproduced clock (e), which is the output signal of the VCO 6, and the input signal (a) is compared with the phase difference. The phase comparator output (m) of the device 18 is output to the output terminal T3. In addition, during the period L of the fixed time width T W (d), the analog switch 4 is off and performs a sample and hold operation to hold the previous value of the phase error voltage and output it as the phase comparator output (o) of the phase comparator 18. It is output to terminal T3.

Furthermore, by controlling the frequency of the VCO 6 using the DC output (n) smoothed by the LPF 5, the P
A regenerated clock (e
) is extracted. The recovered clock (e) is input to the lock input terminal of the NRZ converter 17 through the inverter 16. Furthermore, the delayed input signal (b) is the NRZ
By being input to the signal input terminal of the converter 17, N
The reproduced NRZ signal (P) was extracted from the output terminal T7 of the RZ converter.

(Problem to be Solved by the Invention) However, in the conventional PLL circuit configured as above, when extracting the reproduced signal (p) from the output of the NRZ converter, the reproduced clock signal (e) and the delayed input signal (b)
As a means for delaying the input signal (a) in order to match the timing of the input signal (a), the delay device 2 includes an external fixed delay element,
Or, if a delay circuit must be used, and an external fixed delay element is used, use a fixed delay element with a tap to match the timing of the delayed input signal (b) and the recovered clock signal (e). However, in reality, variations in parts always occur, so the delay amount (
T/4) and a delay error occurs.

Due to this delay error, the delayed input signal (b) cannot be punched out by the reproduced clock signal (e) at the optimum point as per the designed value, and a punching error occurs by the amount of delay caused by component variations or within the circuit. When this punching error occurs, the input signal is actually not an ideal pulse signal but a sinusoidal signal.
Because of the wave shape, punching errors immediately result in a reduction in S/N (signal to noise), which has a serious drawback that ultimately leads to a worsening of the error rate.

Further, even when the delay device 2 is configured as an IC, in order to absorb variations in components, as described above, external components must be used to make fine adjustments. On top of that,
Regarding temperature characteristics, there were many drawbacks such as difficulty in operating stably.

The present invention solves the above-mentioned conventional problems, and provides a PLL circuit that has a simple configuration, creates a variable duty ratio circuit for the co signal, has high accuracy, and can completely automate the optimum punching point of data. It is an object.

(Means for solving problem W) The present invention achieves the above object. For this purpose, a first phase comparator, a VCO, and a first L
A first PLL circuit configured with a PF, a second phase comparator capable of phase locking to an input signal delayed from the input signal, a second LPF, and a duty ratio thereof controlled by using the vC○ signal as input. It has a variable duty ratio circuit controlled by voltage, the output of the variable duty ratio circuit is input to the second phase comparator, and the output of the second phase comparator via the second LPF is controlled by the duty ratio. A second PLL circuit is configured as a control voltage of the variable circuit, and the above-mentioned ■C○ output is taken out from the output of the above-mentioned duty ratio variable circuit.

(Function) Therefore, according to the configuration of the present invention, the VCO signal (e) of the first PLL circuit 19 is inputted to the second phase comparator 20 via the variable duty ratio circuit 7, A phase comparison is made with the delayed input signal (b), and the phase error output (11) is inputted to the control terminal T5 of the variable duty ratio circuit via the second LPF. It is input to the control terminal T5 of the variable duty ratio circuit. By changing the duty ratio of the VCO signal (f) which is the output of the variable duty ratio circuit in accordance with the phase error output (it), the second PLL circuit 21 is configured, and the characteristic of the negative feedback system of the PLL circuit is As a result, the phase error output (11) between the delayed input signal (b) and the vcO signal (f) output from the variable duty ratio circuit is precisely controlled so that it always disappears in the second phase comparator 2o.

(Embodiment) FIG. 1 shows a block diagram of a PLL circuit in an embodiment of the present invention. In Figure 1, 1 is an input signal source, 2 is a delay device, 3.11.12 is an EX-OR gate, 4
, 13.14 is analog switch, 5゜15 is LPF,
6 is a VCO, 7 is a variable duty ratio circuit, 8 is a monomulti, 9 and 1o are D-type flip-flops (D-FF), 1
6.22 is an inverter, 17 is an NRZ converter, 18 is a first phase comparator, 19 is a first I) LL circuit, 20 is a second phase comparator, and 21 is a second I)) LL circuit.

The difference from the conventional PLL circuit is that there is a variable duty ratio circuit 7 for changing the duty ratio of the second phase comparator 20, second LPF 15 and VC06, and a monochrome circuit for adjusting the timing of each signal. A second PLL circuit 21 is configured by adding a multi-channel 8 and an inverter 22. In addition.

Blocks with the same numbers as in FIG. 3 are blocks that perform the same operations as in the conventional example.

FIG. 2 is a time chart of the PLL circuit of FIG. 1.

Next, the operation of the above embodiment will be explained. Note that the explanation of the operation of the blocks having the same numbers as those in FIG. 3 will be omitted.

In the above embodiment, the delayed signal input (b) is input to the input terminals of D-FF9 and EX-ORII that constitute the second phase comparator 20, and is also input to the input terminal of the NRZ converter 17. . On the other hand, the VCO output (e) whose phase is synchronized with the input signal (a) is input to the inverter 16 via the variable duty ratio circuit 7. The monomulti 8 is configured to output a VCO waveform (:) with a constant duty ratio (50%:50%) as shown in Figure 2 using the VCO signal (f) that is the inverter output as a trigger force. . The output of the monomulti 8 via the inverter 22) is D
-Input to the clock input terminal of FFIO. The output (7) of the inverter 16 is input to the clock input terminal of the D-FF 9 and to the clock input terminal of the NRZ converter for converting the NRZI signal into an NRZ signal.

The second phase comparison W2o is D-FF9,1o and EX-O
RII, 12 and analog 5W13.14'? ? The delayed input signal (b) and the VCO output (f)
A phase error output (G) between the two is output to the output terminal T8.

The phase error (G) is input to the control terminal T5 of the variable duty ratio circuit via the LPF 15 of the second PLL circuit. Therefore, the delayed input signal (b) and the vcO signal (f
) The operation timing waveforms of each part in the case where there is no phase error with respect to the above are shown in FIG. Delayed input signal (
b) and the vco signal (f), a phase error output voltage (11) is generated at the output terminal T8 of the second phase comparator 2o. ), for example, if the variable duty ratio circuit 7 is configured with a monomulti, the charging/discharging time constant of the monomulti can be easily controlled using the above error voltage using the VCO output (e) as a trigger force. However, the VCO output (f) also adapts to the phase error output voltage (Q) so that the frequency is constant and only the duty ratio is controlled.
1 is configured, and the delayed input signal (b) and VC○
It operates as a phase error detection circuit with respect to the signal (f).

Therefore, in order to operate so that there is no phase error between the regeneration lock signal (f) input to the NRZ converter 17 and the delayed input signal (b), the NRZ conversion output terminal shaft 7
, the optimally punched reproduction signal (p) is always extracted.

(Effects of the Invention) As is clear from the above embodiments, the present invention allows a PLL circuit to be configured with a simple circuit configuration, and is automatically controlled so that the phase error between the delayed input signal and the reproduced clock signal is always eliminated. Therefore, the influence of variable delay errors caused by external fixed delay elements and delay circuits can be ignored, making it possible to always punch out data at the optimum point, resulting in superior effects such as improved error rates.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a PLL circuit in an embodiment of the present invention, Fig. 2 is a time chart of a PLL circuit in the embodiment of Fig. 1, Fig. 3 is a block diagram of a conventional PLL circuit, and Fig. 4 is a block diagram of a PLL circuit in an embodiment of the present invention. 4 is a time chart of the PLL circuit in the conventional example of FIG. 3. FIG. 1... Input signal source, 2... Delay device, 3゜11,
12-EX-OR gate, 4,13゜14...
・Analog switch, 5, 15...LPF, 6・
...VCOl 7...Duty ratio variable circuit, 8
...Mono multi, 9. IO...D-FF, 16
．． 22... Inverter, 17... NRZ converter,
18... First phase comparator, 19... First PLL circuit, 20... Second phase comparator, 21... Second PL
L circuit. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1

Claims (1)

[Claims] A first phase comparator and a voltage controlled oscillator (VCO) that can be phase-locked to the input signal and a first low-pass filter (
a first phase-locked loop (PLL) circuit configured with an input signal delayed from the input signal, a second phase comparator and a second LPF that are phase-lockable to an input signal delayed from the input signal, and an output signal of the VCO. and a duty ratio variable circuit whose duty ratio is controlled by a control voltage, and an output of the duty ratio variable circuit is input to the second duty ratio variable circuit.
A second PLL circuit is constructed by using the output of the second phase comparator via the second LPF as the control voltage of the variable duty ratio circuit, and the output of the variable duty ratio circuit. A phase-locked device characterized in that the output of the VCO is taken out from the
loop circuit.