JPS6177426A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To eliminate in-time appearance of an error signal and a reference signal by inutting an input signal, an output of the 1st FF and an output of the 1st and 2nd gates to which the output of the 1st and 2nd FFs is applied to gate circuits respectively poled oppositely. CONSTITUTION:An input signal S3 is inputted sequentially to an FF 2 based on a clock signal S2 from an FF 4 inputting and frequency-dividing an output signal S1 of a VCO 17 into 1/2, and an output signal S4 of the FF 2 is fed to an EOR circuit 5 and the FF 3. The input signal S3 is fed to the circuit 5, and an output signal lS6 of the circuit 5 is inputted to a positive logical AND circuit 21 and a negative logic AND circuit 22. Further, an output signal S4 of the FF 2 and an output signal S5 of the FF 3 are inputted to an ENOR circuit 20. An output signal S7 of the circuit 20 is inputted to the circuits 21, 22. Output signals S8, S9 of the circuits 21, 22 do not apear at the same time, and the time difference of their appearance is decreased and an error signal and a reference signal having different polarity are outputted. The signals S8, S9 are inputted to an LPF 10 via diodes 8, 9 respectively and a VC011 is controlled by using a signal obtained from the error signal through the LPF 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention applies to gFM (Eight
The present invention relates to a phase comparator circuit suitable for use in a PLL circuit or the like that demodulates a clock signal from a modulated wave.

[Conventional technology]

As a PLL circuit that demodulates a clock signal from EFMyR harmonics, a circuit as shown in FIG. 4, for example, can be considered. That is, in the same figure, (1) is an input signal such as E
This is an input terminal to which an FM signal is supplied, and the EFM signal from this input terminal (1) is connected to a D-type flip-flop circuit (
2) is supplied to the input terminal DK. The output from the output terminal Q of the clip-flop circuit (2) is supplied to the input terminal DK of the D-type flip-flop circuit (3). The clock signal to these 7-lip 70-tub circuits (2) and (3) is D
The output of the type flip-flop circuit (4) is supplied. Note that the inverting output terminal Q and the input terminal of the flip-flop circuit (4) are interconnected, and the output of the voltage-controlled oscillator (111) provided in the PLL circuit is supplied to the clock terminal thereof.

Furthermore, the output of the 7-ridge flop circuit (2) is supplied to one input terminal of an exclusive OR circuit (hereinafter referred to as EOR circuit) (5), and the other input terminal of this EOR circuit (5) is An input signal from the input terminal (1) is supplied.

Furthermore, the output of the flip-flop circuit (2) is connected to the EOR circuit (
6), and this FJOR circuit (6) is supplied to one input terminal of the FJOR circuit (6).
) is supplied with the output of the flip-flop circuit (3).

The output of the EOR circuit (6) is supplied to one input terminal of a NAND circuit (7), and the inverted output of the flip-flop circuit (4) is supplied to the other input terminal of this NAND circuit (7). The output of the EOR circuit (5) is supplied to the anode side of the diode (8), and the output of the NAND circuit (7) is supplied to the cathode side of the diode (9). The cathode side of the diode (8) and the anode side of the diode (9) are commonly connected, and the connection point thereof is connected to the input side of the low-pass filter aI. And these components (2) ~
(9) constitutes the phase comparison circuit of the PLL circuit.

When a comparison error signal is obtained on the output side of this phase comparison circuit, this comparison error signal is converted into a DC signal (voltage) by a low-pass filter αG, and this DC signal! is supplied to the oscillator 011 as a control signal, and the oscillator (1
11, the oscillation frequency is controlled according to the error.

The output of the oscillator αυ is supplied as a clock signal to the clock terminal of the flip-flop circuit (4).

Next, the operation of the circuit shown in FIG. 4 will be explained with reference to the signal waveforms shown in FIG.

Now, oscillator αυ, signal S1 as shown in lE5 diagram AK.
is supplied to the clock terminal of the clip-flop circuit (4), the dedicated signal S2 as shown in FIG. 5B is taken out as a clock signal at its output terminal Q side,
This signal S2 is connected to flip-flop circuits (2) and (3)
is supplied to the clock terminal of

In addition, the input terminal (11 and #) has an EFM as shown in Figure 5C.
Signal S3 is input terminal DK of flip-flop circuit (2)
.

This gFM signal s3 is latched by the 7-ridge flop circuit (2) at the time when the signal s2 is applied, and the 5th
A signal S4 as shown in the figure is obtained. This signal S4 is supplied to the input terminal DK of the next-stage 7-lip 70-tub circuit (3), and as described above, when the next signal S2 is applied, it is latched by the flip-flop circuit (3). At the output terminal Q of , a signal S5 as shown in FIG. 5E is obtained.

The signal S3 from the input terminal (1) and the output signal S4 of the 7-lip 70-tub circuit (2) are supplied to the EOR circuit (5),
On the output side, a signal S6 as shown in FIG. 5FK is obtained as an error signal. This signal S6 is in an enabled (energized) state when it is at a high level K, as indicated by diagonal lines in FIG. 5F.

Further, the output signals S4 and S5 of the flip-flop circuits (2) and (3) are supplied to an FJOR circuit (6)K, and a signal S7 as shown in FIG. 5GK is obtained at its output side.

This signal S7 is further supplied to one input terminal of a NAND circuit (7), and an inverted output signal S (not shown) from a flip-flop circuit (4) is supplied to the other input terminal of this NAND circuit (power). As a result, a signal S8 as shown in FIG. 5H is obtained as a reference signal on the output side of the NAND circuit (7).This signal S8 has a low level as indicated by diagonal lines in FIG. It is in the enabled state when it is at level.

The signal S6 from the EOR circuit (5) is supplied to the low-pass filter αα via the diode (8), thereby unidirectionally charging a capacitor in the low-pass filter αα (not shown). In addition, the NAND circuit (signal S8 from the force
is supplied to the low chair filter 0ω via the diode (9), and this charges the capacitor in the above-mentioned low/4' square filter 111 in the other direction. Therefore, the difference between the charging amount due to the signal s6 and the charging amount due to the signal s8 is supplied as an error voltage to the oscillator αI), and the excavation frequency is controlled according to the error amount.

In addition, in @5 Figures C and F, the symbol J (corresponding to the solid line part) indicates that the phase of the EFM signal S3, which is the input signal from the long sword terminal (1), and the phase of the signal S2, which is the clock signal, match. In the case, the symbol S (corresponding to the dashed line part) is the EFM
When the phase of the signal s2 lags behind the phase of the signal S3, the symbol F (corresponding to the chain line) represents the case where the phase of the signal s2 leads the phase of the gFM signal S3.

Therefore, if the phase of the EFM signal S3 and the phase of the signal s2 match, the signal S will appear so that F and H in FIG.
Since the signal components (levels) of signals 6 and 88 are equal and the error amount is zero, the oscillation frequency of the oscillator αυ does not change and the one phase locked state is maintained.

On the other hand, if the phase of the signal s2 lags or leads the phase of the EFM signal S3, the fifth
As shown in Figures F and H, the signal components of signal 56S8 differ in phase, so the oscillator aυ
The oscillation frequency of the signal S is controlled, and if the oscillation frequency is behind, the oscillation frequency is increased, and if it is ahead, the oscillation frequency is lowered and the signal S
2 is made to match the phase of the input EFM signal S3.

Therefore, the output side of the flip-flop circuit (2) receives the signal S4 in synchronization with the signal S2, which is the reproduced clock signal.
is extracted as data, and this data is supplied to a demodulation circuit (not shown) and demodulated.

[Problem that the invention seeks to solve]

In the case of the circuit shown in FIG. 4, the signals S6 and 88 appear at the same time, as can be seen from the right-hand portions of FIGS. 5F and H. There is a case where the pick-up signals S6 and S8 are enabled at the same time, and therefore the diodes (8) and (9) to which these signals are supplied are simultaneously turned on, causing the error signal and the reference signal to become simultaneously trapped. Loaf 4th filter α
This may cause the operation of the low-pass filter aυ to become unstable.

In addition, in the case of the circuit shown in FIG. 4, a pair of signals S6 and S8
The time difference (timing) of the appearance of is very different (
Incidentally, in FIG. 5, the signal S
If the time difference is until the falling edge of signal S2, it is 1 as seen from signal S2.
), so the low-pass filter a
The average value of the voltage charged to the capacitor in I fluctuates, which is undesirable. It is preferable that this time difference, that is, the time interval between the appearances of the signals S6 and 88, be as short as possible, as long as they do not appear at the same time.

In addition, in the case of the circuit shown in Fig. 4, since the signals S6 and 88 appear at the same time, the run length minimum limit d
= 2, the minimum inversion interval of the multiple modulation waveform is three times the clock signal, in other words, there are at least two reversible points (in clock units) that do not invert between each inversion. Although it is applicable, it has the disadvantage that it cannot be used with a modulation waveform of d=Q, such as an 8/10 conversion waveform used in a digital audio tape recorder.

The present invention has been made in view of these points, and it is an object of the present invention to provide a phase comparator circuit that can eliminate the above-mentioned drawbacks.

[Means for solving problems]

The present invention includes a first flip-flop circuit (2) to which an input signal is sequentially supplied based on a constant clock signal, and a second flip-flop circuit (2) to which the output of the seven flip-flop circuits is sequentially supplied based on the clock signal. Lip 70 tube circuit (3
), a first gate means (5) supplied with the input signal and the output of the first flip-flop circuit, and a second gate means (5) supplied with the output of the first and second 7-lip 70-tub circuits. gate means (6), and a first gate circuit r2I to which the outputs of the first and second gate means are respectively supplied.
and a second gate circuit having a different polarity from this gate circuit, and a second gate circuit having different polarities which do not appear at the same time on the output side of the first and second gate circuits and whose time difference is shortened. The configuration is configured to obtain first and second signals having the following characteristics.

[Effect]

The first flip-flop circuit (2) K sequentially supplies input signals based on a constant clock signal, and outputs the output of the first flip-flop circuit (2) to the second seven-flip circuit (3) based on the clock signal. ), the output of the first flip-flop circuit (2) and the input signal are supplied to the EOR circuit (5) as a first gate means, and the first and second flip-flop circuits (2) The outputs of (3) and (3) are supplied to an exclusive NOR circuit (hereinafter referred to as ENOR circuit) as the gate means of S2, and the EOR circuit (5) and gNORNOR circuit specific power are supplied as the first gate circuit. A positive logic AND circuit anVC is supplied, and a negative logic AND circuit as a second r-) circuit is supplied so that it does not appear at the same time on the output side of AND circuits Qυ and @ and shortens the time difference in which they appear. first and second signals having different polarities, that is, an error signal and a reference signal, are obtained.

〔Example〕

Hereinafter, various embodiments of the present invention will be described in detail based on FIGS. 1 to 3.

FIG. 1 shows a first embodiment of the present invention. In the figure, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, an ENORNOR circuit blade as a second gate means is supplied to the output side of the second flip-flop circuit (3), and the flip-flop circuit (2) K of the input terminal Kg1 of this ENORNOR circuit blade is supplied. 7 at the input end
' Supply the output of the J-tube flop circuit (3).

Also, the first ? -) A positive logic AND circuit Qυ as a circuit and a negative logic AND circuit @ as a second gate circuit are provided, and the EOR circuit (5) and ENORNOR circuit power are supplied to the AND circuit Cυ, and the AND circuit is K to supply the same.

Further, in this case, the clock terminal to the flip-flop circuit (3) is connected to supply the inverted output of the flip-flop circuit (4) as a clock signal.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the signal waveforms shown in FIG.

Now from the oscillator α1)! Signal S as shown in Figure 2 AIC
When l is supplied to the clock terminal of the flip-flop circuit (4), a signal S2 whose frequency is divided by A as shown in FIG. is supplied to the clock terminal of the flip-flop circuit (2), and an inverted signal island (not shown) of the signal S2 is supplied to the clock terminal of the flip-flop circuit (3).

Further, an EFM signal S3 as shown in FIG. 2CK is sent from the input terminal (1) to the input terminal DIC of the flip-flop circuit (2).
This EFM signal S3 is latched by the flip-flop circuit (2) at the time when the signal S2 is applied, and the output terminal Q of the flip-flop circuit (2) has the second
A signal S4 as shown in the figure is obtained. This signal S4 is supplied to the input terminal of the seventh-stage flip-flop circuit (3), and as described above, when the next signal S2 is applied, the flip-flop circuit (3) is turned on by K and Y, thereby making the flip-flop circuit At the output terminal Q of (3), a signal S5 as shown in FIG. 2E is obtained.

The signal S3 from the input terminal (1) and the output signal S4 of the flip-flop circuit (2) are supplied to the EOR circuit (5),
On the output side, a signal S6 as shown in FIG. 2 FIC is obtained as an error signal. This signal S6 is enabled when it is at a high level, K, as shown by the diagonal line PK in FIG.

(energized) state.

Further, the output signals S4 and S5 of the flip-flop circuits (2) and (3) are supplied to the ENOR circuit (2), and a signal S7 as shown in FIG. 2GK is obtained as a reference signal at its output side. This signal S7 is in an enabled state when it is at a low level, as indicated by diagonal lines GK in FIG. EOR circuit (5) and ENORNOR circuit blade signals S6 and S7 are AND circuit CI! DK is supplied, resulting in AND circuit c
! 11, a signal S8 as shown in FIG. 2H is obtained as a true error signal. Similarly, the signal S6
and S7 are supplied to AND circuit K. As a result, a signal S9 as shown in FIG. 2I is obtained as a true reference signal at the output side of AND circuit (2).

The signal S8 from the AND circuit (21) is a diode (8)
The signal S9 from the AND circuit (C) is supplied to the low-pass filter (101) through which the capacitor in the low-pass filter (11 (not shown) is charged in one direction. The capacitor in the above-mentioned low-pass filter αα is then charged in the other direction.Therefore, the difference between the charge due to the signal S8 and the charge due to the signal S9 is supplied to the oscillator as an error voltage. αB, and the oscillation frequency is controlled according to the error.

Note that in FIG. 2C, the symbol J represents the timing point when the phase of the EFM signal S3, which is the input signal from the input terminal (1), and the phase of the signal S2, which is the clock signal, match. , if the signal S2 is ahead of the signal S3 by time 11 at the falling edge of the fs1 pulse of the signal S3, then at the rising edge of the second pulse, the signal S2 is ahead of the signal S3 by a time 11.
If signal S2 is delayed by time t2 with respect to signal S3, at the falling edge of the 214th pulse, if signal S2 is delayed by time t3 with respect to signal S3, at the rising edge of the 3rd/# pulse. 2 shows a case where the signal S2 advances by a time t4 with respect to the signal S3. Corresponding to the operating state of the waveform shown by the solid line in FIG. 2C, the movement of the signal at each point is shown by the solid line in FIGS.

As can be seen from Figure 2 H and ■, the AND circuit (21
The signal S8 obtained at the output side of the pair of signals S8 and the signal S9 obtained at the output side of the AND circuit do not appear at the same time, and there is a time difference between the two signals (the rise of the pair of signals S8 and the signal S9).
The timing up to the falling edge of 9 is A with respect to signal S2.
It can be seen that the time has been shortened to the clock time.

However, in the operation of the waveform shown by the solid line in Figure 2C, EO
The signal S6 obtained at the output side of the R circuit (5) and the signal S8 obtained at the output side of the AND circuit Qυ are exactly the same, and similarly, the signal S7 obtained at the output side of the ENOR circuit - and the AND circuit (c) The signal S9 obtained on the output side of is exactly the same, and it seems that the AND circuit I2v and I2v Co., Ltd. can be omitted, but its effectiveness can be clearly understood by considering the following case, for example.

That is, for example, when the falling edge of the 1st f pulse of the signal S3 shown in @2 Figure C changes to 5 as shown by the dotted line in the same figure, and the signal S2 becomes slower than the signal S3, Correspondingly, a signal S obtained at the output side of the EOR circuit (5)
6 also changes as shown by the chain dots in FIG. 2F. Then, as can be seen from Figure 2 F and G, this changed part is
This is undesirable because it overlaps with the appearance time of the signal S7 obtained on the ENORNOR circuit output side. Therefore, when such signals S6 and 87 are supplied to the AND circuit r2D and the circuit, a signal 0 signal S8 as shown by the chain line in FIG. 2H is obtained at the output side of the AND circuit Q11, while the On the output side, a signal S9 as shown by the dotted line in FIG. 2I is obtained,
These signals S8. S9 appears at different times and does not repeat.

In other words, it can be seen that appearances at the same time are avoided.

In this way, in this embodiment, the error signal S8 as the first signal and the reference signal S9 as the second signal have mutually different polarities and do not appear at the same time and have a shortened time difference. can be obtained.

FIG. 3 shows a second embodiment of the present invention, in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, an EOFL circuit (c) and a NAND circuit (2) are used in place of the ENOR circuit (2), and the outputs of the first and second flip-flop circuits (2) and (3) are connected to the EOR circuit c! 3, the output of this EOR circuit is supplied to one input terminal of the NAND circuit (2), and the output terminal Q of the flip-flop circuit (4) is supplied to the other input terminal of this NAND circuit (2).
to supply the output from.

Furthermore, in the circuit shown in FIG. 1, the output of the inverted terminal Q of the flip-flop circuit (4) is supplied to the clock terminal of the flip-flop circuit (3), but in this embodiment, the output of the inverted terminal Q of the flip-flop circuit (4) is supplied to the clock terminal of the flip-flop circuit (3). to supply the output from. The other configurations are the same as in FIG. 1.

The circuit operation is also substantially the same as that shown in FIG. 1, so a description of the operation will be omitted here.

In this way, substantially the same effects as in the first embodiment can be obtained in this embodiment as well.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate the occurrence of the error signal and the reference signal, which are the two outputs of the phase comparator circuit, at the same time, so that the run length minimum limit d=
It is also possible to use a modulated wave of o.

Further, since the time difference (timing) between the error signal and the reference signal can be reduced, the stability of the loop can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of FIG. 1, and FIG.
4 is a circuit diagram showing another embodiment of the present invention, FIG. 4 is a circuit diagram showing an example of a conventional circuit, and FIG. 5 is a signal waveform diagram for explaining the operation of FIG. r2+ , (31, (41 is a D-type flip 70-tub circuit, (5). The device is an exclusive OR (EOR) circuit, ■ is an exclusive NOR (ENOR) circuit, Qυ is a positive logic AND circuit, @ is a negative logic AND circuit, and @ is a NAND circuit. Figure 2'Iq)'
/Figure 5 H<sa

Claims (1)

[Claims] 1. A first flip-flop circuit to which an input signal is sequentially supplied based on a constant clock signal, and a second flip-flop circuit to which an output of the flip-flop circuit is sequentially supplied based on the clock signal. a flip-flop circuit; a first gate means to which the input signal and the output of the first flip-flop circuit are supplied; and a second gate means to which the outputs of the first and second flip-flop circuits are supplied. and a first gate circuit to which the outputs of the first and second gate means are respectively supplied, and a second gate circuit having a polarity different from that of the gate circuit; 1. A phase comparator circuit characterized in that first and second signals having mutually different polarities that do not appear at the same time and have a shortened time difference are obtained on the output side. 2. The phase comparator circuit according to claim 1, wherein an exclusive OR circuit and an exclusive NOR circuit are used as the first and second gate means, respectively. 3. The phase comparison circuit according to claim 1, wherein an exclusive OR circuit is used as the first gate means, and an exclusive OR circuit and a NAND circuit are used as the second gate means. 4. The phase comparator circuit according to any one of claims 1 to 3, wherein AND circuits of positive logic and negative logic are used as the first and second gate circuits, respectively.