JP2520560B2 - Phase comparison circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase comparison circuit,
In particular, it relates to a phase comparison circuit of a PLL (Phase Lock Loop) that extracts a clock from a CMI (Code Mark Inversion) code.

[0002]

2. Description of the Related Art In the CMI code, one time slot is divided into two, "01" is associated with code "0", and "00" and "11" are alternated with respect to code "1". Is a code corresponding to. Although there is a circuit using a ceramic filter as a circuit for extracting a clock signal from the CMI code, it is desirable to realize it as a PLL on an integrated circuit in consideration of downsizing and cost reduction.

Generally, a PLL is composed of a phase comparison circuit, a loop filter, and a voltage controlled oscillator circuit (VCO). FIG. 3 shows a conventional CMI code phase comparison circuit used in a PLL. This phase comparison circuit has an edge detection circuit 31, flip-flops 32 and 33, and an exclusive OR gate 34.

The edge detection circuit 31 is composed of, for example, a delay circuit and an exclusive OR (ExOR) gate, and takes the exclusive OR of the input CMI code and the CMI code delayed by the delay circuit. As a result, the input CMI
A pulse signal having a pulse width corresponding to rising and falling of the code and proportional to the delay time of the delay circuit is obtained.

The flip-flop 32 has a C terminal with a VCO.
Input the clock signal (VCO CLK) from
By inputting the bar output to the D terminal, the VCO
Divide CLK by two.

The flip-flop 33 receives the pulse signal from the edge detection circuit 31 at the C terminal, and the flip-flop 3
The Q bar output of 2 is used as the input of the D terminal.

The exclusive OR (ExOR) gate takes the exclusive OR of the Q output of the flip-flop 32 and the Q output of the flip-flop 33 and outputs it as a phase comparison output.

Next, the operation of the phase comparison circuit will be described with reference to FIGS. This phase comparison circuit has a CMI code shown in FIG. 4A and a VCO code shown in FIG. 4B.
CLK and are input. Here, as the CMI code, a code in which “01”, “01”, “00”, and “11” are consecutive is considered. Further, it is assumed that the falling edge of VCO CLK coincides with the change point of the CMI code.

The edge detection circuit 31 detects the rising and falling edges of the CMI code shown in FIG.
The pulse signal shown in (c) is output. Further, the flip-flop 32 divides the VCO CLK shown in FIG. 4 (b) by 2 to output Q signal having the waveform shown in FIG. 4 (d) and Q bar output having the waveform shown in FIG. 4 (e). Is output. The flip-flop 33 outputs the signal having the waveform shown in FIG.
The pulse signal shown in (c) is taken in and the signal having the waveform shown in FIG. 4 (f) is output. Then, the ExOR gate 34
Outputs the phase comparison output shown in FIG. 4 (g) by taking the exclusive OR of the signals shown in FIG. 4 (d) and FIG. 4 (f).

[0010]

In the conventional phase comparison circuit, the output of the edge detection circuit 31 is, as shown in FIG. 4C, when the input CMI code is "00" and "11". , The cycle is half that of the CMI code “01”. Therefore, the flip-flop 33 reads only “1” of the VCO CLK divided by 2,
The output of the flip-flop 33 is continuously "1". That is, the phase information of the CMI code included in the signal of FIG. 4 (c) is partially lost in the signal of FIG. 4 (f).
As a result, inversion of the Q output of the flip-flop 32 appears in the output of the ExOR gate 34, and the CMI code and VC
The information indicating the phase difference of O CLK is not included. (In the case of the signal shown in FIG. 4 (g), the hatched pulse contains information indicating the phase difference between the CMI code and VCO CLK.) In a PLL employing such a conventional phase comparison circuit, The input CMI code is "0
There is a problem in that phase synchronization cannot be achieved when 0 and 11 and jitter occurs, and when "00" and "11" continue, synchronization is lost. Provided is a phase comparator circuit that outputs phase information corresponding to all the changing points of the CMI code even if the CMI code is a series of "00" and "11". The purpose is to provide.

[0011]

According to the present invention, in a phase comparison circuit for comparing the phases of the input CMI code and the clock signal from the voltage controlled oscillator, the CMI code is applied to the D terminal and the CMI code is applied to the C terminal. An exclusive OR that negates the exclusive OR of the flip-flop to which the clock signal is input, the delay circuit that delays the clock signal, and the Q output of the flip-flop and the delayed clock signal from the delay circuit. A phase comparison circuit is obtained which has a NOR gate and an exclusive OR gate which takes the exclusive OR of the CMI code and the output of the exclusive NOR gate to obtain a phase comparison output.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The phase comparison circuit of the present embodiment includes a flip-flop 11 and a delay circuit 1.
2, exclusive logic NOR gate (ExNOR gate) 1
3, and exclusive OR gate (ExOR gate) 14
have.

The flip-flop 11 has a CMI at the D terminal.
The reference numeral is a clock signal (VCO CLK) from a VCO (not shown) input to the C terminal. The Q output of the flip-flop 11 is connected to one input end of the ExNOR gate 13. The delay circuit 12 includes a VCO
CLK is input, and its output is connected to the other input end of the ExNOR gate 13. The COR code and the output of the ExNOR gate 13 are input to the ExOR gate 14, and the output becomes the phase comparison output.

The operation of this phase comparison circuit will be described below with reference to FIGS. 1 and 2. The input CMI code is “01”, “01”, “0” as shown in FIG.
0 "and" 11 "are continuous signals.
As shown in FIG. 2B, it is assumed that the falling edge of O CLK coincides with the change point of the CMI code.

The delay circuit 12 divides the VCO CLK by 1/4.
The delayed VCO C shown in FIG.
LK is output. In addition, the flip-flop 11 is VC
The CMI code is read according to OCLK, and the Q output is
The signal having the waveform shown in FIG. 2D is output. The ExNOR gate 13 outputs the output of the delay circuit 12 and the flip-flop 1
When the level of the output of 1 coincides with "1", and when they do not coincide with each other, "0" is output. Therefore, the ExNOR gate 13
The waveform of the output signal is as shown in FIG.

Here, the output signal of the delay circuit 12 is VC
It contains the phase information of O CLK. Further, since the output signal of the flip-flop 11 is output in synchronization with VCO CLK, it includes the phase information of VCO CLK and CM
The phase information of the I code is lost. Therefore, the delay circuit 1
2 and ExN obtained from the output of the flip-flop 11
The output signal of the OR gate 13 will only contain the phase information of the VCO CLK.

The ExOR gate 14 has a CMI code and Ex.
Exclusive-OR with the output signal of the NOR gate 13,
The phase comparison signal shown in FIG. 2 (f) is output. In this way, when the exclusive OR of the output signal of the ExNOR gate 13 including only the phase information of the VCO CLK and the CMI code is taken, the pulses (hatched pulses) corresponding to all the changing points of the CMI code are represented. Be seen. This pulse contains information on the phase difference between the CMI code and VCOCLK, and the phase difference is expressed as a pulse width. That is, if the CMI code is delayed with respect to VCO CLK, the pulse width is narrowed, and if the CMI code is advanced with respect to VCO CLK, the pulse width is widened to represent a phase difference.

As described above, in the phase comparison circuit of this embodiment, an output signal representing the phase difference from VCO CLK can be obtained even with CMI codes in which "00" and "11" are consecutive. Therefore, in a PLL using this phase comparison circuit, stable operation can be obtained without the occurrence of jitter or loss of synchronization.

[0019]

According to the present invention, "00" and "11"
Even if the CMI code is continuous, a phase comparison circuit that outputs the phase information corresponding to all the change points of the CMI code can be obtained. Further, according to the present invention, it is possible to obtain a PLL without occurrence of jitter and loss of synchronization.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram of an output signal of each part of the phase comparison circuit of FIG.

FIG. 3 is a circuit diagram of a conventional phase comparison circuit.

4 is a waveform diagram of an output signal of each part of the phase comparison circuit of FIG.

[Explanation of symbols]

 11 flip-flop 12 delay circuit 13 exclusive-logical NOR gate 14 exclusive-logical OR gate 31 edge detection circuit 32 flip-flop 33 flip-flop 34 exclusive-logical OR gate

Claims (2)

(57) [Claims] 1. A phase comparison circuit for comparing the phases of an input CMI code and a clock signal from a voltage controlled oscillator, wherein a flip-flop in which the CMI code is input to a D terminal and the clock signal is input to a C terminal. And a delay circuit for delaying the clock signal by 1/4 cycle, and an exclusive NOR for inverting the exclusive OR of the Q output of the flip-flop and the delayed clock signal from the delay circuit.
A phase comparison circuit comprising: a gate; and an exclusive OR gate that takes an exclusive OR of the CMI code and the output of the exclusive NOR gate to obtain a phase comparison output. 2. A phase comparison circuit that compares the phases of a CMI code and a clock signal and outputs a phase comparison signal; a loop filter that filters the phase comparison signal and outputs a filtered phase comparison signal; And a voltage controlled oscillator for generating a clock signal and changing the frequency of the clock signal based on the filtered phase comparison signal.
In which the CMI code is input to the D terminal and the clock signal is input to the C terminal, a delay circuit for delaying the clock signal by 1/4 cycle, a Q output of the flip-flop and the delay circuit. Exclusive NO which negates exclusive OR with the delayed clock signal
A PLL having an R gate and an exclusive OR gate that takes the exclusive OR of the CMI code and the output of the exclusive NOR gate to obtain the phase comparison signal.