JPS5915218B2 - phase lock loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked loop circuit that operates accurately even using very fast pulses.

The phase-locked loop circuit has the structure shown in FIG. 1 in principle.

The input signal IN is passed through the I/N frequency divider to the phase comparator PC as clock 1, and the output of the voltage controlled oscillator VCO is passed through the frequency conversion control unit PCT and the I/N frequency divider to the phase comparator PC as clock 2. is applied to

The output of the phase comparator PC passes through a low-pass filter LPF to VC.
In order to control O, the CO output is a signal whose phase is synchronized with the input signal.

The conventional phase comparator PC uses a set/reset type flip-flop 5R-FF shown in FIG.

This operation is performed by clock 1 (corresponding to the N terminal in Figure 1) of the flip-flop 5R as shown in the time chart in Figure 2.
-FF is set, and an output 0UT (corresponding to the C terminal in Figure 1) reset by clock 2 (corresponding to the C terminal in Figure 1) is obtained, which becomes the output of the low-pass filter LPF (corresponding to the first diagram terminal).

In a circuit using high-speed pulses, the usable range becomes narrow in the phase comparison characteristic of the sawtooth wave shown as the output in the first diagram.

This is because a predetermined time is required to set and reset the flip-flop, and the middle part of the sawtooth waveform becomes extremely narrow, causing inconvenience in operation.

If the interval between each clock signal is Tw, and the set or reset operation time is tw, then the time during which the phase comparison range decreases φ
1. becomes φ...=2gX2π.

For example, in the case of a 200 Mbit signal, the pulse repetition period is 5 nanoseconds, and it takes 2 nanoseconds each to stably set and reset a flip-flop, so let it be φ1.
This results in a value of 4 nanoseconds, and the remaining time is 1 nanosecond.

Therefore, a phase comparator using a flip-flop that operates at the rising edge of a clock signal and performs a reset operation is shown in FIG.

In FIG. 3, FF1. FF2 is a flip-flop,
FF2 is reset by the Q pulse of FF1 obtained when the frequency of the clock signal is divided by two in FF2 and FF1 is set by its inverted output.

In this case, the set side of FF2 does not affect the phase comparison range, but the reset side does, and as a result, the time decreases according to the same formula as above. For φr2, only w φr2=2π×− w can be obtained.

In the numerical example given above, φ,2 is nanoseconds.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked loop circuit which can overcome the above-mentioned drawbacks and can operate with sufficient accuracy even when a high-speed pulse is used as a clock signal.

Embodiments of the present invention shown in the drawings will be described below.

FIG. 4 is a first embodiment of the present invention and its operation time chart, and the same reference numerals as in FIGS. 2 and 3 indicate the same parts.

Both FF3 and FF4 use delay type flip-flops, DL indicates a delay line, and EXOR indicates an exclusive OR circuit.

In FF4, the clock 2 is frequency-divided by 2 to obtain the FF4Q signal, and the FF4Q signal is applied to FF3, and retiming is applied to the FF3 to obtain the FF3Q signal.

Therefore, the output OUT signal has a waveform calculated in the EXOR circuit.

Although not shown in the time chart, there is a slight operational delay when FF3 operates, so the delay line DL is inserted to delay the FF4Q signal by that time.

If the phase of the clock 2 signal changes, the duty ratio of the output OUT signal changes accordingly.

If the lock 1 signal is disconnected again, the PLL circuit's CO output becomes the center frequency and freely oscillates.

In FIG. 4, terminal C of FF3 corresponds to a conventional reset terminal, and terminal C of FF4 corresponds to a conventional set terminal.

Since both FF3 and FF4 operate at the rising point of the clock signal and do not use a set terminal or a reset terminal, there is no range in which the phase comparison operation in the conventional circuit is impossible.

FIG. 5 is a block diagram showing the second embodiment of the present invention, in which Q of FF4 is shown.
The signal is retimed by FF3.

Therefore, the slope of the phase comparison characteristic is opposite to that in Figure 4, and the FF
Terminal C of FF3 corresponds to a conventional set terminal, and terminal C of FF4 corresponds to a reset terminal.

Other operations are the same as in FIG. 4.

In this way, according to the present invention, since flip-flops that operate only on the rising and falling edges of the clock pulse are used in combination, there is no portion that causes loss in the phase comparison range, and extremely high-speed operation is possible.

However, it can also be used effectively in circuits used for ultra-high-speed PCM communication.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle configuration of a phase-locked loop circuit.
2 and 3 are diagrams showing conventional examples of the phase comparator shown in FIG. 1, and FIGS. 4 and 5 are diagrams showing the configuration and timing chart of the first embodiment of the present invention. IN...Input signal, PC...Phase comparator, ■CO...Voltage controlled oscillator, LPF...
...Low pass filter, 5R-FF, FF1, FF
2, FF3. FF4...Flip-flop, DL...
・Delay line, EXOR...Exclusive OR circuit.

Claims (1)

[Claims] 1. In a phase-locked loop circuit that compares the phase of the output of a voltage-controlled oscillator with an input signal and follows the phase of the input signal by feeding back to the voltage-controlled oscillator, the following phase comparator is used. A phase-locked loop circuit having the following configuration. (a) a first flip-flop operating at the rising or falling point of the pulse to be divided by two; (b) using the first flip-flop output to retime the input signal at the rising or falling point of the pulse; (c) delay means for delaying the output of the first flip-flop by the time of the second flip-flop timing; Exclusive OR circuit to which the output is applied.