JPS5592042A - Phase lock loop circuit - Google Patents
Phase lock loop circuitInfo
- Publication number
- JPS5592042A JPS5592042A JP16524178A JP16524178A JPS5592042A JP S5592042 A JPS5592042 A JP S5592042A JP 16524178 A JP16524178 A JP 16524178A JP 16524178 A JP16524178 A JP 16524178A JP S5592042 A JPS5592042 A JP S5592042A
- Authority
- JP
- Japan
- Prior art keywords
- operated
- comparator
- lock loop
- phase lock
- rise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Abstract
PURPOSE:To make it possible to operate a phase lock loop in a very high speed by combining and using FFs which are operated only by rise and break of clock pulses. CONSTITUTION:Input signal IN is subjected to 1/N frequency division and is sent to phase comparator PC, and the output of voltage control oscillator VCO is applied to comparator PC through frequency converter PCT and a 1/N frequency divider. The output of comparator PC is used for frequency control of oscillator VCO through an LPF. In this case, in comparator PC, FF3 is operated at rise and break points of a pulse to be divided by ''2'', and FF4 uses the output of FF4 to be operated at the rise or break point of the pulse, and outputs of FF3 and FF4 are given to exclusive OR circuit EXEOR. As a result, the phase lock loop can be operated in a very high speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53165241A JPS5915218B2 (en) | 1978-12-31 | 1978-12-31 | phase lock loop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53165241A JPS5915218B2 (en) | 1978-12-31 | 1978-12-31 | phase lock loop circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5592042A true JPS5592042A (en) | 1980-07-12 |
JPS5915218B2 JPS5915218B2 (en) | 1984-04-07 |
Family
ID=15808546
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53165241A Expired JPS5915218B2 (en) | 1978-12-31 | 1978-12-31 | phase lock loop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5915218B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60256227A (en) * | 1984-05-22 | 1985-12-17 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Electric circuit device having phase control circuit |
US6194916B1 (en) | 1997-01-17 | 2001-02-27 | Fujitsu Limited | Phase comparator circuit for high speed signals in delay locked loop circuit |
-
1978
- 1978-12-31 JP JP53165241A patent/JPS5915218B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60256227A (en) * | 1984-05-22 | 1985-12-17 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Electric circuit device having phase control circuit |
JPH0628337B2 (en) * | 1984-05-22 | 1994-04-13 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Electrical circuit device with phase control circuit |
US6194916B1 (en) | 1997-01-17 | 2001-02-27 | Fujitsu Limited | Phase comparator circuit for high speed signals in delay locked loop circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5915218B2 (en) | 1984-04-07 |
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