JPS5687924A - Phase comparison circuit - Google Patents
Phase comparison circuitInfo
- Publication number
- JPS5687924A JPS5687924A JP16498479A JP16498479A JPS5687924A JP S5687924 A JPS5687924 A JP S5687924A JP 16498479 A JP16498479 A JP 16498479A JP 16498479 A JP16498479 A JP 16498479A JP S5687924 A JPS5687924 A JP S5687924A
- Authority
- JP
- Japan
- Prior art keywords
- input
- flop
- flip
- output
- phase comparison
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
- G01R25/005—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To enable to make phase comparison in high speed, by exclusive logical sum between the output sampling the input signal and the original input signal. CONSTITUTION:The output 2 from a voltage controlled oscillator 6 is frequency- divided at a flip-flop 13. The output frequency-divided is input to the terminal D of a flip-flop 14. The input clock 1 is input to the terminal C of the flip-flop 14. The input signal at the terminal D is sampled at the leading of the input clock. The Q and Q' outputs of the flip-flop 13 and the flip-flop 14 are input to an exclusive logical sum 15 to obtain the phase comparison output. Since the phase comparison output is obtained at the leading change point of the output 2 and the clock 1 of the voltage controlled oscillator 6, the operating range in high speed can be made in any of the clock 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16498479A JPS5687924A (en) | 1979-12-19 | 1979-12-19 | Phase comparison circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16498479A JPS5687924A (en) | 1979-12-19 | 1979-12-19 | Phase comparison circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5687924A true JPS5687924A (en) | 1981-07-17 |
JPS6364086B2 JPS6364086B2 (en) | 1988-12-09 |
Family
ID=15803616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16498479A Granted JPS5687924A (en) | 1979-12-19 | 1979-12-19 | Phase comparison circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5687924A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6411412A (en) * | 1987-07-03 | 1989-01-17 | Fujitsu Ltd | Phase comparing circuit |
JP2008000023A (en) * | 2006-06-20 | 2008-01-10 | Yanmar Co Ltd | Combine harvester |
-
1979
- 1979-12-19 JP JP16498479A patent/JPS5687924A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6411412A (en) * | 1987-07-03 | 1989-01-17 | Fujitsu Ltd | Phase comparing circuit |
JP2008000023A (en) * | 2006-06-20 | 2008-01-10 | Yanmar Co Ltd | Combine harvester |
Also Published As
Publication number | Publication date |
---|---|
JPS6364086B2 (en) | 1988-12-09 |
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