JPS54141507A - Phase synchronism circuit - Google Patents

Phase synchronism circuit

Info

Publication number
JPS54141507A
JPS54141507A JP4949778A JP4949778A JPS54141507A JP S54141507 A JPS54141507 A JP S54141507A JP 4949778 A JP4949778 A JP 4949778A JP 4949778 A JP4949778 A JP 4949778A JP S54141507 A JPS54141507 A JP S54141507A
Authority
JP
Japan
Prior art keywords
phase
synchronism
output
comparator
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4949778A
Other languages
Japanese (ja)
Other versions
JPS6058620B2 (en
Inventor
Mikio Kiyono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP53049497A priority Critical patent/JPS6058620B2/en
Publication of JPS54141507A publication Critical patent/JPS54141507A/en
Publication of JPS6058620B2 publication Critical patent/JPS6058620B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To execute the phase synchronism having wider frequency drawing range, by not giving the output pulse of the voltage controlled oscillator to the phase synchronism comparator when the input pulse is not given in the phase synchronism circuit including the phase frequency comparator. CONSTITUTION:Each pluse width of the input pulse train is delayed 22 and expanded for the half of the pulse synchronism, it is fed to the phase frequency comparison circuit 25, the unnecessary components of the output of the circuit 25 are rejected with LPF 26 and are fed to the voltage control oscillator 27 to control the oscillation frequency. The output of the oscillator 27 is differentated 28 and is given to FF23 as the reset signal, and FF23 is set with the input signal 20 and the output signals of FF21 and 23 are compared at the comparator 25. Thus, the part not having pulses for the input pluse train is not made for phase comparison, clock signal is picked up without causing unnecessary phase error signal, and the phase synchronism having wider frequency drawing range can be made.
JP53049497A 1978-04-25 1978-04-25 phase locked circuit Expired JPS6058620B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53049497A JPS6058620B2 (en) 1978-04-25 1978-04-25 phase locked circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53049497A JPS6058620B2 (en) 1978-04-25 1978-04-25 phase locked circuit

Publications (2)

Publication Number Publication Date
JPS54141507A true JPS54141507A (en) 1979-11-02
JPS6058620B2 JPS6058620B2 (en) 1985-12-20

Family

ID=12832773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53049497A Expired JPS6058620B2 (en) 1978-04-25 1978-04-25 phase locked circuit

Country Status (1)

Country Link
JP (1) JPS6058620B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0084675A2 (en) * 1982-01-27 1983-08-03 ANT Nachrichtentechnik GmbH Method and device for the clock synchronization at the receiving side of a plesiochronous transmission system
JPS58218015A (en) * 1982-05-31 1983-12-19 Nec Home Electronics Ltd Sampling clock generating circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0339509A (en) * 1989-07-07 1991-02-20 Yoshimasa Imabayashi Guard rail
JPH07324315A (en) * 1994-05-31 1995-12-12 Yoshida:Goushi High strength guard fence

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0084675A2 (en) * 1982-01-27 1983-08-03 ANT Nachrichtentechnik GmbH Method and device for the clock synchronization at the receiving side of a plesiochronous transmission system
JPS58218015A (en) * 1982-05-31 1983-12-19 Nec Home Electronics Ltd Sampling clock generating circuit

Also Published As

Publication number Publication date
JPS6058620B2 (en) 1985-12-20

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