JPS55133137A - Phase synchronous oscillation circuit - Google Patents
Phase synchronous oscillation circuitInfo
- Publication number
- JPS55133137A JPS55133137A JP2587179A JP2587179A JPS55133137A JP S55133137 A JPS55133137 A JP S55133137A JP 2587179 A JP2587179 A JP 2587179A JP 2587179 A JP2587179 A JP 2587179A JP S55133137 A JPS55133137 A JP S55133137A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- signal
- error signal
- output
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 title abstract 2
- 230000001360 synchronised effect Effects 0.000 title abstract 2
- 238000006243 chemical reaction Methods 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To obtain the carrier having the phase in response to AM-PM conversion, in the phase synchronous oscillation circuit used for carrier reproducing unit for the signal subjected to AM-PM conversion. CONSTITUTION:Taking the phase of reference signal as phi1, the phase comparator 202 produces the error signal f1. The error signal f1 is held at the hold circuit 206 with the control signal C1. Next, if the phase of reference signal is phi2, the phase comparator 204 produces the error signal f2. The error signal f2 is held at the hold circuit 207 with the control signal C2. The output signal of the holding circuits 206, 207 is fed to VCO 201 via the adder 210 and low pass filter 211, and it is controlled that the frequency and phase of the phase reference signal can be equal. The output of the holding circuits 206, 207 is inputted to the error signal comparator 209, and the output of the result of comparison controls the phase shifter 203 so that the difference of error signal can be made smaller.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2587179A JPS55133137A (en) | 1979-03-06 | 1979-03-06 | Phase synchronous oscillation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2587179A JPS55133137A (en) | 1979-03-06 | 1979-03-06 | Phase synchronous oscillation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55133137A true JPS55133137A (en) | 1980-10-16 |
JPS6316936B2 JPS6316936B2 (en) | 1988-04-12 |
Family
ID=12177843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2587179A Granted JPS55133137A (en) | 1979-03-06 | 1979-03-06 | Phase synchronous oscillation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55133137A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0108358A2 (en) * | 1982-10-30 | 1984-05-16 | Nec Corporation | Phase demodulator |
-
1979
- 1979-03-06 JP JP2587179A patent/JPS55133137A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0108358A2 (en) * | 1982-10-30 | 1984-05-16 | Nec Corporation | Phase demodulator |
Also Published As
Publication number | Publication date |
---|---|
JPS6316936B2 (en) | 1988-04-12 |
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