GB1464842A - Resettable toggle flip-flop - Google Patents

Abstract

1464842 Bi-stable circuits HUGHES AIRCRAFT CO 9 Jan 1975 [10 Jan 1974] 955/75 Heading H3T A bi-stable circuit comprises a gate 20, a first inverter 22, a switch 26 and two further inverters 28, 30 connected in cascade, a switch 16 connected from the output of inverter 22 to one input of gate 20, or switch 32 connected from the output of inverter 30 to the input of inverter 28 and a switch 24 connected from the output of inverter 22 to one input of the gate 20, the other input 18, of the gate being for resetting the circuit. Switches 24, 32 are controlled by clock signal # and switches 16, 26 by complementary signal #, the two complementary signals constituting the input to the circuit. Assume initially that node 3 is in the "1" state, then when # is at its "1" level the signal at node 3 is inverted by inverter 28 and applied via switch 24 to produce a "0" at nodes 1 and 2. When the clock changes to #=1 gate 24 closes and gate 26 opens to transfer the "0" at node 2 to node 3. When the clock reverts to #=1 gate 26 closes and gate 24 opens to transfer the "0" at node 3 via inverter 28 to produce a "1" at nodes 1 and 2. The next #=1 phase of the clock again closes gate 26 to transfer the "1" at node 2 to node 3 and the cycle recommences with the next #=1 phase. The circuit thus constitutes a divide-bytwo circuit. The gate, inverters and switches may all be realized as CMOS elements, Fig. 3 (not Fig. 4). The state of the circuit may be read out by a further switch 14 controlled by an address signal DR.