JPS5742230A - Clock switching device - Google Patents

Clock switching device

Info

Publication number
JPS5742230A
JPS5742230A JP11808180A JP11808180A JPS5742230A JP S5742230 A JPS5742230 A JP S5742230A JP 11808180 A JP11808180 A JP 11808180A JP 11808180 A JP11808180 A JP 11808180A JP S5742230 A JPS5742230 A JP S5742230A
Authority
JP
Japan
Prior art keywords
switching
signal
clock
state
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11808180A
Other languages
Japanese (ja)
Inventor
Kunio Nakase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11808180A priority Critical patent/JPS5742230A/en
Publication of JPS5742230A publication Critical patent/JPS5742230A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Abstract

PURPOSE:To keep stable operation for logical circuit groups, by switching the output of a clock oscillation circuit, when the distortion of phase is absent at the output before and after the clock switching of the clock oscillation circuit. CONSTITUTION:Normal signals A, B are compared at a normal state, and when they coincide, the state is displayed to a flip-flop 14 with a signal H. When the switching of clock is indicated with a switching signal C, the flip-flop 14 samples the state of the signal H with a timing signal G and it is set to 1 when the phase is in coincidence and if not, it is set to 0. When set to 1, a switching circuit 3 selects an output signal B of a clock oscillation circuit 2 and the clock switching operation is finished by applying the signal D to a logical circuit group 5. Thus, the operation of the logical circuit group 5 is not interrupted.
JP11808180A 1980-08-26 1980-08-26 Clock switching device Pending JPS5742230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11808180A JPS5742230A (en) 1980-08-26 1980-08-26 Clock switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11808180A JPS5742230A (en) 1980-08-26 1980-08-26 Clock switching device

Publications (1)

Publication Number Publication Date
JPS5742230A true JPS5742230A (en) 1982-03-09

Family

ID=14727517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11808180A Pending JPS5742230A (en) 1980-08-26 1980-08-26 Clock switching device

Country Status (1)

Country Link
JP (1) JPS5742230A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135226A (en) * 1987-11-20 1989-05-26 Nec Corp Switching circuit
JPH04136226U (en) * 1991-06-13 1992-12-18 了 境野 Abdominal acupressure device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135226A (en) * 1987-11-20 1989-05-26 Nec Corp Switching circuit
JPH04136226U (en) * 1991-06-13 1992-12-18 了 境野 Abdominal acupressure device

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