JPS558166A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS558166A
JPS558166A JP8134278A JP8134278A JPS558166A JP S558166 A JPS558166 A JP S558166A JP 8134278 A JP8134278 A JP 8134278A JP 8134278 A JP8134278 A JP 8134278A JP S558166 A JPS558166 A JP S558166A
Authority
JP
Japan
Prior art keywords
clock pulse
data signal
circuit
constitution
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8134278A
Other languages
Japanese (ja)
Inventor
Satoshi Ishikawa
Katsuzo Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP8134278A priority Critical patent/JPS558166A/en
Publication of JPS558166A publication Critical patent/JPS558166A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Abstract

PURPOSE:To simplify the circuit constitution by securing the exclusive logic sum for the data signal and the clock pulse. CONSTITUTION:Data signal A within shift register 1 which is read out by clock pulse B synchronized with the transmission request given from clock oscillator 2 plus clock pulse B sent from oscillator 2 are applied to exclusive logic circuit 3 through delay circuit 5. Thus the phase modulation is given to data signal A. Then the longest pulse duration gamma of modulation signal C is set under repetitive cycle T of transmission clock pulse B to be transmitted. In such way, the circuit constitution can be simplified greatly compared with the conventional one with excellent performance secured in the practical use.
JP8134278A 1978-07-04 1978-07-04 Data transmission system Pending JPS558166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8134278A JPS558166A (en) 1978-07-04 1978-07-04 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8134278A JPS558166A (en) 1978-07-04 1978-07-04 Data transmission system

Publications (1)

Publication Number Publication Date
JPS558166A true JPS558166A (en) 1980-01-21

Family

ID=13743686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8134278A Pending JPS558166A (en) 1978-07-04 1978-07-04 Data transmission system

Country Status (1)

Country Link
JP (1) JPS558166A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446521A (en) * 1980-03-28 1984-05-01 Tokyo Shibaura Denki Kabushiki Kaisha Image reconstruction apparatus and process
JP2015000249A (en) * 2013-06-17 2015-01-05 株式会社ユニバーサルエンターテインメント Game machine
JP2015000252A (en) * 2013-06-17 2015-01-05 株式会社ユニバーサルエンターテインメント Game machine
JP2015000253A (en) * 2013-06-17 2015-01-05 株式会社ユニバーサルエンターテインメント Game machine
JP2016193360A (en) * 2016-08-25 2016-11-17 株式会社ユニバーサルエンターテインメント Game machine
JP2016193361A (en) * 2016-08-25 2016-11-17 株式会社ユニバーサルエンターテインメント Game machine

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446521A (en) * 1980-03-28 1984-05-01 Tokyo Shibaura Denki Kabushiki Kaisha Image reconstruction apparatus and process
JP2015000249A (en) * 2013-06-17 2015-01-05 株式会社ユニバーサルエンターテインメント Game machine
JP2015000252A (en) * 2013-06-17 2015-01-05 株式会社ユニバーサルエンターテインメント Game machine
JP2015000253A (en) * 2013-06-17 2015-01-05 株式会社ユニバーサルエンターテインメント Game machine
JP2016193360A (en) * 2016-08-25 2016-11-17 株式会社ユニバーサルエンターテインメント Game machine
JP2016193361A (en) * 2016-08-25 2016-11-17 株式会社ユニバーサルエンターテインメント Game machine

Similar Documents

Publication Publication Date Title
JPS558166A (en) Data transmission system
JPS5799062A (en) Reception circuit for data transmission
JPS53139456A (en) Clock driver circuit
SU702535A1 (en) Device for clocking start-stop systems for transmission of descrete data
JPS5496311A (en) Data serial transmission system
JPS57125425A (en) System for information transmission
JPS5294110A (en) Phase synchronizer using modified fm method
JPS53117947A (en) Parallel-serial conversion device
JPS5413708A (en) Code conversion system
JPS5354935A (en) Information converting device
JPS5742230A (en) Clock switching device
SU1058021A1 (en) Frequency multiplier
JPS5399860A (en) Phase shifter
JPS54122944A (en) Logic circuit
JPS53121533A (en) Multiplier circuit system
JPS5541037A (en) Data sampling system of video display unit
JPS5355920A (en) Answer signal generator
JPS5538714A (en) Data transmission system
JPS5781760A (en) Highway test device
JPS55159660A (en) Code conversion circuit
JPS56169461A (en) Symmetrical wave generating circuit
JPS5394837A (en) Selector circuit
JPS5414145A (en) Polygonal line decoder of digital type
JPS5387617A (en) Digital signal regnerative repeating unit
JPS5760433A (en) Word conversion system