JPS56169461A - Symmetrical wave generating circuit - Google Patents
Symmetrical wave generating circuitInfo
- Publication number
- JPS56169461A JPS56169461A JP7333580A JP7333580A JPS56169461A JP S56169461 A JPS56169461 A JP S56169461A JP 7333580 A JP7333580 A JP 7333580A JP 7333580 A JP7333580 A JP 7333580A JP S56169461 A JPS56169461 A JP S56169461A
- Authority
- JP
- Japan
- Prior art keywords
- output
- terminal
- inputted
- gate
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
Abstract
PURPOSE:To output an input data as converted to a symmetrical waveform suitably with a simple constitution, by providing a D flip-flop which takes an NOR output between the output of a shift register and the output of a basic oscillator as a reset input. CONSTITUTION:An output (a) of a basic oscillator 1 is inputted to a clock terminal CL of a D FF3 and to one terminal of a NOR gate 4. A data (c) to be transmitted is sequentially inputted to another terminal of the NOR gate 4 from a shift register 2. Further, the output of the NOR gate 4 is inputted to a reset terminal R of the D FF3, and a Q output (b) of the D FF3 is inputted to a clock terminal CL of the shift register 2 and also inputted to a terminal D of the D FF3 via an inverter 5. The signal (b) of this Q output terminal is outputted as a symmetrical wave signal from an output terminal 6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7333580A JPS56169461A (en) | 1980-05-31 | 1980-05-31 | Symmetrical wave generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7333580A JPS56169461A (en) | 1980-05-31 | 1980-05-31 | Symmetrical wave generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56169461A true JPS56169461A (en) | 1981-12-26 |
Family
ID=13515186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7333580A Pending JPS56169461A (en) | 1980-05-31 | 1980-05-31 | Symmetrical wave generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56169461A (en) |
-
1980
- 1980-05-31 JP JP7333580A patent/JPS56169461A/en active Pending
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