JPS5498556A - Frequency multplication circuit - Google Patents
Frequency multplication circuitInfo
- Publication number
- JPS5498556A JPS5498556A JP522178A JP522178A JPS5498556A JP S5498556 A JPS5498556 A JP S5498556A JP 522178 A JP522178 A JP 522178A JP 522178 A JP522178 A JP 522178A JP S5498556 A JPS5498556 A JP S5498556A
- Authority
- JP
- Japan
- Prior art keywords
- output
- changed
- signal
- circuit
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE: To make unnecessary the wave shape, by multiplying frequency through the simple combination of exclusive logical sum circuit and FF circuit.
CONSTITUTION: When the inputs a,e of EX-OR 7 are "0", the output f is "0", and when the signal a changes to "1", f is changed to "1". The signal f drives FF12 as clock pulse, and signals a,e are simultaneously changed to "1" and the output e of FF holds "1". When the input a is changed to "0", f is changed to "1". The signal e is "0" with this timing and the output f is changed to "0". When the inputs a and g are "0" and "1", the output h of the gate 7 is "1", and when the input a changes to "1", the output h is "0" and FF output g keeps "1". When the signal a changes to "0", the output h is changed to "1" and the FF output g is changed to "0" and the signal h is changed to "0" and held at "0". Thus, the pulse width of the waveform h at the terminal 11 and the pulse distance are kept constant and perfect waveform and frequency multiplication can be made by combinating a plurality of EX-OR and FF.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP522178A JPS5498556A (en) | 1978-01-23 | 1978-01-23 | Frequency multplication circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP522178A JPS5498556A (en) | 1978-01-23 | 1978-01-23 | Frequency multplication circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5498556A true JPS5498556A (en) | 1979-08-03 |
Family
ID=11605132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP522178A Pending JPS5498556A (en) | 1978-01-23 | 1978-01-23 | Frequency multplication circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5498556A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5010561A (en) * | 1988-05-23 | 1991-04-23 | Advanced Micro Devices, Inc. | Circuit for multiplying the frequency in one series of input pulses |
US5111066A (en) * | 1990-02-13 | 1992-05-05 | Sgs-Thompson Microelectronics S.A. | Clock frequency doubler |
-
1978
- 1978-01-23 JP JP522178A patent/JPS5498556A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5010561A (en) * | 1988-05-23 | 1991-04-23 | Advanced Micro Devices, Inc. | Circuit for multiplying the frequency in one series of input pulses |
US5111066A (en) * | 1990-02-13 | 1992-05-05 | Sgs-Thompson Microelectronics S.A. | Clock frequency doubler |
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