JPS5761326A - Double frequency generating circuit - Google Patents

Double frequency generating circuit

Info

Publication number
JPS5761326A
JPS5761326A JP13652280A JP13652280A JPS5761326A JP S5761326 A JPS5761326 A JP S5761326A JP 13652280 A JP13652280 A JP 13652280A JP 13652280 A JP13652280 A JP 13652280A JP S5761326 A JPS5761326 A JP S5761326A
Authority
JP
Japan
Prior art keywords
signal
output signals
stages
generating circuit
double frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13652280A
Other languages
Japanese (ja)
Inventor
Kiyoshi Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13652280A priority Critical patent/JPS5761326A/en
Publication of JPS5761326A publication Critical patent/JPS5761326A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003Changing the DC level

Abstract

PURPOSE:To obtain a signal whose frequency is double as high as that of an input signal by using an N-stage shift register which shifts the input signal and a logical circuit which inputs output signals from two optional stages of the N stages and performs exclusive OR. CONSTITUTION:A clock signal (b) whose frequency is much higher than that of an input signal (a) is supplied from a clock signal input terminal 2 to an N-stage shift register 4. An exclusive OR circuit 5 exclusively ORs output signals (c), (d) and (e) of the resistor 4 when N=1 or two optional output signals among output signals of the N stages when N>=2, thereby sending an output signal (f) to an output signal terminal 3. Consequently, the signal (f) has a frequency double as high as that of the signal (a).
JP13652280A 1980-09-30 1980-09-30 Double frequency generating circuit Pending JPS5761326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13652280A JPS5761326A (en) 1980-09-30 1980-09-30 Double frequency generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13652280A JPS5761326A (en) 1980-09-30 1980-09-30 Double frequency generating circuit

Publications (1)

Publication Number Publication Date
JPS5761326A true JPS5761326A (en) 1982-04-13

Family

ID=15177139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13652280A Pending JPS5761326A (en) 1980-09-30 1980-09-30 Double frequency generating circuit

Country Status (1)

Country Link
JP (1) JPS5761326A (en)

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