JPS5718128A - Frequency dividing circuit - Google Patents

Frequency dividing circuit

Info

Publication number
JPS5718128A
JPS5718128A JP9224180A JP9224180A JPS5718128A JP S5718128 A JPS5718128 A JP S5718128A JP 9224180 A JP9224180 A JP 9224180A JP 9224180 A JP9224180 A JP 9224180A JP S5718128 A JPS5718128 A JP S5718128A
Authority
JP
Japan
Prior art keywords
signal
counter
clock
outputs
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9224180A
Other languages
Japanese (ja)
Other versions
JPS6328368B2 (en
Inventor
Kiyoshi Mochizuki
Toru Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP9224180A priority Critical patent/JPS5718128A/en
Publication of JPS5718128A publication Critical patent/JPS5718128A/en
Publication of JPS6328368B2 publication Critical patent/JPS6328368B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a signal which has divided a clock signal into 2/integer N(N>= 3), by providing a logical circuit for coupling logically the first counter and the second counter, and also carrier signals of both the counters. CONSTITUTION:A clock pulse signal (fin) from a clock signal source PG is applied to a clock input terminal CKA of the first counter CNTA, and also is applied to a clock input terminal CKB of the second counter CNTB through an inverter INV. The first counter counts a clock pulse signal, outputs the first carrier signal from a ripple carry output at every full count, and outputs this output as (fout) through an OR circuit OR. Also, in this case, the first preset signal which is a data DA is set so as to count from this value up to a full count value, and it is repeated.
JP9224180A 1980-07-08 1980-07-08 Frequency dividing circuit Granted JPS5718128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9224180A JPS5718128A (en) 1980-07-08 1980-07-08 Frequency dividing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9224180A JPS5718128A (en) 1980-07-08 1980-07-08 Frequency dividing circuit

Publications (2)

Publication Number Publication Date
JPS5718128A true JPS5718128A (en) 1982-01-29
JPS6328368B2 JPS6328368B2 (en) 1988-06-08

Family

ID=14048932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9224180A Granted JPS5718128A (en) 1980-07-08 1980-07-08 Frequency dividing circuit

Country Status (1)

Country Link
JP (1) JPS5718128A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59125039A (en) * 1982-12-30 1984-07-19 Yamamoto Suiatsu Kogyosho:Kk Composite crushing testing method
JPS60121337U (en) * 1984-01-26 1985-08-16 クラリオン株式会社 Frequency divider circuit
JPS61102819A (en) * 1984-10-24 1986-05-21 Yokogawa Hokushin Electric Corp 2/3 frequency divider
US4975931A (en) * 1988-12-19 1990-12-04 Hughes Aircraft Company High speed programmable divider
US5304938A (en) * 1992-11-18 1994-04-19 Gec Plessey Semiconductors, Inc. Method and apparatus for providing a lower frequency signal with reference to a higher frequency signal
US5808494A (en) * 1994-04-01 1998-09-15 International Business Machines Corporation Apparatus and method for generating a clock in a microprocessor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59125039A (en) * 1982-12-30 1984-07-19 Yamamoto Suiatsu Kogyosho:Kk Composite crushing testing method
JPS60121337U (en) * 1984-01-26 1985-08-16 クラリオン株式会社 Frequency divider circuit
JPS61102819A (en) * 1984-10-24 1986-05-21 Yokogawa Hokushin Electric Corp 2/3 frequency divider
US4975931A (en) * 1988-12-19 1990-12-04 Hughes Aircraft Company High speed programmable divider
US5304938A (en) * 1992-11-18 1994-04-19 Gec Plessey Semiconductors, Inc. Method and apparatus for providing a lower frequency signal with reference to a higher frequency signal
US5808494A (en) * 1994-04-01 1998-09-15 International Business Machines Corporation Apparatus and method for generating a clock in a microprocessor

Also Published As

Publication number Publication date
JPS6328368B2 (en) 1988-06-08

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