SU839067A1 - Frequency divider with either integer countdown ratio - Google Patents

Description

The invention relates to a pulse technique and can be used in automation and computing, in data transmission and telegraphy techniques, in digital magnetic recording equipment and in other fields of discrete technology. A known frequency divider with any integer division factor, containing two valves and an investor, whose inputs are connected to the input bus, the output of the first valve is connected to the counting input of a binary counter, the output of the second valve is with its reset bus, the output of the meter triggers corresponding to the specified the division ratio,; is connected to the inputs of the first decoder, the control trigger, the outputs of which are connected to the control inputs of the valves, and the second decoder, the inputs of which are connected to the zero outputs of the binary triggers In this case, the output of the inverter is connected to the inputs of the decoders, the outputs of which are connected to the inputs of control trigger 1, However, with this increase in the division ratio, the decoder circuit becomes complicated, which in its implementation can be multi-stage, which reduces the reliability of the device . The purpose of the invention is to increase the reliability of the device. Dp achieve the goal in the frequency divider with any integer division factor containing valves and inverter, the inputs of which are combined and connected to the input bus, the valve outputs are connected respectively to the counting input and the reset counter of the binary counter, the output of the inverter is connected to one of the decoder inputs , the other inputs of which are connected to the parallel outputs of the binary counter, and the output

the decoder is connected to the installation input of the control trigger, the outputs of which are connected to the control inputs of the gates, the series-connected additional inverter and the NAND element are connected between the output of the first valve and the counting input of the control trigger, while the second input of the EID is connected to the bus reset binary counter.

Figure 1 shows a structural electrical frequency splitter circuit with any integer division factor; 2 shows timing diagrams explaining the principle of operation of the device.

The device contains the first valve 1, the second valve 2 and the inverter 3, the inputs of which are connected to the input bus 4, the outputs of the first valve 1 and the second valve 2 are connected respectively to the counting input and the reset bus of the binary counter 5, the output of the inverter 3 is connected to one of the decoder inputs 6, the other inputs of which are connected to the parallel input of the counter 5 corresponding to the specified division factor, and the output of the decoder 6 is connected to the setup input of the trigger trigger 7 connected by its outputs to the control inputs of the first ve tl and the second valve 2, the IS-HE 8 element and the additional inverter 9 are inserted in the divider. In this case, the input of the inverter 9 is connected to the output of the valve 1, the second input of the IS-HE element 8 is connected to the reset bus of the counter 5, which is the output 10 dev istel, and the output of the NAND 8 element is connected to the counting input of the trigger 7.

The divider works as follows.

In the description of the divider circuit, the operating signal received a positive signal (potential, impulse, voltage drop) when it implements the division factor of 11.

In the initial state, the binary counter 5 and the control trigger 7 are in the zero state, in which the control input of the first valve 1 receives a single, permitting potential, and this input. valve 2 - inhibitory potential. At the same time from the input bus 4 is binary

a sequence of pulses (figa) through the valve 1 is fed to the input of the counter 5 (fig.2b). In the interval between the 10th and 1 1st input pulses with

an inverter 3 to the input of the decoder 6 allocating 10th. From the start of counting (in accordance with the selected division factor and always less than 1) the state of counter 5, a single impulse is received, which through the decoder 6 (Fig. 2b) sets trigger 7 to unit state via the setup input S. After that the resolving potential from trigger 7

enters the control input of the second

gates 2, and at the first input of the element AND-NOT after the additional inverter

9 a positive signal continues to be present, permitting the operation of the NAND 8 element (FIG. 2 g).

The next, 1st 1st pulse, which is the output pulse of the divider through the valve 2, passes to the reset bar of the counter 5 (fig.2d), bringing it back to its original state, prohibiting further operation of the decoder 6, from the output of which the positive pulse to the trigger input 7. A reset impulse of counter 5 through the IS-NOT element in 8 inverse form (negative goes to the counting input of trigger control 7 (FIG. 2e)), changing from one back to the initial, zero state, on The divider’s next operation starts at the same time as the first input of the NAND element 8 during transients in the counter 5

(transition from one state to another) always comes from the output of the additional inverter 9 a inhibitory, negative signal that prevents the IS-HE 8 interference from passing through the second input to the non-counting input of the control trigger 7.

Claims (1)

1. USSR author's certificate No. 62A371, cl. H 03 K 23/00, 1976 (prototype).