SU402154A1 - USSR Academy of Sciences - Google Patents

Description

one

This invention relates to electrical measuring technology. The device can be used in systems with a frequency-pulse presentation of information.

A multi-input pulse counter is known, which contains a counting register, an OR circuit and triggers with coincidence circuits at zero inputs, with single trigger inputs connected to the counter inputs.

Full or partial coincidence of the polling pulses with the output pulses of the trigger reduces the counting accuracy, and as the number of inputs increases, the speed decreases as the tact pulse passes to the last trigger through a certain number of keys and, if the next pulse to the OR circuit comes from the first trigger, the time interval between these two pulses is less than the period of the clock frequency by the amount of delay in the chain of serially connected keys; therefore, the period of the clock frequency must be greater than the period of the maximum counting frequency by the amount of delay in the key chain. In addition, the impulse of demand, the passage through the keys weakens, and in order to maintain its amplitude, pairs of keys (to maintain the desired polarity of the pulses) of the amplifier stages must be included in the key chain, which further increases the delay of the polling pulses.

The proposed counter differs in that, in order to increase speed and eliminate the summation error, its inputs are additionally connected to its coincidence circuits, the outputs of the triggers with the same inputs of additional triggers, the clock inputs of which are connected to the wide clock pulses, the zero outputs are connected to the diagrams of the subsequent triggers , and single ones - with the input of their own matching circuits and with the inputs of the "OR" circuit, the output of which is connected to the input of the counting register through an additional gate, the second input all of which and the inputs of the matching circuits are connected via an inverting delay element.

Ia drawing shows a diagram of the device.

The input terminal for each pulse sequence is connected to the input of the coincidence circuit and to the setup input of trigger 1, the zero input of which is connected to the output of the coincidence circuit 2, and the single and zero outputs are connected respectively to the installation and zero inputs of additional trigger 3. Its single output is connected to another input of the matching circuit 2, and the clock inputs of the additional triggers of all 3 memory elements are connected to the input terminal for the clock pulses. The unit outputs of all additional triggers are connected via the OR 4 circuit to the input of the additional valve 5, the second input of which is connected to the output of an inverting delay element 6 that delays the leading edge of the pulse, for example, a simple rheostat inverter with a shunt output capacitance. The same output is connected to the third inputs of the matching circuit 2 of each memory element. The output of the valve 5 is connected to the input of the counter.

Each input negative pulse (inputs fa, / 3) translates the corresponding trigger 1 into one state regardless of the presence of a clock pulse that does not pass through the coincidence circuit due to the prohibition on the first and second inputs. If at the same time there is no negative clock pulse at the clock input of the additional trigger 3, this trigger is also set to one, giving permission to reset the trigger 1 to zero and through the OR 4 circuit to the clock pulse passing through the additional gate 5 to the counter.

The delay of the leading edge of this pulse is necessary so that the trigger 3, after the recording has been prohibited from the clock input, has been set to a certain state. By the arrival of a clock pulse in a single state several such triggers can be found, then the first one of them with a low zero-output potential prohibits the flashing of triggers 1 of all other memory elements. The clock pulse through the coincidence circuit 2 of the first memory element converts its trigger to zero and passes through an additional valve 5 to the counter. After the end of the clock pulse, the ban is removed from the clock input of the additional trigger 3 and it also goes to zero, thereby allowing the passage of the next clock pulse to the next memory element.

Thus, the input pulse converts the corresponding trigger 1 to the single state of the additional triggers 3, which control the additional valve 5, does not change during the time of action of the clock pulse, which ensures reliable memorization and reading of the pulses in the absence of failures and

extra pulses, tact pulses are applied to the reset of all triggers 1 and to the additional valve circuit 5 in parallel, which creates the same conditions for their passage through all channels and eliminates a decrease in speed due to grouping of output pulses.

Subject invention

A multi-input pulse counter containing a counting register, an OR circuit and triggers with coincidence circuits at zero inputs, the single trigger inputs connected to the counter inputs, characterized in that, in order to improve performance and eliminate the sum total error, the counter inputs are additionally connected to their own circuits matches, outputs of triggers - with the same inputs of additional triggers, clocked inputs of which

connected to the clock bus, the zero outputs are connected to the coincidence circuits of the subsequent triggers, and the single outputs - to the input of their matching circuits and to the inputs of the OR circuit, the output of which is connected to

the input of the counting register through an additional gate, the second input of which and the inputs of the coincidence circuits are connected via an inverting delay element.