SU1325663A1 - Digital controllable delay line - Google Patents

Abstract

The invention relates to radio engineering and can be used in radar radionavigation and telemetry, in measuring and computing. The purpose of this invention is to enhance the functionality by providing a delay, longer period of input signals. Digital adjustable delay line contains a clock pulse generator, front-edge driver of the input signal, rear edge driver of the input signal, pulse counters, shift registers, static registers, AND element blocks, OR elements, RS-triggers, I. elements 2 Il. (L

Description

The invention relates to radio engineering and can be used in radiolocation, radio navigation and telemetry, in measuring and computer engineering.

The aim of the invention is to enhance the functionality by providing a delay, longer period of input signals.

Fig. 1 shows the functional scheme of the proposed digital adjustable delay line; Fig. 2 is a diagram illustrating the operation of the device.

The digital adjustable delay line contains a generator of 1 clock pulses, a driver of the leading edge of the input signal, a driver of the rear edge of the input signal, counters 4 and 5 pulses, shift registers 6–9, static registers 10 and 11, blocks 12–15 elements, And elements OR 16-19, RS-flip-flops 20-22, elements AND 23 and 24, input 25 and output 26 tires.

The number of bits in the registers 6 and 7 of the shift, in counters 4 and 5, the number of elements And in blocks 12 and 13 elements And are selected based on the requirements of the accuracy of adjusting the amount of delay. Their increase leads to a more gradual adjustment of the delay value. The number of elements And in blocks 12 and 13 one exceeds the number of bits in shift registers 6 and 7 and is equal to the number of bits of the static register 10. The number of bits in counters 4 and 5 is defined as the logarithm of the number of bits of registers 6 and 7 shifts. The period of the signals of the generator 1 clock pulses is chosen based on the condition

GTM

Tux. n to

de T.

SCC

BX

- the period of the following signals of the generator 1 clock pulses;

- the period of the following input signals;

-dividing ratio of counters 4 and 5;

is any positive integer.

The number of bits in the registers 8 and 9 shift, the number of elements And

in blocks 14 and 15, and the number of bits in the static register i1 is determined based on the requirement of the delay value. In this case, the number of bits in the registers 8 and 9 of the shift is defined as

m

GTI

P

to

)five

20

25

thirty

35

40

45

50

55

where m

rTV

I n

the number of bits in the shift registers; the period of the following signals of the generator 1 clock pulses;

maximum delay;

counter division factor.

The number of bits in the static register I1 and the number of elements in blocks 14 and 15 by one exceeds the number of bits in registers 8 and 9 of the shift.

The device works as follows.

Before starting work, counters 4 and 5, shift registers 6-9, static registers 10 and 11, triggers 20-22 are set to zero (the reset circuits are not shown in Fig. I). In static registers 10 and 11, any of the known methods record numbers proportional to the delay. B register 10 records a number proportional to the exact part of the delay, and S register 11 is a number proportional to the coarse part of the delay. The total delay is equal to the sum of the coarse and accurate delays,

From the input bus 25, the delayed signals are fed to the driver 2 pulses of the leading edge of the input signal and to the driver 3 pulses of the trailing edge of the input signal. The impulse formed on the leading front (Fig. 2c), through one of the elements And block 12, opened at the second input by the potential from the static register 10, goes to the corresponding information input of the shift register 6. After a time determined by the frequency of the generator 1 and the number of bits of the shift register 6, the output of its last bit appears pulse (fig.2d) 5 which through the element OR 16 and one of the elements And the third block 14 is recorded in

shift register 8 and, in addition, sets trigger 20 to one state.

When the flip-flop 20 is set to one, the AND 23 element is opened at the second input and the pulse sequence from the generator 1 begins to arrive at the input of the counter 4. After the time determined by the frequency of the generator 1, the division factor of the counter 4, the number of the register bits 8 at the output of its last discharge, a pulse appears (Fig. 2 and), KOTOpbtfi, passing through the element OR 18 sets the trigger 22 to the one state (Fig. 2k).

Thus, a potential appears on the output bus 26 of the device, which is delayed in relation to the leading edge of the input signal by an amount equal to the delays in shift registers 6 and 8.

Similarly, using the shift registers 7 and 9 of the shift, the counter 5, the static register 11, the elements AND blocks 13 and 15, the pulse generated on the falling edge of the input signal is delayed (Fig.2 g, e, s, k) .

When this delayed pulse arrives at the zero input of the trigger 22, the latter is set to the zero state. An output pulse equal in duration to the input and delayed relative to it by the required amount is formed on the output bus 26 of the device (Fig. 2 l). If in registers 10 or 11 null information, then the pulses formed on the leading and trailing edges of the input signal pass through the elements AND blocks 12–15 connected by second inputs with zero bits of static registers 10 and 11, min respectively registers B and 9 shift.

Claims (1)

Thus, the design features of the proposed device make it possible to expand the functionality - to delay the input pulse sequence by a value like a smaller follow-up period so equal and greater. The duration of the output pulses is equal to the duration of the input pulses. Formula of Invention Digital adjustable delay line containing static signal , ten 15 20 25 25663 gist, clock pulse generator connected to the first inputs of the first and second elements And, the second inputs of which are connected to the single outputs of the first and second triggers, respectively, the outputs of the first and second elements And are connected to the counting inputs of the first and second pulse counters, the output of the third trigger connected to the output bus, the input bus, characterized in that, in order to extend the functionality by providing a delay, a longer period of input signals, it additionally introduces s are a static register, four shift registers, four blocks of AND elements, four OR elements, a leading edge driver and a falling front driver, with the outputs of the leading and trailing edges of the first and second elements of the first and second blocks of the And elements, the second inputs of which are connected to the corresponding outputs of the static register, the outputs of the AND elements of the first and second blocks of AND elements, except the AND elements corresponding to the first discharge of the static register and connected to The first inputs of the first and second elements OR, respectively, are connected to the corresponding one-by-one inputs of the first and second shift registers, the synchronization inputs of which are connected to the output of the clock generator, the outputs of the first and second shift registers are connected to the second inputs of the first and second elements OR, respectively. the first element OR is connected to the unit input of the first trigger 45 and to the first inputs of the elements AND of the third block of elements AND, the output of the second element AND is connected to the unit in one second trigger and the first inputs of the AND elements of the fourth QQ block of the AND elements, the second inputs of the AND elements of the third and fourth blocks of the AND elements are connected to the corresponding outputs of the additional static register, the outputs of the AND elements of the third and fourth blocks of the AND elements, except the AND elements corresponding to the first bit do additional static register and connected to the first inputs of the respective 30 35 40 55 The third and fourth elements OR are connected to the one-by-one inputs of the third and fourth shift registers, respectively, whose synchronization inputs are connected to the outputs of the first and second counters, the outputs of the third and fourth shift registers The hirs are connected to the second inputs of the third and fourth elements, respectively, OR “whose outputs are connected to the single and 5 zero inputs of the third trigger, respectively, and the inputs of the front and rear edges of the drivers are connected to the input bus. 26 1 LD