SU926672A2 - Frequency pulse multiplying/dividing device - Google Patents

Description

The invention relates to automation, computing, and measurement technology, intended to multiply the magnitudes given by the pulse frequency. According to the main author. St. No. 278233 is known a frequency-pulse multiplier-separating device containing counters, a register, prohibition circuits and a delay device, in which the F, F, Fj frequencies are converted to the output frequency F. By the formula In this device the first input of the device (pg / which receives pulses with frequency F) is connected to informational inputs of the circuits of the first group, the control inputs of which are connected to the discharge outputs of the first counter, and the outputs are connected to the discharge inputs of the register, the discharge outputs of the register are connected to the control inputs of the prohibition circuit of the second group, the information inputs of which are connected to the output of the second counter, the counting input of which is connected to the second input of the device (through which impulses of frequency Fi are received), and the discharge inputs are connected to the outputs of the prohibition of the second group. The first input of the device through the delay device is connected to the reset circuit of the first counter, to the counting input, which receives pulses with a frequency F. The output of the second counter-in-. The output of the device is 1. A disadvantage of the known device is the low output frequency as compared to the frequencies of the factors, which leads to a low speed of the device and a large dynamic error resulting from the loss of information about the periods of the frequency of the first factor and divider. The purpose of the invention is to reduce the dynamic error and increase the speed of the device. The goal is achieved by the fact that the frequency-pulse multiplier of the TO-separating device additionally contains a second register, a third counter, a third and fourth groups. A prohibition circuit, a second delay device, and an OR terminal, and the second input of the device

the counter input of the third counter, the bit outputs of which are connected to the information inputs of the prohibition circuits of the third group, whose control inputs are connected to the bit outputs of the second register, and the outputs to the inputs of the OR element inputs, the output of which is connected to the counting input of the first counter, the bit outputs of the third counter are connected to the control inputs of the fourth group prohibition circuits, the outputs of which are connected to the bit inputs of the second register, and the information inputs are connected to the third input of the device, which Without a second delay delay device is connected to the reset circuit of the third counter.

The drawing shows the block diagram of the device.

The frequency-pulse multiplying device contains, counters 1 and 2, prohibition schemes 3 and 4, register 5, delay device b, counter 7, register 8, prohibition schemes 9 and 10, delay device 11, element OR 12.

The inputs of counters 2 and 7 receives the frequency F ,,. The input of the device, to which the frequency FS arrives, is connected via a delay device 11 to the reset circuit of counter 7, the bit outputs of which are connected to the information inputs of the inhibitor circuits 9 and the control inputs of the inhibit circuits 10. The information inputs of the inhibit circuits 10 are connected to the input of the device to which the frequency Fj- arrives, and the outputs are connected to the bit inputs of the register 8, the bit outputs of which are connected to the control inputs of the ban circuits 9, the outputs of which are connected to the inputs of the element OR 12, the output which is connected to the counting input of the counter 1, the bit outputs of which are connected to the control inputs of the inhibit circuits 3, the information inputs of which are connected to the input of the device to which the frequency F arrives, this input through the device 6 Inen with the reset circuit of the counter 1, the outputs of the prohibition circuits 3 are connected to the bit inputs of the register 5, the bit outputs of which are connected to the control inputs of the prohibition circuits 4, the outputs of which are connected to the bit inputs of the counter 2, the counting input of which is connected to the device input, to which the frequency F is fed, and the output at which the output frequency F c is formed is connected to the information inputs of the prohibition circuit 4.

The device works as follows.

When the next pulse of the input signal Fg arrives at the input of the device, the number from the counter 7 is transferred to the register 8, and the counter 7 itself is reset to zero after the time determined by the delay device 11.

Since PS Vs time Tg in counter 7 accumulates the number of pulses Ng received at the following frequency Fj.

N5 Fj. TS (2)

The counter 7, the register 8, the prohibition scheme 9 and the element OR 12 constitute a binary multiplier, at the output of which a frequency-pulse sequence with a pulse frequency F is generated.

NsJJEl

(3)

F - 2

where n is the number of binary bits of counters and device registers. The pulse sequence with a frequency Fg is fed to the input of counter 1.

When the next pulse F of the input signal arrives at the input of the device, the number from the counter 1 is transferred to the register 5 by the reverse code, and the counter 1 itself is reset to zero after the time 6 of the delay device 6 is reset. Since, fT time T into counter 1 passes the number of pulses NY:

(four)

Nl T. F;

Counter 2, register 5. and prohibition schemes 4 form a controlled frequency divider FJ, at the output of which a pulse frequency sequence is formed with a pulse frequency

- - 1b

(five)

I - - N,

and taking into account expressions (1), (3) and (4) D)

- -2

F F - F 1 5

This device has a higher speed than the known one and performs a multiplication operation with a much lower dynamic error.

An increase in the frequency of the output frequency-pulse sequence F ,, and, consequently, of speed, is achieved due to the fact that the ratio of the output frequencies of this device and that known, as can be seen from a comparison of formulas (1) and (5), is

Fk

(6)

An increase in the frequency of the output signal in this device as compared to the output frequency of the known one also leads to a decrease in its dynamic error, since this increases the frequency of information flow and periods of frequencies-cat.

Claims (1)

Claim -Pulse-frequency multiplier divider according to ed. St. No. 278233, characterized in that, in order to reduce the dynamic error and increase the speed of the device, it additionally contains a second register, a third counter, a third and a fourth corpse of the inhibit circuits, a second delay device and an OR element, the second input of the device being connected with it, the input of the third counter, the bit outputs of which are connected to the information inputs of the prohibition circuits of the third group, whose control inputs are connected to the bit outputs of the second register, and the outputs with the inputs of the OR element, output which is connected to the counting input of the first counter, the bit outputs of the third meter are connected to the control inputs of the fourth group inhibit circuits, the outputs of which are connected to the bit inputs of the second register, and the information inputs are connected to the third input of the device, 20 which is connected to the circuit through the second delay device reset the third. counter.