SU1312727A1 - Digital filter with binary time quantization - Google Patents

Abstract

The invention can be: i) and i.-Si for optimal fi: 1 sintation 1 (1) and a small signal-to-noise ratio. The purpose of the invention 11 high-speed performance. The device contains a time quantizer) I. register 2 response codes, resistor 3 ghvsha. block 4 of equivalence el-points, k peisepcHB-counters 7, Mr. 11 tact and, 1. IMR..I, owls. The distributor of 12 is named nu.chs, k multiplexers в, three registers 5, 8 and 10, the adder 9. 2 и.1. 9 (L oo go yu

Description

The invention relates to radio engineering and can be used to optimally filter signals with a low signal-to-noise ratio.

The purpose of the invention is to increase speed.

FIG. 1 shows the structural electrical circuit of the proposed digital filter; in fig. 2 - diagrams explaining his work.

The digital filter with binary quantization of the signal contains a time quantizer 1, a register 2 response code, a shift register 3, a unit of equivalence elements, the first register 5, K multiplexers 6, K reversible counters 7, the second register 8, adder 9, the third register K), 11 clock pulses and distribute. 12 pulses.

Digital filter with binary quantization of the signal works as follows.

The input signal is quantized in time quantizer I by pulses obtained by dividing the frequency of the oscillator 1 1 (Fig. 2a) with the distributor 12 pulses (Fig. 2 b). The same pulse. They shift the information in the shift register 3. The outputs of the shift register 3 are connected to the inputs of the block of 4 equivalence elements, the second inputs of which are connected to the register 2 of the response code. Block 4 elements of equivalence implements the function. Therefore, if the signal code coincides with the response code, then the output of block 4 of equivalence will be the value of a logical unit. The summation of the 11 values is produced by reversible counters 7, at the input of which there are. 1116xors 6. From the outputs of register 5, information is fed to the inputs of multiplexers in 6 groups of seven bits.

Depending on the code received at the control inputs of the multiplexer 6 (Fig. 2c) from the distributor 12 pulses, it produces a serial connection of the bits of register 5 with the control input of the reversible counter 7. Uni-. 1 and the code is 000, then the zero channel is turned on; with a grounded input, at which time reversible meters 7 are zeroed (Fig. 26). With code 001, the first bits of each group are turned on, and the first pulse (Fig. 20) records the value into a reversible counter 7, with

2

2d) second bits

15

20

code 010 (fig., etc. to seven.

Reversible counters 7 are made on four-bit synchronous binary counters, with the three least significant bits representing the sum of the counted zeros and ones, and the most significant bits representing the sum sign. From the outputs of the reversible counters 7, the obtained values are written to the register 8 (Fig. 26), from the outputs of which 10 are fed to the input of the adder 9. The output of the dry mat 9 is connected to the register 10, in which the final value of the sum is received.

Claims (1)

Invention Formula Digital signal with binary quantization of the signal, containing a clock pulse generator, serially connected time quantizer, the signal input of which is the input of a digital filter with binary signal quantization, shift register, the clock input of which is connected to the control input of the quantizer, and a block of equivalence elements, second inputs which are connected to the outputs of the bits of the register of the response code, K reversible counters, where, characterized in that, in order to improve speed, the distributor impulses, K multiplexers, the first reg istr and serially connected second register, adder and third register, the output of which is the output of a digital filter with binary quantization of the signal, the inputs of the first register connected to the outputs of the block of equivalence elements, the outputs of the first register connected to 35 corresponding information inputs To multiplexers, the outputs of which are connected to the inputs of addition-subtraction To reversible counters, besides, the output of the clock generator is connected to the input The dd of the distributor and pulses, the group of the first outputs of which is the outputs of control pulses and connected to the control inputs K of the multiplexers, the second output is the output of the installation pulses and connected to the reset inputs K 45 counters and clock inputs of the shift register, the first, second and third registers, the third output is the output of clock pulses and is connected to counting inputs K of reversible counters, the bit outputs of which are connected to the inputs of the second register. thirty ta xcj J j C4J CO